KR100202188B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100202188B1 KR100202188B1 KR1019960046428A KR19960046428A KR100202188B1 KR 100202188 B1 KR100202188 B1 KR 100202188B1 KR 1019960046428 A KR1019960046428 A KR 1019960046428A KR 19960046428 A KR19960046428 A KR 19960046428A KR 100202188 B1 KR100202188 B1 KR 100202188B1
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- layer
- interlayer insulating
- mask
- insulating layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 111
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 22
- 239000005368 silicate glass Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로서 메모리소자들이 형성된 셀영역과 구동회로가 형성된 주변영역으로 구분된 반도체기판 상에 제1층간절연층을 형성하는 공정과, 상기 제1층간절연층 상에 도전성금속층과 이 도전성금속층 상에 보호층을 형성하는 공정과, 상기 보호층 상에 흐름성이 좋은 물질로 표면이 평탄한 마스크층을 형성하는 공정과, 상기 마스크층과 보호층의 소정 부분을 제외한 나머지 부분을 상기 도전성금속층이 노출되도록 선택적으로 식각하는 공정과, 상기 패터닝된 마스크층 및 보호층을 마스크로 사용하여 상기 도전성금속층의 노출된 부분을 상기 제1층간절연층이 노출되도록 식각하여 금속배선을 형성하는 공정을 구비한다. 따라서, 금속배선을 2번의 식각 공정과 1번의 스트립 공정으로 형성하므로 공정이 단순해질 뿐만 아니라 파티클의 감소로 인해 수율이 향상되며, 또한, 마스크층을 제거하지 않고 플로우시켜 제2층간절연층을 형성하므로 공정수 및 제조 원가가 감소된다.The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a first interlayer insulating layer on a semiconductor substrate divided into a cell region in which memory elements are formed and a peripheral region in which a driving circuit is formed; A step of forming a protective layer on the conductive metal layer and the conductive metal layer, a step of forming a mask layer having a flat surface with a material having good flowability on the protective layer, Etching the exposed portion of the conductive metal layer using the patterned mask layer and the protective layer as a mask to expose the first interlayer insulating layer to expose the metal wiring, To form a film. Therefore, since the metal wiring is formed by two etching processes and one strip process, not only the process becomes simple but also the yield is improved due to the reduction of the particles, and the second interlayer insulating layer is formed by flowing without removing the mask layer The process water and the manufacturing cost are reduced.
Description
제1도(a) 내지 (e)는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정도.FIGS. 1 (a) to 1 (e) are process drawings showing a manufacturing method of a semiconductor device according to the prior art.
제2도(a) 내지 (d)는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정도.2 (a) to (d) are process drawings showing a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
31 : 기판 33 : 제1층간절연층31: substrate 33: first interlayer insulating layer
35 : 도전성금속층 37 : 보호층35: conductive metal layer 37: protective layer
39, 41 : 제1 및 제2마스크층 43 : 감광막39, 41: first and second mask layers 43:
45 : 금속배선 47 : 제2층간절연층45: metal wiring 47: second interlayer insulating layer
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 셀영역과 주변영역의 단차가 큰 절연층 상에 금속 배선을 공정 수의 감소와 그에 따른 입자의 감소로 수율을 향상시킬 수 있는 반도체장치의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving the yield by reducing the number of process steps and decreasing the number of particles of metal wiring on an insulating layer having a large step between a cell region and a peripheral region And a manufacturing method thereof.
반도체장치가 고집적화 및 고밀도화에 따라 반도체장치는 메모리소자들은 큰 커패시턴스를 가져야 하므로 커패시터의 표면적이 증가되어야 한다. 그러므로, 반도체장치는 메모리소자들이 형성되는 셀영역과 이 셀영역의 메모리소자들을 구동하는 구동회로가 형성되는 주변영역의 단차가 증가되며, 이에 따라, 커패시터와 이 후의 1차 금속배선 사이를 절연시키는 층간절연층도 셀영역과 주변영역의 단차가 증가된다. 그러므로, 1차 금속배선을 형성할 때 마스크로 사용되는 감광막은 셀영역과 주변영역에서 두께가 다르게 형성되므로 노광 공정이 어려울 뿐만 아니라 1차 금속배선을 일정한 폭을 갖도록 형성하기 어렵다. 따라서, 이러한 문제점을 해결하기 위해 다층 감광막(Multi Layer Resist)을 사용하는 방법이 제시되었다.As the semiconductor device is highly integrated and densified, the semiconductor device must have a large capacitance so that the surface area of the capacitor must be increased. Therefore, in the semiconductor device, the step between the cell region in which the memory elements are formed and the peripheral region in which the driving circuit for driving the memory elements in the cell region are formed is increased, thereby insulating the capacitor from the subsequent primary metal wiring The step difference between the cell region and the peripheral region also increases in the interlayer insulating layer. Therefore, since the photoresist used as a mask in forming the primary metal interconnection has a different thickness in the cell region and the peripheral region, it is difficult to form the primary metal interconnection with a constant width as well as the exposure process. Therefore, a method of using a multi-layered photoresist (multi-layered photoresist) has been proposed to solve such a problem.
제1도(a) 내지 (e)는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정도이다.1 (a) to 1 (e) are process drawings showing a method of manufacturing a semiconductor device according to the prior art.
제1도(a)를 참조하면, 메모리소자들(도시되지 않음)이 형성된 셀영역(S1)과 구동회로(도시되지 않음)가 형성된 주변영역(P1)으로 구분된 반도체기판(11) 상에 BPSG(Boro-Phosphor Silicate Glass) 등을 두껍게 증착하여 제1층간절연층(13)을 형성한다. 그리고, 제1층간절연층(13) 상에 알루미늄 등의 도전성금속층(15)을 증착하고, 이 도전성금속층(15) 상에 제1감광막(17)을 도포한다. 상기에서, 제1감광막(17)을 회전 도포법으로 도포하므로 상부 표면이 평탄하게 된다.Referring to FIG. 1 (a), on a semiconductor substrate 11 divided into a cell region S1 formed with memory elements (not shown) and a peripheral region P1 formed with a driving circuit (not shown) BPSG (Boro-Phosphor Silicate Glass) or the like is thickly deposited to form the first interlayer insulating layer 13. [ A conductive metal layer 15 such as aluminum is deposited on the first interlayer insulating layer 13 and the first photosensitive film 17 is coated on the conductive metal layer 15. Since the first photoresist layer 17 is applied by the spin coating method, the upper surface is flat.
제1도(b)를 참조하면, 제1감광막(17) 상에 산화실리콘 등을 증착하여 마스크층(19)을 형성하고, 이 마스크층(19) 상에 제2감광막(21)을 도포한다. 그리고, 제2감광막(21)을 노광 및 현상하여 마스크층(19)의 소정 부분을 노출시킨다.Referring to FIG. 1 (b), a mask layer 19 is formed by depositing silicon oxide or the like on the first photoresist layer 17, and the second photoresist layer 21 is coated on the mask layer 19 . Then, the second photoresist layer 21 is exposed and developed to expose a predetermined portion of the mask layer 19.
제1도(c)를 참조하면, 제2감광막(21)을 마스크로 사용하여 마스크층(19)의 노출된 부분을 제1감광막(17)이 노출되도록 식각한다. 그리고, 제2감광막(21)을 스트립(strip)하여 제거한 후 마스크층(19)이 형성되지 않은 제1감광막(17)의 노출된 부분을 마스크층(15)이 노출되도록 제거하여 패터닝한다. 상기에서, 제2감광막(21) 제거시 제1감광막(17)이 노광되지 않았으므로 마스크층(19)이 형성되지 않아 노출된 부분은 제거되지 않는다.Referring to FIG. 1 (c), the exposed portion of the mask layer 19 is etched to expose the first photoresist layer 17 using the second photoresist layer 21 as a mask. After the second photoresist layer 21 is stripped off, the exposed portion of the first photoresist layer 17, on which the mask layer 19 is not formed, is removed and patterned to expose the mask layer 15. Since the first photoresist layer 17 is not exposed when the second photoresist layer 21 is removed, the exposed portion is not removed because the mask layer 19 is not formed.
제1도(d)를 참조하면, 패터닝된 제1감광막(17) 상에 잔류하는 마스크층(19)을 스트립하여 제거한다. 그리고, 제1감광막(17)를 마스크로 사용하여 제1층간절연층(13)이 노출되도록 도전성금속층(15)을 패터닝하여 금속배선(23)을 형성한다.Referring to FIG. 1 (d), the remaining mask layer 19 on the patterned first photoresist layer 17 is removed by stripping. The metal wiring 23 is formed by patterning the conductive metal layer 15 so that the first interlayer insulating layer 13 is exposed using the first photosensitive film 17 as a mask.
제1도(e)를 참조하면, 금속배선(23) 상에 잔류하는 제1감광막(17)을 스트립하여 제거한다. 그리고, 상술한 구조의 전 표면에 표면이 평탄하도록 SOG(Spin On Glass) 또는 USG(Undoped Silicate Glass) 등을 증착하여 제2층간절연층(25)을 형성한다.Referring to FIG. 1E, the first photoresist layer 17 remaining on the metal wiring 23 is removed by stripping. Then, a second interlayer insulating layer 25 is formed by depositing SOG (Spin On Glass) or USG (Undoped Silicate Glass) or the like on the entire surface of the above-described structure so as to have a flat surface.
그러나, 상술한 종래의 반도체장치의 제조방법은 셀영역과 주변영역에 증착된 제1층간절연층 상에 금속배선을 형성하기 위해 제1 및 제2감광막과 마스크층을 다수 번의 식각 및 스트립 공정이 필요하므로 공정이 복잡하고 파티클(particle)의 발생이 증가하여 수율이 저하되는 문제점이 있었다.However, in the above-described conventional semiconductor device manufacturing method, the first and second photoresist layers and the mask layer are subjected to a plurality of etching and strip processes to form a metal interconnection on the first interlayer insulating layer deposited in the cell region and the peripheral region There is a problem that the process is complicated and the generation of particles is increased and the yield is lowered.
따라서, 본 발명의 목적은 식각 및 스트립 공정을 감소시켜 공정이 간단한 반도체장치의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device that is simple in process by reducing etching and stripping processes.
본 발명의 다른 목적은 파티클의 발생을 감소시켜 수율을 향상시킬 수 있는 반도체장치의 제조방법을 제공함에 있다.It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing the generation of particles and improving the yield.
본 발명의 또 다른 목적은 마스크층을 제거하지 않고 플로우시켜 제2층간절연층을 형성하여 공정 단계 및 제조 원가를 감소시킬 수 있는 반도체장치의 제조방법을 제공함에 있다.It is still another object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing a process step and a manufacturing cost by forming a second interlayer insulating layer by flowing without removing a mask layer.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 메모리소자들이 형성된 셀영역과 구동회로가 형성된 주변영역으로 구분된 반도체기판 상에 제1층간절연층을 형성하는 공정과, 상기 제1층간절연층 상에 도전성금속층과 이 도전성금속층 상에 보호층을 형성하는 공정과, 상기 보호층 상에 흐름성이 좋은 물질로 표면이 평탄한 마스크층을 형성하는 공정과, 상기 마스크층과 보호층의 소정 부분을 제외한 나머지 부분을 상기 도전성 금속층이 노출되도록 택적으로 식각하는 공정과, 상기 패터닝된 마스크층 및 보호층을 마스크로 사용하여 상기 도전성금속층의 노출된 부분을 상기 제1층간절연층이 노출되도록 식각하여 금속배선을 형성하는 공정을 구비한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first interlayer insulating layer on a semiconductor substrate divided into a cell region in which memory elements are formed and a peripheral region in which a driving circuit is formed; A step of forming a protective layer on the conductive metal layer and the conductive metal layer on the interlayer insulating layer, a step of forming a mask layer having a smooth surface on the protective layer with a good flow property, Etching the exposed portions of the conductive metal layer so that the first interlayer insulating layer is exposed using the patterned mask layer and the protective layer as a mask; And forming a metal wiring by etching.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.
제2도(a) 내지 (d)는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정도이다.FIGS. 2 (a) to 2 (d) are process drawings showing a method of manufacturing a semiconductor device according to the present invention.
제2도(a)를 참조하면, 메모리소자들(도시되지 않음)이 형성된 셀영역(S2)과 구동회로(도시되지 않음)가 형성된 주변영역(P2)으로 구분된 반도체기판(31) 상에 BPSG(Boro-Phosphor Silicate Glass) 등을 두껍게 증착하여 제1층간절연층(33)을 형성한다. 그리고, 제1층간절연층(33) 상에 알루미늄 등의 도전성금속층(35)을 증착하고, 이 도전성금속층(35) 상에 PECVD(Plasma Enhanced Chemical Vapor Deposition) 등의 방법으로 TEOS(tetraethyl orthosilicate), SiH40X또는 SiO2등을 2001000정도의 두께로 증착하여 보호층(37)을 형성한다.Referring to FIG. 2 (a), on a semiconductor substrate 31 divided into a cell region S2 formed with memory elements (not shown) and a peripheral region P2 formed with a driver circuit (not shown) BPSG (Boro-Phosphor Silicate Glass) or the like is thickly deposited to form the first interlayer insulating layer 33. [ A conductive metal layer 35 made of aluminum or the like is deposited on the first interlayer insulating layer 33 and is formed on the conductive metal layer 35 by a method such as PECVD (Plasma Enhanced Chemical Vapor Deposition) SiH 4 O X, SiO 2 , 1000 The protective layer 37 is formed.
제2도(b)를 참조하면, 보호층(37) 상에 흐름성이 좋은 SOG, 예를 들면, 실록산(siloxane) 또는 실리케이트(silicate) 등을 한 층 이상, 예를 들면, 연속해서 2층 도포하여 제1 및 제2마스크층(39)(41)을 형성한다. 상기에서 제1 및 제2마스크층(39)(41)을 총 두께가 40006000정도의 두께가 되도록 각각 20003000정도의 두께로 도포하여 형성한다. 이 때, 흐름성이 좋은 제1 및 제2마스크층(39)(41)은 단차에 의해 셀영역(S2) 보다 주변영역(P2)에 두껍게 형성된다. 그러므로, 제2마스크층(41)의 표면은 평탄하게 된다. 상기에서, 제1마스크층(39) 하부의 보호층(37)은 제1 및 제2마스크층(39)(41)을 이루는 SOG가 도전성금속층(35)과 반응되는 것을 방지한다. 그리고, 제2마스크층(41) 상에 감광막(43)을 1.01.5m 정도의 두께로 도포한 후 노광 및 현상하여 제2마스크층(41)의 소정 부분을 노출시킨다.Referring to FIG. 2 (b), SOG having good flowability, for example, siloxane or silicate may be formed on the protective layer 37 by one or more layers, for example, The first and second mask layers 39 and 41 are formed. In the above, the first and second mask layers 39 and 41 have a total thickness of 4000 6000 2000 < / RTI > 3000 As shown in FIG. At this time, the first and second mask layers 39 and 41 having good flowability are formed thicker in the peripheral region P2 than the cell region S2 due to the step difference. Therefore, the surface of the second mask layer 41 becomes flat. The protective layer 37 under the first mask layer 39 prevents the SOG constituting the first and second mask layers 39 and 41 from reacting with the conductive metal layer 35. On the second mask layer 41, the photoresist film 43 is formed to a thickness of 1.0 1.5 m, and exposed and developed to expose a predetermined portion of the second mask layer 41.
제2도(c)를 참조하면, 감광막(43)을 마스크로 사용하여 제2 및 제1마스크층(41)(39)과 보호층(37)을 순차적으로 이방성 식각 방법으로 패터닝하여 도전성금속층(35)을 노출시킨다.Referring to FIG. 2 (c), the second and first mask layers 41 and 39 and the protective layer 37 are sequentially patterned by an anisotropic etching method using the photoresist 43 as a mask to form a conductive metal layer 35 are exposed.
제2도(d)를 참조하면, 감광막(43)을 스트립하여 제거한 후 제2 및 제1마스크층(41)(39)과 보호층(37)을 마스크로 사용하여 도전성금속층(33)을 패터닝하여 금속배선(45)을 형성한다. 그리고, 패터닝된 금속배선(45) 상에 잔류하는 제1 및 제2마스크층(39)(41)을 플로우(flow)시켜 제2층간절연층(47)을 형성한다. 상기에서, 제1 및 제2마스크층(39)(41)은 100450정도의 온도를 가하면 양호한 흐름 특성에 의해 플로우되어 제2층간절연층(47)이 형성된다. 이 때, 셀영역(S2)과 주변영역(P2)의 단차에 의해 제2층간절연층(47)은 셀영역(S2) 보다 주변영역(P2)이 두껍게 형성되어 표면이 평탄하게 되는 데, 보호층(37)은 하부의 금속배선(45)이 상부의 제2층간절연층(47)과 반응하는 것을 방지한다.Referring to FIG. 2 (d), the conductive metal layer 33 is patterned using the second and first mask layers 41 and 39 and the protective layer 37 as a mask after the photoresist layer 43 is stripped and removed. Thereby forming a metal wiring 45. Then, the second interlayer insulating layer 47 is formed by flowing the first and second mask layers 39 and 41 remaining on the patterned metal interconnection 45. In the above, the first and second mask layers 39 and 41 are made of 100 450 The second interlayer insulating layer 47 is formed by flowing with a good flow characteristic. At this time, the second interlayer insulating layer 47 is formed to have a thicker peripheral region P2 than the cell region S2 due to the difference in level between the cell region S2 and the peripheral region P2, The layer 37 prevents the underlying metal interconnection 45 from reacting with the upper second interlayer insulating layer 47.
상술한 바와 같이 본 발명에 따른 반도체장치의 제조방법은 셀영역과 주변영역으로 구분된 반도체기판 상에 두껍게 증착된 제1층간절연층상에 도전성금속층 및 보호층을 형성한 후 이 보호층 상에 흐름성이 좋은 SOG를 도포하여 마스크층을 형성하고 이 마스크층 상의 소정 부분에 감광막을 형성한다. 그리고, 감광막을 마스크로 사용하여 마스크층과 보호층을 순차적으로 패터닝하고 이 감광막을 제거한 후 마스크층과 보호층을 마스크로 사용하여 도전성금속층을 패터닝하여 금속배선을 형성하고 이 패터닝된 금속배선 상에 잔류하는 마스크층을 플로우시켜 제2층간절연층을 형성한다.As described above, the method of manufacturing a semiconductor device according to the present invention includes forming a conductive metal layer and a protective layer on a first interlayer insulating layer which is thickly deposited on a semiconductor substrate divided into a cell region and a peripheral region, A good SOG is applied to form a mask layer, and a photoresist layer is formed on a predetermined portion of the mask layer. Then, the mask layer and the protective layer are sequentially patterned using the photoresist layer as a mask, and the photoresist layer is removed. Then, the metal layer is patterned by using the mask layer and the protective layer as a mask to form metal wirings, The residual mask layer is flowed to form the second interlayer insulating layer.
따라서, 본 발명은 금속배선을 2번의 식각 공정과 1번의 스트립 공정으로 형성하므로 공정이 단순해질 뿐만 아니라 파티클의 감소로 인해 수율이 향상되는 잇점이 있다. 또한, 마스크층을 제거하지 않고 플로우시켜 제2층간절연층을 형성하므로 공정 수 및 제조 원가가 감소되는 잇점이 있다.Accordingly, since the metal wiring is formed by two etching processes and one strip process, not only the process is simplified but also the yield is improved due to reduction of particles. Further, since the second interlayer insulating layer is formed by flowing without removing the mask layer, there is an advantage that the number of steps and the manufacturing cost are reduced.
Claims (7)
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