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KR100209763B1 - Method for manufacturing of semiconductor package - Google Patents

Method for manufacturing of semiconductor package Download PDF

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Publication number
KR100209763B1
KR100209763B1 KR1019970002247A KR19970002247A KR100209763B1 KR 100209763 B1 KR100209763 B1 KR 100209763B1 KR 1019970002247 A KR1019970002247 A KR 1019970002247A KR 19970002247 A KR19970002247 A KR 19970002247A KR 100209763 B1 KR100209763 B1 KR 100209763B1
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South Korea
Prior art keywords
manufacturing
semiconductor package
tape
lead frame
semiconductor chip
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KR1019970002247A
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Korean (ko)
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KR19980066591A (en
Inventor
김조한
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구본준
엘지반도체주식회사
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Priority to KR1019970002247A priority Critical patent/KR100209763B1/en
Publication of KR19980066591A publication Critical patent/KR19980066591A/en
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Publication of KR100209763B1 publication Critical patent/KR100209763B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 반도체 패키지의 제조방법에 관한 것으로 특히, 생산성 및 신뢰성을 향상시키도록 한 반도체 패키지의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package to improve productivity and reliability.

이와 같은 본 발명의 반도체 패키지의 제조방법은 인너 리드가 형성된 리드 프레임의 패들에 반도체 칩을 접착시키는 공정과, 상기 반도체 칩과 인너 리드를 전기적으로 연결하는 공정과, 상기 리드 프레임이 랜드에 실장될 수 있도록 패턴이 형성된 테이프를 접합하는 공정과, 상기 반도체 칩을 보호하기 위해 몰딩하는 공정과, 상기 테이프를 제거하는 공정을 포함하여 형성함을 특징으로 한다.Such a method of manufacturing a semiconductor package according to the present invention includes a step of bonding a semiconductor chip to a paddle of a lead frame having an inner lead, electrically connecting the semiconductor chip and the inner lead, and the lead frame to be mounted on a land. And a step of bonding the tape having a pattern formed thereon, a step of molding to protect the semiconductor chip, and a step of removing the tape.

Description

반도체 패키지의 제조방법Manufacturing method of semiconductor package

본 발명은 반도체 패키지의 제조방법에 관한 것으로 특히, 생산성 및 신뢰성을 향상시키도록 한 반도체 패키지의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package to improve productivity and reliability.

일반적으로 반도체 소자의 제조공정시 웨이퍼에 집적회로를 형성하는 FAB공정(Fabrication process)을 완료한 후에는 웨이퍼상에 만들어진 각 칩을 서로 분리시키는 다이싱(Dicing)과, 분리된 각 칩을 리드 프레임(Lead Frame)의 다이 본딩 패드에 안착시키는 칩 본딩(Chip Bonding)과, 칩 위의 본딩 패드(Bonding Pad)와 리드 프레임의 인너리드(Inner Lead)를 전기적으로 접속시키는 와이오 본딩(Wire Bonding)을 순차적으로 수행한 후 회로를 보호하기 위해 몰딩(Molding)을 수행하게 된다.In general, after the FAB process (Fabrication process) for forming an integrated circuit on a wafer during the manufacturing process of a semiconductor device is completed, dicing (Dicing) to separate each chip made on the wafer, and each separated chip lead frame (Chip Bonding) to be seated on the die bonding pad of the (Lead Frame), and Wire Bonding to electrically connect the Bonding pad on the chip and the inner lead of the lead frame After sequentially performing, molding is performed to protect the circuit.

또한, 몰딩을 수행한 후에는 리드 프레임의 써포트 바(Support Bar) 및 댐 바(Dam Bar)를 자르는 트리밍(Trimming)과 아웃 리드(Out Lead)를 소정의 형상으로 성형하는 포밍(Forming)을 차례로 수행하게 되며 트리밍 및 포밍을 실시함으로써 패키지 공정을 완료하게 된다.In addition, after molding, trimming to cut the support bar and the dam bar of the lead frame and forming the out lead to a predetermined shape are sequentially performed. The package process is completed by trimming and forming.

도 1은 종래의 반도체 패키지를 나타낸 종단면도이다.1 is a longitudinal cross-sectional view showing a conventional semiconductor package.

종래의 반도체 패키지는 도 1에 도시된 바와같이 인너 리드(12)가 형성된 패키지 본체( 이하, PCB라고 한다. 여기서 PCB는 Printed Circuit Board)(11)의 패들(13)상에 플라스틱 접착제에 의해 본딩된 반도체 칩(14)과, 상기 PCB(11)의 이면에 일정한 간격을 갖고 상기 PCB(11)를 견고히 고정시키는 솔더 볼(Solder Ball)(15)과, 상기 인너 리드(12)와 상기 반도체 칩(14)을 전기적으로 연결하는 금속 와이어(Metal Wire)(16)와, 상기 금속 와이어(16)를 포함한 상기 반도체 칩(14)을 몰딩하는 EMC(Epoxy Molding Compound)(17)로 이루어진다.The conventional semiconductor package is referred to as a package body (hereinafter referred to as a PCB) in which an inner lead 12 is formed as shown in Fig. 1, where the PCB is bonded by a plastic adhesive on the paddle 13 of the printed circuit board 11. The semiconductor chip 14, a solder ball 15 for firmly fixing the PCB 11 at regular intervals on the back surface of the PCB 11, the inner lead 12 and the semiconductor chip. A metal wire 16 electrically connecting the 14 and an epoxy molding compound 17 which molds the semiconductor chip 14 including the metal wire 16.

그러나 이와 같은 종래의 반도체 패키지에 있어서 다음과 같은 문제점이 있었다.However, these conventional semiconductor packages have the following problems.

첫째, PCB의 두께가 얇기 때문에 패키지의 휨에 의한 불량이 발생한다.First, since the PCB is thin, defects due to the bending of the package occur.

둘째, PCB와 플라스틱 접착제와의 계면에서 박리 발생으로 패키지의 신뢰성이 떨어진다.Second, peeling occurs at the interface between the PCB and the plastic adhesive, resulting in poor package reliability.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 패키지의 불량을 방지하고 높은 신뢰성을 갖는 반도체 패키지의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a semiconductor package having a high reliability to prevent defects of the package to solve the above problems.

도 1은 종래의 반도체 패키지를 나타낸 종단면도1 is a vertical cross-sectional view showing a conventional semiconductor package

도 2는 인너 리드가 형성된 리드 프레임을 나타낸 레이아웃도2 is a layout diagram illustrating a lead frame having inner leads formed therein;

도 3은 랜드가 형성되도록 패턴이 형성된 테이프를 나타낸 레이아웃도3 is a layout diagram showing a tape in which a pattern is formed so that lands are formed;

도 4a - 도 4d는 본 발명에 의한 반도체 패키지의 제조방법을 나타낸 공정단면도4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to the present invention.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 패키지의 제조방법은 인너 리드가 형성된 리드 프레임의 패들에 반도체 칩을 접착시키는 공정과, 상기 반도체 칩과 인너 리드를 전기적으로 연결하는 공정과, 상기 리드 프레임이 랜드에 실장될 수 있도록 패턴이 형성된 테이프를 접합하는 공정과, 상기 반도체 칩을 보호하기 위해 몰딩하는 공정과, 상기 테이프를 제거하는 공정을 포함하여 형성함을 특징으로 한다.The method of manufacturing a semiconductor package of the present invention for achieving the above object comprises the steps of adhering a semiconductor chip to the paddle of the lead frame in which the inner lead is formed, the step of electrically connecting the semiconductor chip and the inner lead, and the lead Forming a tape to form a pattern so that the frame can be mounted on the land, molding to protect the semiconductor chip, and the step of removing the tape, characterized in that formed.

도 2는 인너 리드가 형성된 리드 프레임을 나타낸 레이아웃도이고, 도 3은 랜드가 형성되도록 패턴이 형성된 테이프이다.2 is a layout diagram illustrating a lead frame having inner leads, and FIG. 3 is a tape in which patterns are formed so that lands are formed.

그리고 도 4a - 도 4d는 본 발명에 의한 반도체 패키지의 제조방법을 나타낸 공정단면도이다.4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to the present invention.

먼저, 도 4a에 도시된 바와같이 인너 리드(Inner Lead)(21)와 아웃 리더(Out Lead))(22)가 형성되어 있는 리드 프레임의 패들(23)상에 접착제(24)를 이용하여 반도체 칩(25)을 부착한다.First, as shown in FIG. 4A, a semiconductor is formed by using an adhesive 24 on a paddle 23 of a lead frame in which inner leads 21 and out leads 22 are formed. The chip 25 is attached.

그리고 상기 인너 리드(21)와 상기 반도체 칩(25)을 금속 와이어(26)를 이용하여 전기적으로 연결한다.The inner lead 21 and the semiconductor chip 25 are electrically connected to each other using a metal wire 26.

도 4b에 도시된 바와같이 상기 인너 리드(21)와 아웃 리드(22)로 이루어진 리드 프레임을 PCB의 랜드(Land)에 실장될 수 있도록 패턴이 형성된 테이프(Type)(27)에 열 압착방식으로 접합한다.As shown in FIG. 4B, a lead frame including the inner lead 21 and the out lead 22 is thermally compressed to a patterned tape 27 to be mounted on a land of the PCB. Bond.

이때 상기 인너 리드(21)가 형성되어 있는 리드 프레임의 접합부에는 주석/납(Sn/Pb) 플레이팅(28)을 하며, 패턴이 형성되어 있는 상기 테이프(27)의 접합부는 구리(Cu)플레이팅(29)한다.At this time, tin / lead (Sn / Pb) plating 28 is applied to the joint of the lead frame on which the inner lead 21 is formed, and the joint of the tape 27 on which the pattern is formed is copper (Cu) play. (29).

도 4c에 도시된 바와같이 상기 열 압착방식으로 접합된 테이프(27)상의 상기 반도체 칩(25)을 보호하기 위해 전면에 플라스틱 수지(30)로 몰딩한다.As shown in FIG. 4C, the front surface of the semiconductor chip 25 is molded with a plastic resin 30 to protect the semiconductor chip 25 on the tape 27 bonded by the thermocompression bonding method.

도 4d에 도시된 바와같이 상기 플라스틱 수지(30)로 몰딩 후에 상기 테이프(27)를 제거하므로써 LGA 패키지(Land Grid Array Package)를 제조한다.As shown in FIG. 4D, a LGA package (Land Grid Array Package) is manufactured by removing the tape 27 after molding with the plastic resin 30.

만약, 상기 LGA 패키지를 PCB에 실장시 실장높이를 낮출수 있으며 SMT(Surface Mounting Technology)를 이용할 경우 스크린 프린팅(Screen Printing)을 이용한 제품을 제작할 수 있다.If the LGA package is mounted on a PCB, the mounting height can be lowered, and if SMT (Surface Mounting Technology) is used, a product using screen printing can be manufactured.

이상에서 설명한 바와같이 본 발명에 의한 반도체 패키지의 제조방법에 있어서 다음과 같은 효과가 있다.As described above, the method of manufacturing a semiconductor package according to the present invention has the following effects.

첫째, 플라스틱 수지로 전체 패키지를 구성하고, 최소면적의 금속 리드 프레임을 사용함으로써 반도체 패키지의 휨을 방지한다.First, the entire package is made of plastic resin, and the bending of the semiconductor package is prevented by using the metal lead frame of the smallest area.

둘째, 접합부에 구리(Cu)플레이팅을 사용하기 때문에 계면 박리현상을 방지하므로써 신뢰성이 좋은 반도체 패키지를 얻는다.Second, since copper (Cu) plating is used at the junction, a semiconductor package having high reliability can be obtained by preventing interfacial delamination.

셋째, PCB에 스크린 프린팅을하여 패키지를 실장할 수 있어 마운팅(Mounting)의 생산성이 향상된다.Third, the product can be mounted by screen printing on the PCB, thus improving the productivity of mounting.

Claims (4)

인너 리드가 형성된 리드 프레임의 패들에 반도체 칩을 접착시키는 공정과,Bonding a semiconductor chip to a paddle of a lead frame in which an inner lead is formed, 상기 반도체 칩과 인너 리드를 전기적으로 연결하는 공정과,Electrically connecting the semiconductor chip and an inner lead; 상기 리드 프레임이 랜드에 실장될 수 있도록 패턴이 형성된 테이프를 접합하는 공정과,Bonding a tape having a pattern formed thereon so that the lead frame is mounted on land; 상기 반도체 칩을 보호하기 위해 몰딩하는 공정과,Molding to protect the semiconductor chip; 상기 테이프를 제거하는 공정을 포함하여 형성함을 특징으로 하는 반도체 패키지의 제조방법.Forming a semiconductor package comprising the step of removing the tape. 제 1 항에 있어서,The method of claim 1, 상기 테이프는 상기 리드 프레임의 접합부에 납이나 주석으로 플레이팅 되며, 테이프의 접합부는 금 플레이팅되는 것을 특징으로 하는 반도 체 패키지의 제조방법.And the tape is plated with lead or tin at the joint of the lead frame, and the joint of the tape is plated with gold. 제 1 항에 있어서,The method of claim 1, 상기 리드 프레임을 테이프에 접합은 열 압착방식으로 접합함을 특징으로 하는 반도체 패키지의 제조방법.The method of manufacturing a semiconductor package, characterized in that for bonding the lead frame to the tape is bonded by a thermal compression method. 제 1 항에 있어서,The method of claim 1, 상기 반도체 칩을 보호하기 위해 플라스틱 수지로 몰딩하는 것을 특징으로 하는 반도체 패키지의 제조방법.Method of manufacturing a semiconductor package, characterized in that for molding the plastic resin to protect the semiconductor chip.
KR1019970002247A 1997-01-27 1997-01-27 Method for manufacturing of semiconductor package KR100209763B1 (en)

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