KR100209637B1 - Platinum etching method - Google Patents
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- KR100209637B1 KR100209637B1 KR1019960034035A KR19960034035A KR100209637B1 KR 100209637 B1 KR100209637 B1 KR 100209637B1 KR 1019960034035 A KR1019960034035 A KR 1019960034035A KR 19960034035 A KR19960034035 A KR 19960034035A KR 100209637 B1 KR100209637 B1 KR 100209637B1
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- 238000005530 etching Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 39
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 title abstract description 80
- 229910052697 platinum Inorganic materials 0.000 title abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 17
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000001552 radio frequency sputter deposition Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 14
- 239000006227 byproduct Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 16
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000009257 reactivity Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000011232 storage material Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- UPIXZLGONUBZLK-UHFFFAOYSA-N platinum Chemical compound [Pt].[Pt] UPIXZLGONUBZLK-UHFFFAOYSA-N 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 백금(platinum) 식각방법에 관한 것으로 기판상에 베리어층을 형성하고, 베리어층상에 Pt층을 형성한 후 Pt층상에 산화막을 형성하고 패터닝하여 식각할 Pt층의 일정 영역을 노출시킨 다음 패터닝된 산화막을 마스크로 노출된 Pt층을 BCl3개스 시스템을 이용하여 식각하고 산화막을 제거함으로써 Pt의 식각율과 Pt에 대한 마스크의 선택비가 향상되고 식각후 부산물이 생성되지 않으므로 후 공정을 용이하게 하고 또한 Pt의 미세 형상 제작을 가능하게 함으로써 고집적 회로에 적합하도록 한 것이다.The present invention relates to a platinum etching method, forming a barrier layer on a substrate, forming a Pt layer on the barrier layer, forming an oxide film on the Pt layer, and then patterning and exposing a predetermined region of the Pt layer to be etched. By etching the Pt layer exposed with the patterned oxide film as a mask using a BCl 3 gas system and removing the oxide film, the etching rate of Pt and the selectivity of the mask to Pt are improved, and by-products are not generated after etching, thereby facilitating subsequent processes In addition, it is possible to manufacture a fine shape of Pt to be suitable for a highly integrated circuit.
Description
본 발명은 식각방법에 관한 것으로, 특히 백금(platinum) 식각방법에 관한 것이다.The present invention relates to an etching method, in particular to a platinum (platinum) etching method.
일반적으로 반도체 소자의 미세구조 제작기술의 발전 동향 중 주목할 만한 분야는 고유전체 축전지를 채용한 마이크로 컴퓨터 분야이다.In general, one of the notable areas of development of the microstructure fabrication technology of semiconductor devices is the microcomputer field employing high-k dielectric batteries.
고유전체 축전지는 불필요한 복사 현상이나 전자기적 간섭현상을 줄이는데 효과가 있으며, 메모리의 집적도를 향상시키는데 있어서는 단위기억소자에 필요한 축전지의 크기를 효과적으로 줄일 수 있는 장점이 있다.The high-k dielectric has an effect of reducing unnecessary radiation and electromagnetic interference, and has an advantage of effectively reducing the size of the battery required for the unit memory device in order to improve the memory density.
고유전체는 주로 금속산화물로 이루어지며 매우 반응성이 좋은 산소를 함유하게 된다.The high dielectric material mainly consists of metal oxides and contains very reactive oxygen.
이러한 고유전체로 축전지를 만드는데 있어서는 전극으로 사용될 물질이 아주 반응성이 좋지 않은 물질이 사용되어야만 한다.In making a battery with such a high dielectric material, a material having a very poor reactivity must be used.
그러한 전극으로 주로 사용되는 물질은 platinum, palladium 등이다.The materials mainly used for such electrodes are platinum, palladium and the like.
제1도는 반도체 소자에 있어서 유전체 축전지를 보여주는 일반적인 구조단면도이다.1 is a general structural cross-sectional view showing a dielectric storage battery in a semiconductor device.
제1도에 도시된 바와 같이 하부층(1)과, 하부층(1)상에 형성되는 하부전극(2)과, 하부전극(2)의 일정 영역에 형성되는 커패시터막(3)과, 커패시터막(3)상에 형성되는 상부전극(4)과, 상부전극(4)을 포함한 하부층(1) 전면에 형성되는 절연막(5)과, 상부전극(4)과 하부전극(2)에 각각 콘택되어 절연막(5)상에 형성되는 제1, 제2전극(6,7)으로 이루어진다.As shown in FIG. 1, the lower layer 1, the lower electrode 2 formed on the lower layer 1, the capacitor film 3 formed in a predetermined region of the lower electrode 2, and the capacitor film ( 3, an insulating film 5 formed on the entire surface of the lower electrode 1 including the upper electrode 4 formed on the upper electrode 4 and the upper electrode 4 and the lower electrode 2, respectively, It consists of the 1st, 2nd electrodes 6 and 7 formed on (5).
이때, 하부전극(2)은 전극 양단의 접촉을 위해서 상부에 올라가는 층들 보다 큰 모양을 가지게 된다.At this time, the lower electrode 2 has a shape larger than the layers that rise to the top for contact between both ends of the electrode.
이러한 구조를 갖는 축전지를 만들기 위해서는 두 단계의 식각공정이 필요하게 된다.In order to make a battery having such a structure, a two-step etching process is required.
첫 번째는 상부전극과 축전물질을 식각하는 공정이며, 두 번째는 하부전극을 식각하는 공정이다.The first is the process of etching the upper electrode and the storage material, the second is the process of etching the lower electrode.
여기서 축전물질 식각시 하부전극과 축전물질간에는 식각율에 현격한 차이가 있어야 하부전극의 과도한 시각을 방지할 수 있다.Here, when the storage material is etched, there must be a significant difference in the etching rate between the lower electrode and the storage material to prevent excessive viewing of the lower electrode.
제1도와 같은 고유전체 축전지를 개발하는데 있어서 전극물질로 폭넓게 사용되고 있는 백금(platinum)을 효과적으로 식각해 내는 것은 매우 필수적이고도 중요한 과정이다.Efficient etching of platinum, which is widely used as an electrode material, is a very essential and important process in the development of high-k dielectric batteries, such as FIG.
백금(이하 Pt라 함)을 식각하기 위하여 사용되는 종래의 기술은 HF의 액상 화합물을 이용한 습식 식각 방식과 Ar 개스를 이용한 이온 밀링(ion milling)방법 그리고 CF4, SF6, Cl2, CH4등의 개스 시스템(Gas System)을 이용하여 RIE(Reactive Ion Etcher), MERIE(Magnetically Enhanced RIE), ECR(Electron Cyclotron Resonance) 등의 장비를 통한 건식 식각 방식 등이 있다.Conventional techniques used to etch platinum (hereinafter referred to as Pt) include wet etching using liquid compounds of HF, ion milling using Ar gas, and CF 4 , SF 6 , Cl 2 , CH 4. Dry etching using a gas system (Gas System), such as Reactive Ion Etcher (RIE), Magnetically Enhanced RIE (MERIE), Electron Cyclotron Resonance (ECR).
종래에 따른 백금(Pt) 식각방법에 있어서는 다음과 같은 문제점이 있었다.The conventional platinum (Pt) etching method has the following problems.
습식 식각 방식은 Pt와 HF 액상 화합물간의 화학 반응을 통하여 식각되기 때문에 Pt의 식각 속도는 빠른편이지만 등방성 식각으로 인해 고집적 회로에 적용할 수 있을 만큼 미세한 형상을 얻을 수 없다는 문제점이 있다.Since the wet etching method is etched through a chemical reaction between Pt and HF liquid compounds, the etching speed of Pt is fast, but there is a problem in that a fine shape can be obtained to be applied to a highly integrated circuit due to isotropic etching.
그리고 Ar 밀링과 건식 식각 방식의 경우 기존에 사용된 개스 시스템과 식각 공정 방식으로는 식각율이 매우 낮고(100nm/min 이하) 마스크(mask)로 사용되는 재료의 식각율이 Pt에 비하여 한층 더 빠르므로 마스크가 마스크로서의 역할을 제대로 수행하지 못하였다.In the case of Ar milling and dry etching, the etching rate is very low (100 nm / min or less) and the etching rate of the material used as a mask is much faster than that of Pt. Therefore, the mask did not function properly as a mask.
예시된 개스 시스템으로 Pt를 식각할 때의 식각 메카니즘은 주로 Ar 밀링 방식의 스퍼터링(sputtering)에 의하여 식각이 이루어진다.The etching mechanism when etching Pt with the illustrated gas system is mainly etched by sputtering of Ar milling method.
이러한 스퍼터링 방식에 의한 Pt의 식각은 Pt를 물리적으로 제거해 주는 방식이기 때문에 식각 공정 후에도 Pt가 잔류할 뿐 아니라 Pt와의 화학반응이 일어난다 하더라도 반응 후 생성되는 부산물 자체도 쉽게 개스 상태로 휘발할 수 있는 물질이 아니기 때문에 식각 공정이 끝난 후 Pt의 잔류물이나 부산물들이 웨이퍼위에 남게 된다.The etching of Pt by the sputtering method physically removes Pt, so that not only Pt remains after the etching process but also the by-products generated after the reaction can easily volatilize to a gas state even if a chemical reaction with Pt occurs. Because of this, after the etching process, residues or by-products of Pt remain on the wafer.
따라서, Pt의 식각 공정 후 형성된 잔류물과 부산물을 제거하는 까다로운 후공정이 필요하게 되는 문제점이 있다.Therefore, there is a problem that a difficult post process for removing residues and by-products formed after the etching process of Pt is required.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로써, Pt의 식각율을 향상시키는 식각 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide an etching method for improving the etching rate of Pt.
본 발명의 다른 목적은 Pt에 대한 마스크의 선택비를 향상시키는 식각방법을 제공하는데 있다.Another object of the present invention is to provide an etching method for improving the selectivity of the mask to Pt.
본 발명의 또 다른 목적은 Pt의 미세 형상을 용이하게 하고 부산물의 증착이 일어나지 않도록 하는 식각방법을 제공하는데 있다.Still another object of the present invention is to provide an etching method for facilitating the fine shape of Pt and preventing deposition of by-products.
제1도는 반도체 소자에 있어서 유전체 축전지를 보여주는 일반적인 구조단면도.1 is a general structural cross-sectional view showing a dielectric storage battery in a semiconductor device.
제2a도 내지 제2d도는 본 발명에 따른 Pt의 식각공정을 보여주는 공정단면도.2a to 2d is a cross-sectional view showing the etching process of Pt according to the present invention.
제3a도 내지 제3c도는 BCl3개스 시스템을 이용한 Pt 식각시 조건들에 대한 Pt 식각율과 SiO2마스크에 대한 Pt의 선택비를 보여주는 그래프.3a to 3c are graphs showing the Pt etching rate for Pt etching conditions and the selectivity ratio of Pt to SiO 2 mask using the BCl 3 gas system.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 기판 11 : Ti층10 substrate 11 Ti layer
12 : Pt층 13 : SiO2층12: Pt layer 13: SiO 2 layer
14 : 포토레지스트14 photoresist
이와 같은 목적을 달성하기 위한 본 발명에 따른 백금(Pt) 식각방법은 기판상에 베리어층을 형성하고 베리어층상에 Pt층을 형성한 후 Pt층상에 산화막을 형성하고 패터닝하여 식각할 Pt층의 일정 영역을 노출시킨 다음 패터닝된 산화막을 마스크로 노출된 Pt층을 BCl3개스를 이용하여 식각하고 산화막을 제거하여 이루어짐을 그 특징으로 한다.Platinum (Pt) etching method according to the present invention for achieving the above object is to form a barrier layer on the substrate, a Pt layer on the barrier layer, and then forming an oxide film on the Pt layer and patterning the Pt layer to be etched After exposing the region, the Pt layer exposed using the patterned oxide film as a mask is etched using BCl 3 gas and the oxide film is removed.
본 발명의 다른 특징은 베리어층은 Ti로 형성하고 산화막은 SiO2로 형성하는데 있다.Another feature of the present invention is that the barrier layer is formed of Ti and the oxide film is formed of SiO 2 .
본 발명의 또 다른 특징은 산화막은 CF4개스로 제거하는데 있다.Another feature of the invention is that the oxide film is removed with CF 4 gas.
본 발명의 또 다른 특징은 Pt층 식각시의 압력은 1∼20mTorr로 하고 ICP 파워는 600∼1000W로 하며 RIE 파워는 200∼300W로 하는데 있다.Another feature of the present invention is that the pressure during etching of the Pt layer is 1-20 mTorr, the ICP power is 600-1000 W, and the RIE power is 200-300 W.
상기와 같은 본 발명에 따른 백금(Pt) 식각방법을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Referring to the platinum (Pt) etching method according to the present invention as described above in more detail with reference to the accompanying drawings as follows.
제2a도 내지 제2d도는 본 발명에 따른 Pt의 식각 공정을 보여주는 공정단면도이다.2a to 2d are cross-sectional views showing the etching process of Pt according to the present invention.
제2a도에 도시된 바와 같이 실리콘 기판(10)상에 Pt 증착을 위한 베리어(barrier)층으로 Ti층(11)을 형성하고 Ti층(11)상에 RF스퍼터링(sputtering) 방법으로 Pt층(12)을 형성한다.As shown in FIG. 2A, the Ti layer 11 is formed as a barrier layer for Pt deposition on the silicon substrate 10 and the Pt layer is formed on the Ti layer 11 by RF sputtering. 12) form.
그리고 Pt층(12)상에 LPCVD(Low Pressure CVD) 방법으로 SiO2층(13)을 형성한다.The SiO 2 layer 13 is formed on the Pt layer 12 by a low pressure CVD (LPCVD) method.
제2b도에 도시된 바와 같이 SiO2층(13)상에 포토레지스트(14)를 도포하고 노광 및 현상공정으로 원하는 패턴을 형성한다.As shown in FIG. 2B, the photoresist 14 is applied onto the SiO 2 layer 13, and a desired pattern is formed by an exposure and development process.
이때, 포토레지스트(14) 도포후 소프트 베이킹(soft baking)의 조건은 온도 95℃, 시간 100초로 하고 현상후의 하드 베이킹(hard baking)은 온도 110℃, 시간 10분으로 한다.At this time, the conditions of soft baking after application of the photoresist 14 are at a temperature of 95 ° C. for a time of 100 seconds, and a hard baking after development is at a temperature of 110 ° C. for a time of 10 minutes.
그리고 포토레지스트(14)를 마스크로 하고 CF4개스를 에천트(etchant)로 SiO2층(13)을 제거하여 Pt층(12)을 노출시킨다.Then, the Pt layer 12 is exposed by removing the SiO 2 layer 13 with the photoresist 14 as a mask and CF 4 gas as an etchant.
CF4개스는 SiO2층(13)과 만나 COX나 SiFX의 기상 화합물을 형성하여 식각후 잔류물이 없이 깨끗하게 패턴을 만들 수 있다.The CF 4 gas can meet with the SiO 2 layer 13 to form a gaseous compound of CO X or SiF X to form a clean pattern without residue after etching.
제2c도에 도시된 바와 같이 남아 있는 포토레지스트(14)를 O2플라즈마(Plasma)로 제거한다.As shown in FIG. 2C, the remaining photoresist 14 is removed with an O 2 plasma.
그리고 패터닝된 SiO2층(13)을 마스크로 노출된 Pt층(12)을 BCl3개스 시스템을 이용하여 식각한다.The Pt layer 12 exposed by patterning the patterned SiO 2 layer 13 is etched using a BCl 3 gas system.
이때, BCl3개스 시스템을 이용한 Pt층(12) 식각시의 조건은 다음과 같다.At this time, the conditions during the etching of the Pt layer 12 using the BCl 3 gas system are as follows.
압력은 1∼20mTorr로 하고 ICP 파워(Inductively Coupled Plasma power)는 600∼1000W로 하며 RIE 파워(Reactive Ion Etcher power)는 200∼300W으로 한다.The pressure is 1-20 mTorr, the ICP power (Inductively Coupled Plasma power) is 600-1000W, and the RIE power (Reactive Ion Etcher power) is 200-300W.
또한, BCl3는 Pt 식각시 Pt와의 반응성이 뛰어나며 비교적 쉽게 기상의 화합물을 형성하기 때문에 Pt의 식각율을 향상시키며 상대적으로 SiO2마스크에 대해서는 반응성이 좋지 않아 식각율이 낮다.In addition, BCl 3 has a high reactivity with Pt during Pt etching and forms a gaseous compound relatively easily, thereby improving the etching rate of Pt and relatively low etching rate due to poor reactivity to SiO 2 masks.
제2d도에 도시된 바와 같이 남아있는 SiO2층(13)을 Pt에 대한 선택비가 좋은 CF4개스 플라즈마를 이용하여 제거한다.As shown in FIG. 2d, the remaining SiO 2 layer 13 is removed using a CF 4 gas plasma having a good selectivity to Pt.
이때, CF4개스 플라즈마에 노출된 Pt층(12)의 면 거칠기는 후 공정인 응용재료(BST, STO, BTO 등) 증착시 영향을 미치지 않는 양호한 상태를 유지하게 된다.At this time, the surface roughness of the Pt layer 12 exposed to the CF 4 gas plasma is maintained in a good state that does not affect the deposition of the application material (BST, STO, BTO, etc.) in the subsequent process.
그리고 Pt의 식각이 끝나면 식각 형상 자체를 사용하거나 응용재료를 증착하여 사용할 수 있다.After the etching of Pt, the etching shape itself or the application material may be deposited.
제3a도 내지 제3c도는 BCl3개스 시스템을 이용한 Pt 식각시 조건들에 대한 Pt 식각율과 SiO2마스크에 대한 Pt의 선택비를 보여주는 그래프이다.3a to 3c are graphs showing the Pt etch rate for the Pt etching conditions using the BCl 3 gas system and the selectivity ratio of Pt to the SiO 2 mask.
제3a도에 도시된 바와 같이 공정 압력은 낮은 압력(1∼20mTorr)에서 SiO2마스크에 대한 Pt의 선택비와 Pt식각율이 좋고 제3b도에 도시된 바와 같이 RIE 파워(Reactive Ion Etcher power)는 200∼300W으로 할 때 즉, 식각면에 수직한 방향에 대한 이온의 운동에너지가 높을 때 SiO2마스크에 대한 Pt의 선택비와 Pt 식각율이 좋으며 제3c도에 도시된 바와 같이 ICP 파워(Inductively Coupled Plasma power)는 600∼1000W에서 최적의 조건을 얻을 수 있다.As shown in FIG. 3a, the process pressure has a good Pt selectivity and Pt etch rate for the SiO 2 mask at low pressure (1-20 mTorr), and the reactive ion etchant power (RIE) as shown in FIG. 3b. The selectivity of Pt and the Pt etching rate for the SiO 2 mask are good at 200 to 300W, that is, when the kinetic energy of ions in the direction perpendicular to the etching plane is high, and the ICP power ( Inductively Coupled Plasma power) can achieve optimal conditions at 600 ~ 1000W.
이때, Pt의 식각율은 130nm/min 이상이고 SiO2마스크에 대한 Pt의 선택비는 1.5:1(Pt:SiO2)을 얻을 수 있다.In this case, the etching rate of Pt is 130 nm / min or more, and the selectivity of Pt to SiO 2 mask is 1.5: 1 (Pt: SiO 2 ).
이와 같은 본 발명은 BCl3개스 시스템을 Inductively Coupled Plasma로 만들어서 Pt를 좀 더 빨리 식각하고 LPCVD법으로 증착한 SiO2마스크의 식각 속도는 Pt에 비하여 상대적으로 느린 식각 속도를 얻기 위한 건식 식각방법이다.The present invention is a dry etching method for obtaining a relatively slow etching rate of the etching rate of the SiO 2 mask deposited by the LPCVD method by etching the Pt faster by making the BCl 3 gas system to Inductively Coupled Plasma.
본 발명에 따른 백금(Pt) 식각방법은 다음과 같은 효과가 있다.Platinum (Pt) etching method according to the present invention has the following effects.
첫째, Pt의 식각율과 Pt에 대한 마스크의 선택비가 향상되므로 후 공정이 용이하다.First, since the etching rate of Pt and the selectivity of the mask with respect to Pt are improved, post-processing is easy.
둘째, Pt의 미세 형상을 용이하게 하고 부산물의 증착이 일어나지 않도록 함으로써 고집적 회로에 적합하다.Second, it is suitable for high-integrated circuits by facilitating the fine shape of Pt and preventing the deposition of by-products.
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