KR100209417B1 - Controller for video signal coding system - Google Patents

Abstract

The present invention is a controller for determining an inter / intra mode, a field / frame mode and a quantization coefficient used in a video signal encoding system, wherein the video signal includes a plurality of GOPs. Each GOP is divided into three types of pictures, each picture is divided into a plurality of macroblocks, and the encoding system encodes a video signal with a single macroblock, but the controller: the type of the picture currently being encoded and the start of the picture. A state machine for generating a control sequence including a plurality of control signals in response to a signal representing a signal; An arithmetic unit that generates a group of control values for each macroblock of a picture by calculating a predetermined series of equations based on a serial number of a currently encoded macroblock and a predetermined initial constant value in response to the control sequence. The group of control values includes an arithmetic unit meaning inter / intra mode, field, / frame mode and quantization coefficient; A memory and an input / output unit for storing the initial constant value, supplying the initial constant value to the arithmetic unit, stores a group of control values determined in the arithmetic unit, and provides a control value used in the video encoding process.

Description

Video signal coding system controller

1 is a block diagram of a video signal encoding system employing a controller according to the present invention.

2 is a block diagram of a controller of the present invention.

3 is a block diagram of the memory and input / output unit of FIG.

4 is a block diagram of the arithmetic unit of FIG.

5 is an illustration of a method of determining an inter / intra mode by VAR and VAROR.

The present invention relates to a controller used in a video signal encoding system, and in particular, by controlling the amount of data from the encoding system by controlling the quantization coefficient to prevent the buffer from overflowing or underflowing, A controller for determining the / intra mode and the field / frame DCT.

With the development of communication and circuit integration technology, the transmission of discrete video signals has become a reality. When a video signal consisting of a series of video frames is represented in discrete form, a considerable amount of data must be transmitted, especially in high definition televisions. However, since the usable frequency band of the conventional transmission channel is limited, to transmit a considerable amount of discrete data, it is necessary to use a compression technique that can reduce the amount of transmission data without deteriorating the picture quality.

In this respect, standards have been created for the compression of discrete video signals over the last few decades, and some are currently under development. One such standard is the ISO / IEC MPEG standard, developed by the Moving Picture Export Group, a joint technical conference of the International Standard Organization and the International Electrotechnical Commission. . Although this standard determines compressed bitstreams and decoding methods, various algorithms are available for encoding.

Since the present invention aims to be used in such an encoding system, some contents of MPEG video compression algorithms will be described to help the understanding of the present invention. However, any video encoding algorithm that shares the features of the MPEG algorithm according to the present invention may be applied elsewhere.

An MPEG video sequence is divided into a series of pictures or frames called a group of pictures (GOP). Each GOP includes a number of pictures and each picture is divided into a number of slices. Each slice contains a number of macroblocks (MBs) and each macroblock has four 8 × 8 brightness blocks and two 8 × 8 chrominance blocks.

And three kinds of pictures may appear in one GOP, the first of which is an intra mode picture or an I-picture, which is compressed separately from other pictures. The other two types are predictive motion compensated pictures (P-pictures) and bidirectional motion compensated pictures (B-pictures).

On the other hand, motion compensation is a method of removing redundancy between successive pictures. In MPEG, each macroblock is compared with a 16x16 area at a similar position of the reference frame. A frame compressed using one frame in the past is a P-picture. This prediction is called forward-in-time prediction. In B-picture, forward-in-time prediction is performed as well as backward-in-time prediction. In an I-picture, all macroblocks are encoded in intra mode, without considering motion compensation. In the P-picture and the B-picture, each macroblock may be encoded in an intra mode or an inter mode using motion compensation. To determine one encoding mode for a macroblock, VAR and VAROR are calculated as follows.

Where O (i, j) and S (i, j) represent the pixel values of the original block to be encoded and the pixel values reconstructed using the conventional motion compensation method, respectively; ave [O (i, j)] is an average value of O (i, j). VAR and VAROR are related to the amount of data generated when encoding the corresponding macroblock in inter mode and intra mode, respectively. As shown in FIG. 5, the inter / intra mode is determined according to the values of VAR and VAROR.

In addition, in MPEG and some other compression standards, discrete cosine transform (DCT) has been adopted. In MPEG, which uses interlaced scanning to define a frame, two types of DCTs, namely, field-specific DCT and frame-specific DCT, may be selectively used. The horizontal lines forming the frame are divided into radix fields and ordinal fields so that the ordinal lines form the ordinal fields (2, 4, 6 ...) and the radix lines form the radix fields (1, 3, 5 ...). Discrete interlaced video signals may be compressed in field mode or frame mode. In field mode, each frame is divided into a radix field and an ordinal field and processed separately. In frame mode, two fields are treated as one frame by interleaving corresponding lines of the odd and ordinal fields. In video compression, neither one is fully satisfactory. Since each frame has twice as many lines as the field, the correlation between samples is large, which means that the compressibility is improved. However, in the case of precise motion, frame mode processing may be affected by the high frequency generated by interleaving the odd and ordinal fields. At this time, the field / frame DCT is determined in units of macroblocks. One of the rules for determining the DCT mode is described by the following equation.

(See Test Model 4 of ISO-IEC / JTC1 / SC29 / W G11 / MPEG93 / 225)

At this time, a macro block having a larger VAR1 than a VAR2 uses a frame unit DCT and vice versa.

Then, the DCT coefficients obtained using the field unit or frame unit DCT are subjected to quantization. Quantization is performed by dividing a block of DCT coefficients by W _mn × QP, where W _mn is a weighting factor matrix and QP is a quantization parameter. The weighting factor causes quantization to be sparse on visually less important DCT coefficients. The quantization parameter QP is a means of tradeoff between picture quality and bit rate of an image. QP can be accelerated according to the macroblock even within a picture. This property, known as adaptive quantization, allows different regions of each frame to be quantized with different quantization step sizes.

The quantized coefficients after quantization are encoded using variable length coding (VLC) such as Huffman coding. The amount of data generated as a result of VLC depends on the video signal characteristics. Therefore, there is a need for a rate control method for adjusting the amount of encoded data according to a given amount of transmission. As mentioned above, such a rate controller serves to adjust the amount of coded data, for example, by varying the quantization parameter QP according to the fullness of the buffer and the activity of the input image.

Next, a method of controlling the bit rate by adjusting the quantization parameter in units of macroblocks will be described. The whole process consists of target bit allocation; Rate control; There are three stages of adaptive quantization. In the first step, the number of bits that can be used to encode the next frame is estimated. In the second step, the reference value of the quantization parameter for each macroblock is determined using the virtual buffer. Finally, the reference value of the quantization parameter is adjusted according to the spatial activity of the macroblock to calculate the quantization parameter. I will explain each step in detail.

[Step 1]

After encoding some kind of (I, P or B picture) picture, each total complexity index (X _i , X _p , X _b ) is updated as follows.

Where S _I , S _P , and S _b represent the number of bits generated as a coding term for the picture, and Q _I , Q _P and Q _b represent the average quantization obtained by averaging the actual quantization parameters for all the macroblocks of the picture. Parameter.

At the beginning of the encoding process, the initial constant value of the complexity index is determined by the following equation.

At this time, the value of BIT_RATE is a predetermined constant in bits / sec unit. After X _i , X _p and X _b are determined, an estimated value of the number of target bits, i.e., the number of bits generated for encoding the next picture, is predetermined.

Next, the target number of bits (T _i , T _p , T _b ) for the I, P or B-picture is determined by the following equation.

In this case, K _p and K _b are preset constants. R is the number of bits remaining among the bits allocated to the current GOP, and is updated as shown in the following equation after encoding one picture.

In this case, S _i (or S _P , or S _b ) is the number of bits generated in the just-encoded frame, and the subscripts i, p, and b represent the type of frame. The R value before the first picture of the GOP is encoded is as follows.

In this case, N is the number of pictures in the GOP and the value of PICTURE_RATE is a predetermined constant. At the beginning of the encoding process, the initial constant of R is zero. In Equations 4a to 4c, NP and Nb are the number of P-pictures and B-pictures remaining in the current GOP. Therefore, at the beginning of the GOP, N _p and N _b are the total number of P-pictures and B-pictures of the current GOP, respectively.

[Step 2: Rate Control]

In this step, the reference quantization parameter is calculated according to the concept of the virtual buffer.

First, before encoding the macroblock j, the fullness of the virtual buffer is determined as follows according to the picture type.

Where do ⁱ , do ^p , do ^b represent the fullness of the virtual buffer at the start of the picture for each picture type; B _j is the number of bits generated for encoding the macroblock j up to and including the macroblock _j in the current frame; MB_cnt is the number of macroblocks included in the picture; d _j ⁱ , d _j ^p , d _j ^b are the fullness of the virtual buffer in macroblock j for each picture type.

The final fullness of the virtual buffer at the end in the picture also, that when j = MB_cat d _j ^i, d _j ^p, d _j ^b) is used to do ^i, do ^p, do ^b for encoding the type of the following picture, such as do.

Next, the reference quantization parameter Qj for macroblock j is determined as follows.

At this time, And d _j is the fullness value of the virtual buffer.

In addition, at the beginning of the encoding, the fullness of the virtual buffer is as follows.

[Step 3: Adaptive Quantization]

In this step, the Mquant (modified quantization parameter) actually used to quantize each macroblock is obtained from the reference quantization parameter using the spatial activity of the image.

The spatial activity index for the macroblock j is obtained from the four frame-aligned blocks and the four field-aligned blocks of the macroblock j using the intra pixel value as follows.

At this time,

ego,

P _k is the pixel value of the original block. In the case of a frame-aligned block, a block consists of eight consecutive lines. In the case of a field-aligned block, the lines of the block radix field and the ordinal field form separate blocks.

Where P _k is

And avg_act is an average value of act _j for the previous picture. In the first picture, the value of avg_act is 400.

After that, Mquant is determined by the following formula:

In the above equation, the final value of Mquant _j is adjusted in the range of 1 to 31 and used in the quantization process. Thus, by doing the above, when the number of bits generated in the encoding process exceeds the predetermined number (in case the data inputted into the buffer increases), the quantization step size increases and vice versa, thus reducing the buffer fullness. Adjust to whatever position.

The three tasks described above, namely inter / intra mode, field / frame DCT mode and quantization parameter determination, are a series of arithmetic processes. While these tasks can be implemented using a common processor, developing a dedicated circuit has advantages in speed and cost.

Accordingly, an object of the present invention is to provide a structure and a method of operation of a controller for calculating quantization parameters and determining inter / intra mode and field / frame DCT mode.

In order to achieve the above object, the present invention provides a controller for determining an inter / intra mode, a field / frame mode and a quantization coefficient, which is used in a video signal encoding system. A plurality of GOPs, each GOP is divided into three kinds of pictures, each picture is divided into a plurality of macroblocks, and the encoding system encodes a video signal in units of macroblocks, the controller being: currently encoded State machine for generating a control sequence including a plurality of control signals in response to a type of a picture and a signal indicating the start of the picture: a serial number of a macroblock currently encoded in response to a control sequence, and By calculating a set of preset equations based on the set initial constant value, a group of control values are generated for each macroblock of the picture. An arithmetic unit, wherein the group of control values includes an arithmetic unit meaning inter / intra mode, field, / frame mode, and quantization coefficient; And a memory and an input / output unit for storing the initial constant value, supplying the initial constant value to the arithmetic unit, storing a group of control values determined in the arithmetic unit, and providing a control value used in the video encoding process. To provide.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a block diagram of a conventional video encoding system using the controller 100 of the present invention for determining inter / intra mode, field / frame mode and quantization parameters is shown.

First, the current frame to be encoded of the video signal is input to the DPCM block 200 and the motion compensation (MC) block 500. Predicted frame data from the MC block 500 is also input to the DPCM block 200. In practice, video data is provided and processed in units of macroblocks throughout the entire encoding process. In the DPCM block 200, the difference between the frame data predicted according to the encoding mode, that is, the inter / intra mode of the macroblock and the current frame data, or the current frame data itself is provided to the DCT block 250. The difference or current frame data is transformed in the DCT block 250 using DCT and the like, and the transform coefficient is input to the quantization (Q) block 300 and quantized. The quantized coefficient then moves along two paths. That is, one is entropy encoder 350, in which quantized transform coefficients are encoded using, for example, run length coding and variable length coding. The other is connected to an inverse quantization (IQ) block 400 to convert the quantized transform coefficients into recovered frame data. The reconstructed frame data is input to the MC block 500 to obtain predicted frame data using known motion prediction and compensation techniques.

Then, the encoded data from the entropy encoder 350 is input to the buffer 600 and transmitted to the corresponding decoding system.

The controller 100 of the present invention determines the inter / intra mode, the field / frame DCT mode, the quantization parameter in units of macroblocks, and the former two (mode determination results) are assigned to the DPCM block 200 by the latter (quantization parameter). Serves to provide 300. In response to the inter / intra mode signal, the DPCM block 200 provides the DCT block 250 with the difference between the predicted frame data and the current frame data (inter mode) or the current frame data (intra mode). The difference or pixel value is provided in 8x8 block units and performs 8x8 DCT. The format of the block provided from the DPCM block 200 to the DCT block 250 is determined according to the field / frame DCT mode signal. In the frame DCT mode, the DPCM block 200 provides a frame aligned block, and in the field DCT mode, the field aligned block is provided so that the DCT block 250 performs field or frame unit DCT according to the mode. . The quantization parameter provided to the Q block 300 is used to adjust the degree of quantization and thus to adjust the fullness of the buffer 600.

2, a detailed block diagram of the controller 100 shown in FIG. 1 is shown.

In the controller 100 of the present invention, all arithmetic calculations involving three kinds of determinations are performed by the arithmetic unit 130 with the help of the state machine 120 and the memory and input / output unit 140.

Next, input signals for performing these operations will be described. The input signals are PIC_SYNC, MBS, CLK, RESET, PIC_TYPE, BUF_FULL, differential data from the DPCM block of FIG. 1, or current frame data. PIC_SYNC and MBS input to the control unit 110 among the input signals indicate the start of each frame and macroblock, respectively. RESET and CLK are system control signals. The PIC_TYPE input to the state machine 120 refers to a frame (I, P, B) currently processed among three picture types. PIC_SYNC, MBS, and PIC_TYPE can be derived from the input video signal sequence. BUF_FULL indicating the state of the buffer is input to the arithmetic unit 130.

Various initial constant values are needed to make three decisions. Such values are preset according to the system design and entered into the controller 100 of the present invention. More specifically, the controller 100 is input to the memory and the input / output unit 140 via L90 before performing the calculation. The initial constants in the above equations are X _i , X _p , X _b , R, N _b , N _p and K _p , K _b at the beginning of the encoding process.

In response to the input signal, the control unit 110 generates a control signal and provides it to the state machine 120. First, the control unit 110 provides a PRCS_PIC_MB indicating whether a picture unit operation or a macroblock unit operation is performed in the controller. In this case, the picture unit operation and the macro unit operation are each macro in each of the above equations. What is done per block. Picture unit operations are equations 3A to 3C, 4A to 4C, 5, and the like, and macroblock unit operations are equations 1A, 1B, and 2A. 2B, 7A to 7C, 8 to 13, and so on. Next, the control unit 110 generates MB_NUM representing the macroblock currently being processed and provides it to the arithmetic unit 130.

In response to the input signals, i.e., PIC_SYNC and PRCS_PIC_MB, the state machine 120 generates a series of control sequences and provides them to the arithmetic unit 130 and the memory and input / output unit 140 so that the arithmetic unit 130 provides one of the above equations. Do it. The state machine 120 is programmed to generate a control sequence that is preset according to what equation the arithmetic unit 130 performs. The memory and input / output unit 140 receives and stores an initial constant value from the host processor (not shown) on the L3O phase and receives and stores the calculation result from the arithmetic unit 130 on the L50 phase. In response to the control sequence on L80 from the state machine 120, the memory and input / output unit 140 is controlled to provide the initial constant value and temporary values included in the calculation result on the L60. In this case, the temporary values are values that are generated as a result of the calculation of the equation and are updated for each macroblock (or picture) using a value used for calculation of another equation or a value for a previous macroblock (or picture). In the above equation, values of T _i , T _p , T _b , R, D ⁱ _j , D ^p _j , D ^b _j , and the like are examples of temporary values. The memory and input / output unit are controlled to provide the final result of the calculation, namely the inter / intra, field / frame DCT mode, quantization parameters, to DPCM block 200 and Q block 300 of FIG. Detailed operations of the arithmetic unit 130 and the memory and input / output unit 140 will be described with reference to FIGS. 3 and 4.

Referring to FIG. 3, there is shown a block diagram of the memory and input / output unit 140 of FIG.

H0ST_DATA indicates initial constant values used to perform the expression in the arithmetic unit 130. BIT_RATE, PICTURE_RATE, X _i , X _p , X _b , R, N _p , N _b , D ⁱ _o , D ^p _o , D ^b _o , etc. at the beginning of the K _p , K _b encoding process of equations 4A to 4C This is an example of the initial constants provided by HOST_DATA. These are provided by the host processor that stores and provides various initial constants that are preset according to the system design. At the beginning of encoding an image sequence, all necessary constants are stored in RAM 160 via MUX 166 on L90. If arithmetic unit 130 performs these equations, the values are needed from RAM 160 to L60. To the arithmetic unit 130.

The calculation result obtained in the arithmetic unit 130 is also inputted through the MUX 166 on the L50 and stored in the RAM 160. Examples of such calculations are R, N _p , N _b , T _i , T _p , T _b . R is the remaining amount of bits allocated to the current GOP (Equation 5), stored in RAM 160 and updated in arithmetic unit 130 after one frame is encoded. N _p and N _b are the numbers of each of the P and B pictures remaining in the current GOP, and are used to calculate the target bits T _i , T _p , and T _b according to equations 4a to 4c.

ST_WR_ADRS and HOST_WR_ADRS are data input from arithmetic unit 130 and address signals used to store HOST_DATA in RAM 160, respectively. ST_WR_EN and HOST_WR_EN are signals that become active when data is stored in the RAM 160.

While the initial constant is input to the RAM 160, the MUXs 162, 164, and 166 select HOST_WR_ADRS, HOST_WR_EN, and HOST_DATA, respectively, where HOST_WR_ADRS represents the address of the RAM 160 where the initial value is to be stored, and HOST_WR_EN is active. Similarly, while the calculation result from the arithmetic unit 130 is input to the RAM 160, the MUXs 162, 164, and 166 select data on ST_WR_ADRS, ST_WR_EN, and L50, respectively, where ST_WR_ADRS stores the RAM 160 to store the calculation result. Indicates an address, and ST_WR_EN becomes active.

RD_ADRS is an address signal used to read data stored in RAM 160 and provide it to arithmetic operation 130 or DPCM and Q blocks of FIG. In detail, the initial constant value or the temporary value determined by the arithmetic unit 130 is read from the RAM 160 and input to the arithmetic unit 130 on the L60. On the other hand, the final result of the three kinds of determination, namely inter / intra, field / frame DCT mode and quantization parameter determination result Mquant is provided to DPCM and Q blocks of FIG.

Referring to FIG. 4, a block diagram of the arithmetic unit of FIG. 2 is shown.

MB_NUM and BUF_FULL are input to the MUX 132a from the control unit 110 and the buffer 600, respectively. Difference data and current frame data from the DPCM block 200 are also input to the MUX 132a. As described above, the initial constant value and the temporary value are provided on the L60 from the memory and input / output unit 140 (details RAM 160).

FR_EXT_SEL, REG_EN_X, REG_EN_Y, CIN, OPERAT10N_SEL, FEED_BACK_SEL, DIV_START, QUOT_EN, TO_RAM_SEL, WINDOW_PNT, FR_RAM_PNT and the like are control signals included in the control sequence of the state machine of FIG. The components of the arithmetic unit shown in FIG. 4 are controlled to perform arithmetic operations in accordance with this control sequence. The function of the control signal will be described.

(1) FR_RAM_PNT (or WIN_PNT)

This is valid when data is input to the barrel shifter 131 or 136. The value of FR_RAM_PNT (or WIN_PNT) indicates how many times the input data is shifted in the barrel shifter 131 or 136. For example, when FR_RAM__PNT is 2, the output of the barrel shifter 131 is four times the input.

(2) FR_EXT_SEL (or FB_SEL)

Which of the inputs to the MUX 1323 or 132b is selected to be provided to the register (X) 133a or the register (Y) 133b.

(3) REG_EN_X (or REG_EN_Y)

This is a valid signal when data is stored in register (X) 133a or register (Y) 133b.

(4) CIN, DIV_START, QUOT_EN

A signal for controlling the calculation block 134.

CIN indicates whether ADD (adder) 134a provides the calculation result of register (X) 133a and register (Y) 133b or adds one more to it. DIV_START informs DIV (divider) 134d of the start of division.

Also, QUOT_EN indicates when the result quotient of division is output from the DIV 134d. This signal should be enabled by a delay of DIV 134d from the start of division.

The start signal is not necessary for the other blocks included in the calculation block, that is, ADD 134a, SUB (subtractor) 134b, and MUL (multiplier) 134c. The moment ADD, SUB, or MUL receive data from register (X) and / or register (Y), they do not wait for the start signal. The signal corresponding to QUOT_EN is not used for ADD, SUB, and MUL. Upon completion of the calculation, the ADD 134a, SUB 134b, and MUL 134c immediately output the result. ADD and SUB can output results without delay and MUL and DIV can output results after a preset delay.

(5) OP_SEL

The MUX 135 selects one of the calculation results obtained from the calculation block 134. The calculation block 134 performs addition, deceleration, power, and division using the corresponding blocks, that is, ADD 134a, SUB 134b, MUL 134c, and DIV 1346. In addition to these four operations, the calculation block 134, together with the MUX 135, serves to compare two data, namely, A and B from the register (X) and the register (Y). The comparison is to subtract one data B from another data A and select A or B according to the sign of the subtraction result. As shown in FIG. 4, the MSB or sign bit of the output of the SUB 134b forms one bit of OP_SEL, which affects the selection result. For example, when the sign is '+', A is selected as the output of the MUX 135 and vice versa.

(6) TO_RAM_SEL

This is valid when data from the arithmetic unit 130 is stored in the RAM 160. It also shows which of the inputs of the MUX 137, i.e., the input from the MUX 132a and the input from the barrel shifter 136, is provided to the RAM 160.

Next, detailed blocks of the arithmetic unit 130 will be described by taking a process of obtaining T _i as in the following equation.

In the above formula I will explain the process of obtaining. This process consists of ten steps: At each stage, the control signals to be provided by the state machine 120 to perform the tasks assigned to that stage are specified along with their function. The remaining control signals that are not specified in each step are Don't Care, which means that these signals are irrelevant to perform the task.

[1] Read X _i from RAM 160 into register (X) 133a RD_ADRS: Address of X _i in RAM 160

FR_RAM_PNT: '0' (meaning that data from RAM 160 is not multiplied by 2 ⁿ )

FR_EXT_SEL: Select output from barrel shifter 131

REG_EN_X: Enables register (X) for one clock to prevent other extraneous data from being written to register (X) at the position X _i .

[2] Read K _p from RAM 160 into register (Y) 133b

RD_ADRS: Address of K _p in RAM 160

FR_RAM_PNT: 'O'

FB_SEL: Select output from barrel shifter 131

REG_EN_Y: Enables register (Y) for one clock to prevent other extraneous data from being written to register (Y) at K _{p 's} .

[3] Read N _p and start X _i · K _p .

Two tasks are done at the same time. In order to start the X _i K _p · control signal is not required.

The following is to read N _p .

RD_ADRS: Address of N _p in RAM 160

FR_RAM_PNT: '0'

FR_EXT_SEL: Select output from barrel shifter 131

REG_EN_X: Enables register (X) for one clock.

[4] Read X _p from RAM (160)

RD_ADRS: Address of X _p in RAM 160

FR_RAM_PNT: '0'

FB_SEL: Select output from barrel shifter 131

REG_EN_Y: Enables register (Y) for one clock.

[5] Start of N _{pX P}

No control signal is needed.

[6] X _i · K _p Exit and write the result to RAM 160.

OP_SEL: Selects the output of the MUL 134c.

WIN_PNT: '0' (meaning that 2 ⁿ is not multiplied by the data from MUX (135))

T0_RAM_SEL. Select the output of barrel shifter 136 and provide it to RAM 160.

[7] coming from the RAM (160) reads the X _i K _p ·

RD_ADRS: address of X _i · K _p from the RAM (160)

FR_RAM_PNT: '0'

FR_EXT_SEL: Select output from barrel shifter 131

REG_EN_X: Enables register (X) for one clock.

[8] N _p · X _p Exit and feed back the result to register (Y)

OP_SEL: Selects the output of the MUL 134c.

WIN_PNT: '0'

FB_SEL: Select the output from the barrel shifter (13d)

REG_EN_X: Disables register (X) for one clock.

REG_EN_Y: Enables register (Y) 133b for one clock.

[9] start

DIV_START: Notifies start of division at DIV (134d)

[10] Exit and write the result to RAM 160

QUOT_EN: Combine division result with MUX 13E

OP_SEL: Selects the output of the DIV 134d.

WIN_PNT: '0'

TO_RAM_SEL: selects the output of the barrel shifter 136

ST_WR_ADRS: Address to write

ST_WR_EN: enable the writing operation of RAM 160

As described above, in the same manner as described in the steps [1] to [10] Is calculated and stored in RAM 160. This result is also input to register (Y) 133b with the help of FB_SEL and REG_EN_Y. Then, steps [17] to [17] are continued.

[11] Read to register (X) (133a)

Similar to step [1]. This data is stored in RAM 160 in step [10].

[12] Calculate and store the result in register (Y)

CIN: Means an additional one

OP_SEL: Selects the output of ADD 134a.

WIN_PNT: '0'

FB_SEL: selects the output of the barrel shifter 136

REG_EN_Y: Enable for 1 clock

[13] Reading R from RAM 160 into Register (X) 133a

Same as step [1].

[14] Calculation start

DIV_START: Notifies start of division at DIV (134d)

[15] Compute and input the result to register (Y)

QUOT_EN: Combine division results with MUX 135

OP_SEL: Selects the output of the DIV 134d.

WIN_PNT: '0'

FB_SEL: selects the output of the barrel shifter 136

REG_EN_Y: Enable for 1 clock

[16] RAM 160 to Register (X) 133a Read

Same as step [1].

[17] Compare and select a large one to store in the RAM (160).

OP_SEL: Selects one of the outputs of register (X) and register (Y) according to the MSB of the output of SUB 134b.

WIN_PNT: '0'

T0_RAM_SEL: selects the output of the barrel shifter 136

ST_WR_ADRS: address to write T _i

ST_WR_EN: enable the writing operation of RAM 160

By performing the above processes one by one, T _i of Equation 4A is calculated, which adds, multiplies, divides, compares and retrieves data from RAM 160 and stores data in RAM 160. Include. Other equations can be calculated in a similar way. By obtaining the result of the above equations, three tasks performed by the controller 100 of the present invention are performed.

Claims (10)

A controller for determining an inter / intra mode, a field / frame mode and a quantization coefficient used in a video signal encoding system, wherein the video signal includes a plurality of GOPs, each GOP The picture is divided into three types of pictures, each picture is divided into a plurality of mask blocks, and the encoding system encodes a video signal in units of macroblocks, wherein the controller is configured to indicate the type of picture that is currently encoded and the start of the picture. A state machine for generating a control sequence including a plurality of control signals in response to a signal: a predetermined series based on a serial number and a predetermined initial constant value of a currently-encoded macroblock in response to the control sequence. An arithmetic unit that generates a group of control values for each macroblock of a picture by calculating an equation of. The value is an arithmetic unit meaning inter / intra mode, field, / frame mode, quantization coefficient; And a memory and an input / output unit for storing an initial constant value, supplying an initial constant value to the arithmetic unit, storing a group of control values determined in the arithmetic unit, and providing a control value used in a video encoding process. Controller. 2. The apparatus of claim 1, wherein the memory and input / output unit comprises: memory means for storing an initial constant value and a control value; Reading means for providing control values in response to the control sequence; And write means for inputting and storing control values into said memory means in response to a control sequence. The method of claim 2, wherein the control sequence; A write address signal indicative of the position of the memory means in which the initial constant value and the control value are stored; A write enable signal that becomes active when an initial constant value or a control value is stored in the memory means; And a read address signal indicative of the position of said memory means provided with an initial constant value and a control value. The method of claim 2, wherein the arithmetic unit further comprises: generating a temporary value obtained in the process of calculating a predetermined series of equations; A temporary value is further stored in said memory means; The reading means further provides a temporary value in response to a control sequence; And said writing means further inputs and stores temporary values into said memory means in response to a control sequence. 5. The apparatus of claim 4, wherein the control sequence comprises: a write address signal indicating an initial constant value, a position of the memory means in which a control value temporary value is stored; A write enable signal which becomes active when an initial constant value, a control value or a temporary value is stored in the memory means; And a read address signal indicative of the location of said memory means provided with an initial constant value, a control value and a temporary value. 2. The apparatus of claim 1, wherein the arithmetic unit comprises: first input means for selecting a first input value from among a first group of input values; Second input means for selecting a second input value from among a second group of input values, the second group including second input means including a first input value selected from the first input means; A first register and a second register for storing the first input value and the second input value, respectively; Calculation means for performing an addition, subtraction, multiplication, and division comparison operation on the first input and the second input to provide a group of calculation results including an addition result, a subtraction result, a multiplication result, and a division result comparison calculation result; Selecting means for selecting one of the calculation results; And output means for providing the selected calculation result or the first input to the second input means as one of the input values or to the memory and the input / output means. 7. The apparatus of claim 6, wherein the calculating means comprises: adding means for providing an addition result by adding the first input value and the second input value; Subtraction means for subtracting the second input value from the first input value to provide a subtraction result including an absolute coded value; Multiplication means for multiplying the first input value and a second input value to provide a multiplication result after a first delay set after the first input and the second input are input; And dividing means for dividing the first input value by a second input value to provide a division result after a predetermined second delay after the first input and the second input are input. 4. The apparatus of claim 3, wherein the arithmetic unit comprises: first input means for selecting a first input value from among a first group of input values; Second input means for selecting a second input value from among a second group of input values, the second group including second input means including the first input value selected from the first input means; A first register and a second register for storing the first input value and the second input value, respectively; Calculation means for performing an addition, subtraction, multiplication, and division comparison operation on the first input and the second input to provide a group of calculation results including an addition result, a subtraction result, a multiplication result, and a division result comparison calculation result; Selecting means for selecting one of the calculation results; And output means for providing the selected calculation result or the first input to the second input means as one of the input values or to the memory and the input / output means, wherein the calculation means comprises: the first input value and the second input; Adding means for providing an addition result by adding a value; Subtracting means for subtracting the second input value from the first input value to provide a subtraction result including an absolute coded value; Multiplication means for multiplying the first input value and a second input value to provide a multiplication result after a first delay set after the first input and the second input are input; And dividing means for dividing the first input value by a second input value to provide a division result after a predetermined second delay after the first input and the second input are input. 9. The method of claim 8, wherein the control sequence comprises: a first input value and a second input value of the first group of input values and the second group of input values in response to the first input selection signal and the second input selection signal, respectively; A first input selection signal and a second input selection signal selected; A first register enable signal and a second register enable signal in which the first register and the second register store the first input value and the second input value, respectively, in response to the first register enable signal and the second register enable signal; ; An addition control signal indicating whether the addition means adds one more to the addition result; A division start signal in which the division means starts division in response to the division start signal; A dividing end signal for notifying when dividing ends in the dividing means; The selecting means selects one of the calculation results in response to the operation selection signal, and when the comparison operation result is selected, the selection means selects the first input or the second input in response to the sign of the operation selection signal and the subtraction result. A selection signal; And a selection signal which, in response to the selection signal, provides the selected calculation result or the first input value to the second input means as one of the input values or to the memory and the input / output means in response to the selection signal. A controller for determining an inter / intra mode, a field / frame mode and a quantization coefficient used in a video signal encoding system, wherein the video signal includes a plurality of GOPs, each GOP The picture is divided into three kinds of pictures, each picture is divided into a plurality of macroblocks, and the encoding system encodes a video signal in units of macroblocks, wherein the controller is configured to indicate the type of picture that is currently encoded and the start of the picture. Means for generating a control sequence comprising a plurality of control signals and providing a signal representing the serial number of the currently encoded macroblock in response to the signal and the signal indicative of the beginning of the macroblock: currently encoded in response to the control sequence By calculating a predetermined series of equations based on the macroblock serial number and a predetermined initial constant value, Of an arithmetic unit for generating a control value for a group, for each macroblock, the arithmetic unit for controlling the value of said set means the inter / intra mode, a field, / frame mode, the quantized coefficients; And a memory and an input / output unit for storing an initial constant value, supplying an initial constant value to the arithmetic unit, storing a group of control values determined in the arithmetic unit, and providing a control value used in a video encoding process. Controller.