KR100206917B1 - Both direction global bitline sensing circuit of memory cell - Google Patents

Abstract

The present invention relates to a technique for reducing the electrical capacity of a bidirectional global bit line to facilitate sensing of a memory cell. In a conventional memory cell, a sense amplifier is connected to each bit line so that the layout area is unnecessary by the sense amplifier. There are defects such as large defects, small noise margins, and unstable operation conditions, and a large amount of power is consumed by the refresh operation.

Accordingly, in order to solve this problem, the present invention divides the global bit line pair bidirectionally by using a MOS transistor and a switch signal, and separates the local bit line pair by using another switch signal and a plurality of MOS transistors. A BMGB array element is configured to be connected to a desired global bit line in a pair, and an array is configured by serially connecting such a plurality of elements between respective sense amplifiers, and a plurality of such arrays are provided. By connecting the I / O control unit in both directions of the global bit line pair to selectively output the I / O data according to the bit line selection signal, the number of use of the sense amplifier can be reduced, and only a part of the global bit lines can be used by using the switch signal during the initial operation. Activate to power off the global bitline By limiting the capacity, the noise margin can be improved.

Description

Bidirectional Global Bitline Sensing Circuit of Memory Cells

1 is a schematic block diagram of a bidirectional global bitline sensing circuit of a typical memory cell.

2 is a detailed block diagram of a bidirectional global bitline sensing circuit of a typical memory cell.

3 is a waveform diagram of each part of FIG.

4 is a block diagram showing an embodiment of a bidirectional global bitline sensing circuit of a memory cell of the present invention.

5a to c illustrate an implementation of a BMGB array element in FIG.

6 is a timing diagram of a sensing operation of a memory cell according to the present invention.

7 is a to f is a refresh operation timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

41: BMGB array element 42A-42D: array

43A, 43B: input / output controller 44: DRAM cell

The present invention relates to a technique for reducing the electrical capacity of a bidirectional global bitline to facilitate sensing of a memory cell, and in particular, a method of reducing the number of use of a sense amplifier and limiting the capacitance of the global bitline during initial sensing. As a result, the present invention relates to a bidirectional global bit line sensing circuit of a memory cell that improves a noise margin and is suitable for operating only a part of global bit lines in a refresh mode.

FIG. 1 is a schematic block diagram of a bidirectional global bit line sensing circuit of a general memory cell. FIG. 2 is a block diagram illustrating this in more detail. As shown therein, a word line WL1-WL4 signal and a bit line BL are shown. ₁ , BL _1b -BL _K , BL _Kb ) Cell array (1) that stores the data supplied from the outside under the control of the signal in a matrix cell or outputs the already stored data to the outside through the corresponding bit line. ; An equalizer 2 for equalizing the pair of bit lines BL ₁ , BL _1b -BL _K , BL _Kb under the control of the equalization signal BLEQ supplied from the outside; A sense amplifier unit 3 for amplifying and outputting a sensing signal output to the outside through the bit lines BL ₁ , BL _1b -BL _K , BL _Kb to an appropriate level, or for amplifying and outputting a signal input through an opposite path. Wow; It is composed of an input and output control unit 4 for outputting the signal amplified by the sense amplifier unit 3 to the input and output terminals (IO ₁ , IO _1b -IO _K , IO _Kb ) or to supply a signal supplied in the opposite path, A sensing operation of the conventional memory cell configured as described above will be described with reference to FIG. 3.

If any one of the word lines WL1-WL4 transitions from the ground potential Vss to Vcc + ΔV (ΔV is greater than 0) as in (a) of FIG. 3, the cell capacitors C _BL1 and C Bit line precharged to 1/2 Vcc by charge sharing when charge stored in the corresponding capacitor Cs among _BL1b -C _BL1 and C _BLKb is _outputted through _NMOS . As shown in (c) of FIG. 3, a charge difference of ΔV is generated between BL and bit line BLB.

Thereafter, as shown in (b) of FIG. 3, the equalization signals BLEQ and SAEQ transition from high to low, and the sense amplifier control signal SN goes from low to high, and the sense amplifier control signal SP _b goes high. As it transitions from low to low, the sense amplifiers SA _{1 to} SA _K operate, which causes the potentials of the bit lines BL and BLB to shift to the ground potential Vss and the power supply terminal voltage Vcc, respectively. Done.

Sensing is completed by such a series of operations. At this time, when the selection signal Y _{SE L1} transitions to high as shown in (d) of FIG. 3, the NMOSs NM10 and NM11 are turned on. Signals sensed to the input / output terminals IO ₁ and IO _1b are transmitted through NMOS 10 and NM11 to recognize them externally.

Here, the voltage difference ΔV generated between the bit line BL and the bit line BLB is represented by a relation between C _s , which is the capacitance of the cell 1A itself, and C _BL , which is the capacitance of the bit line. Assuming that the bit line is precharged to Vcc / 2, this is expressed as

As shown in Equation 1, ΔV, which is related to the noise margin of the sense amplifiers SA ₁ -SA _K , can be seen as a ratio of cell capacitance and bit line capacitance.

However, such a conventional memory cell has a defect in which a sense amplifier is connected to each bit line so that the area of the layout is unnecessarily large by the sense amplifier, a defect in which an operation state is unstable due to a small noise margin, and a refresh operation. There is a defect such as a lot of power consumption.

Accordingly, an object of the present invention is to reduce the number of use of the sense amplifier, improve the noise margin by limiting the capacitance of the global bit line during the initial sensing, and memory cells to operate only a part of the global bit line in the refresh mode To provide a bidirectional global bit line sensing circuit.

4 is an exemplary diagram illustrating a bidirectional global bitline sensing circuit of a memory cell of the present invention for achieving the above object. As shown in FIG. A sense amplifier (SA _1.1 , SA) having a BMGB (BiGB Matching Global Bitline) array element 41 for connecting two local bit line pairs to any one of the separated global bit lines according to a switch signal. _2.1 ), (SA _1.2 , SA _2.2 ), (SA _1.3 , SA _2.3 ), (SA _1.4 , SA _2.4 ) are connected in series to each of the four BMGB array elements 41 as described above, so that a total of 16 elements 41 ) Configures one array 42A and cascades arrays 42B, 42C, and 42D such as array 41A to the array 41A, and the four global bit line pairs as described above. I / O control unit 43A, in both directions of ( 43B) is configured to selectively output the input / output data according to the bit line selection signal. The operation and effect of the present invention configured as described above will be described in detail with reference to FIGS. 5 to 7.

First, referring to FIG. 4, the overall operation process will be described. Four sense amplifiers are connected to one global bit line pair GBL1 and GBL2, and a BMGB (B) between the sense amplifier SA and the SA. BMGB: Bidirectional Matched Global Bitline (BMGB) array elements 41 are formed in a total of 16 BMGB array elements 41 per global bit line (GBL).

Further, the input / output control units 43A and 43B are arranged in both directions of the global bit line GBL, and the input / output data IO DATA is selectively output therefrom by the bit line selection signal.

The switch signals SW supplied to the BMGB array element 41 serve to separate the global bit line GBL inward, so that different data appear on both input / output controllers 43A and 43B.

An operation example of each structure of the BMGB array element 41 will now be described with reference to FIGS. 5A to 5C.

First, FIG. 5A illustrates an embodiment of a BMGB array element 41 having a structure of a folded local bit line. As illustrated therein, one word line among a plurality of word lines WL1-WLn is illustrated. When high, the upper switch signal BSU becomes high, the NMOS NM52-NM55 turns on, the lower switch signal BSD turns low, the NMOS 56-NM59 turns off, and the switch signal SW Becomes low, and the NMOS NM50 and NM51 are turned off.

Accordingly, the upper and lower global bit lines GBL1 and GBL2 and GBL1 'and GBL2' are separated, so that the local bit line pairs LBL1 and LBL2 at the upper right are upper global bit lines GBL1 and GBL2. On the other hand, the local bit line pairs LBL3 and LBL4 on the upper right side are connected to the lower global bit lines GBL1 'and GBL2'.

However, when one word line of the word lines WLn + 1-WLn + m becomes high, the upper switch signal BSU becomes low, the NMOSs NM52-NM55 are turned off, and the lower switch signal BSD is turned off. NMOS (NM56-NM59) is turned on to become high, and switch signal (SW) is turned low to turn off NMOS (NM50) and (NM51).

Accordingly, the lower right local bit line pairs LBL1 'and LBL2' are connected to the upper global bit lines GBL1 and GBL2, while the lower right local bit line pairs LBL3 'and LBL4' are lower global bit lines. (GBL1 ', GBL2').

In addition, FIG. 5B illustrates an embodiment of the BMGB array element 41 having a structure of a folded local bit line but sensing in an open bit line form. As shown in FIG. 5B, the word lines WL1-WLn are illustrated. When the odd-numbered word line becomes high, the upper switch signal BSUA becomes high and the upper switch signal BSUB becomes low, and one bit line signal of the lower switch signals BSDA and BSDB is high, and the other is Goes low.

Accordingly, the activated local bit line among the upper left local bit lines LBL1 and LBL2 is connected to the lower right global bit line GBL2 ', and activated among the lower left local bit line pairs LBL1' and LBL2 '. One local bit line is connected to the global bit line GBL1 'at the lower left. At the same time, the active local bit line on the upper right is connected to the global bit line (GBL2) on the upper right, and one of the local bit lines (LBL3 ', LBL4') on the lower right is connected to the global bit line (GBL1) on the upper left. do.

At this time, when the switch signal SW is supplied low, the NMOS 60 connecting the global word lines GBL1 and GBL1 'and the NMOS 61 connecting the global word lines GBL2 and GBL2' are connected. Since they are turned off, the respective bit line signals appear through the upper and lower global word lines GBL1 and GBL1 'and GBL2 and GBL2'.

Therefore, each of the local bit lines LBL1, LBL2, LBL1 ', and LBL2' are sensed in the form of open bit lines, and the global bit lines GBL1, GBL1 ', and GBL2, GBL2' are grounded. It is sensed in the form.

On the other hand, when the even-numbered word line becomes high among the word lines WL1-WLn, the operation method is different from the case where the odd-numbered word line becomes high except that the roles of the upper switch signals BSUA and BSUB are changed. same. In addition, when one of the word lines WLn + 1-WLn + m becomes' high, the operation method is the same as above except that the roles of the upper switch signal BSU and the lower switch signal BSD are changed. Do.

5C shows an embodiment of the BMGB array element 41 in the form of an open bit line, and as shown therein, any one of the word lines WL1-WLn and (WLn + 1-WLn + m). When the word line of the signal becomes high, the switch signal SW goes low, and the NMOS NM70 and NM71 are turned off, which causes the upper and lower global bit lines GBL1, GBL2, and GBL1 ', GBL2'. This is separated into up and down. At this time, the switch signal BS is supplied high to turn on the NMOSs NM72 and NM73.

Accordingly, the upper left local bit line LBL1 is connected to the lower right global bit line GBL2 ', and the lower left local bit line LBL1' is connected to the lower left global bit line GBL1 '. In addition, the upper right local bit line LBL2 is connected to the upper right global bit line GBL2, and the lower right local bit line LBL2 ′ is connected to the upper left global bit line GBL1.

That is, the left local bit line pairs LBL1 and LBL1 'of the open bit line type are connected to and sensed by the global bit lines GBL2' and GBL1 'of the ground type bit line pair. The five-sided local bit line pair LBL2 and LBL2 'are connected to the global bit lines GBL2 and GBL1 of the ground type bit line pair and sensed.

As a result, the BMGB array element 41 shown in FIGS. 5A-C has a global bit line and a local bit line, and the global bit line is separated by a switching transistor in the middle so that the data of the local bit line is separated. It is intended to be transferred to the bit line.

On the other hand, the operation timing of the present invention will be described with reference to the timing chart of a-i in FIG.

In the idle state, the word line WL is low and all bit lines are State, all the switch signals SW are in the Vcc + Δ state. Here, Δ refers to a voltage higher than the threshold voltage of NMOS.

First, when an arbitrary word line is selected, the switch signal SW of the BMGB element to which the word line belongs is brought low as shown in FIG. 6B, and at the same time, the BMGB array element 41 activated in the arrays 42A-42D. The switch signal SW of the element closest to the activated array in the neighboring array of the arrays is taken low as shown in (c) of FIG.

Then, when the word line WL becomes high at Vcc + Δ, a potential difference of ΔV due to the charge output from the DRAM cell 44 is generated between the corresponding local bit line pairs, which is in the BMGB array element 41. It is delivered to global bit line through NMOS used as block selection switch.

After that, when sense amplifier enable signals such as (e) of FIG. 6 are supplied to sense amplifiers on both sides of the activated array, upper and lower global bit lines (GBL) and (GBL ') are first isolated. The potential of the bitline is transferred back to the local bitline pair.

Once the sensing operation has been performed for some time, when the switch signal SW of the BMGB array element 41 closest to the outside of the activated array becomes high again (Vcc + Δ), the charge distribution action of the external global bit line occurs, and thus activation is performed. The potential difference is reduced in the global bit lines within the array, while a new potential difference is generated in the other global bit lines.

Thereafter, when the remaining sense amplifiers are enabled, the potentials of all global bit lines open at Vcc / Vss, and the local bit lines open at Vcc / Vss, and the DRAM cell 44 is recharged. Once the potential difference appears in the bit lines connected to the input / output control units 43A and 43B, the read operation is performed because the output signal can be output as input / output data using the input / output selection signal.

In addition, the refresh operation timing according to the present invention will be described with reference to Figs. 7A to 7F.

This method is only possible if the normal / refresh operation is already determined at entry of the cycle, such as CBR refresh. During the refresh operation, data read from the DRAM cell 44 does not need to be transferred to the input / output controllers 43A and 43B, so that the most activated data is activated in the adjacent array of the array having the BMGB element activated as in the normal cycle. It is not necessary to switch the switch signal SW of a nearby element low and then to high again.

Therefore, the global bit line in the activated array is recharged in the DRAM cell 44 in a state separated from the input / output controllers 43A and 43B. Here, it should be noted that since the global bit lines in the activated array are operated in a separated state, in FIG. 4, refresh operations may be simultaneously performed in two activated arrays. That is, the arrays 42A and 42C or the arrays 42B and 42D can be refreshed at the same time.

As a result, the refresh operation according to the present invention is performed only on some global bit lines, thereby reducing power consumption during the refresh operation, and simultaneously performing refresh operations on blocks separated into different arrays. It is possible to reduce the number of cycles at which the refresh operation of 44 is completed, thereby alleviating the refresh characteristics of the DRAM cell 44.

In addition, it is possible to improve the noise margin by limiting the capacitance C _B / C _S of the global bit line by activating only a part of the global bit lines by using the switch signal during the initial operation.

Using a MOS transistor and a switch signal, the global bit line pair can be separated in both directions, and another switch signal and a plurality of MOS transistors can be used to connect a local bit line pair to a desired global bit line among the separated global bit line pairs. A BMGB array element is configured, and an array is configured in such a manner that a plurality of such elements are connected in series between respective sense amplifiers. A plurality of such arrays are provided, and an input / output control unit is bidirectionally provided with a plurality of global bit line pairs. It can reduce the number of use of sense amplifier by selectively outputting I / O data according to the bit line selection signal, and limit the capacitance of global bit line by activating only some global bit lines by using switch signal during initial operation. Improved noise margin There are effects that can kill.

Claims (4)

And a BMGB array element 41 for separating the global bit line pair bidirectionally according to the switch signal and respectively connecting a plurality of local bit line pairs to any one of the separated global bit lines according to another switch signal. A predetermined number of BMGB array elements 41 are respectively provided between the sense amplifiers SA _1.1 , SA _2.1 , SA _1.2 , SA _2.2 , SA _1.3 , SA _2.3 , and SA _1.4 , SA _2.4 . In series connection, one array 42A is configured, and array 42B, 42C, and 42D such as the array 41A are cascaded to the array 41A, and a plurality of global bits as described above. A bidirectional global bit line sensing circuit of a memory cell, characterized in that the input / output control units (43A) and (43B) are connected in both directions of a line pair to selectively output input / output data according to a bit line selection signal. The NM50 of claim 1, wherein the BMGB array element 41 separates the global bit line pairs GBL1 and GBL2 and GBL1 'and GBL2' in both directions under the control of the switch signal SW. (NM51); Under the control of the upper switch signal BSU, the local bit lines LBL1 and LBL2 are connected to the global bit line pairs GBL1 and GBL2, or the local bit lines LBL3 and LBL4 are global. NMOS NM52-NM55 connected to the bit line pairs GBL1 'and GBL2'; Under the control of the lower switch signal BSD, the local bit lines LBL1 and LBL2 are connected to the global bit line pairs GBL1 and GBL2, or the local bit lines LBL3 and LBL4 are global. A bidirectional global bit line sensing circuit of a memory cell comprising NMOS (NM56-NM59) connected to bit line pairs (GBL1 ') and (GBL2'). The NM50 of claim 1, wherein the BMGB array element 41 separates the global bit line pairs GBL1 and GBL2 and GBL1 'and GBL2' in both directions under the control of the switch signal SW. (NM51); Under the control of the upper switch signals BSUA and BSUB, the local bit lines LBL1 and LBL2 are connected to the global bit line pair GBL2 ', or the local bit lines LBL3 and LBL4 are connected to the global bit line pair GBL2'. NMOS NM62-NM65 connected to the global bit line pair GBL2; Under the control of the lower switch signals BSDA and BSDB, the local bit lines LBL1 'and LBL2' are connected to the global bit line pair GBL1 ', or the local bit lines LBL3' and LBL4. A bidirectional global bit line sensing circuit of a memory cell, characterized by consisting of NMOS (NM66-NM69) connecting ') to the global bit line pair (GBL1). The NM70 of claim 1, wherein the BMGB array element 41 separates the global bit line pairs GBL1 and GBL2 and GBL1 'and GBL2' in both directions under the control of the switch signal SW. (NM71); An NMOS connecting the local bit line LBL1 to the global bit line pair GBL2 'under the control of a switch signal BS, or connecting the local bit line LBL2 to the global bit line pair GBL2. NM72), (NM73); The local bit line LBL1 'is connected to the global bit line pair GBL1' under the control of the switch signal BS, or the local bit line LBL2 'is connected to the global bit line pair GBL2'. A bidirectional global bit line sensing circuit of a memory cell, comprising NMOS 74 and NM75.