KR100206845B1 - Image signal processing apparatus for double scanning - Google Patents

Abstract

The present invention relates to a video signal processing apparatus of a simultaneous scanning method of two scan lines, and the conventional interlaced display method has a flicker on a large screen. In particular, in the PAL type TV, the field frequency is 50 Hz. Although the flicker problem of the conventional sequential display device is solved, since the frequency bandwidth of all signals after the scanning converter is doubled, the frequency bandwidth of the Citi drive unit, the horizontal deflection unit, the horizontal deflection coil, and the color CRT should also be doubled. To this end, there is a problem in that the deflection linearity, a switching problem in the flyback section, and the like must be solved. The present invention provides an image processing means for receiving a composite video signal output from a tuner and processing it to output a three primary color signal (R.G.B) to solve the conventional problems; Synchronization separating means for separating and outputting horizontal and vertical synchronization signals and field discrimination signals from the composite video signal; Memory control means for receiving the three primary color signals RGB from the image processing means and converting the three primary color signals according to the horizontal synchronization signal and the field discrimination signal and outputting two three primary color signals, i.e., odd field signals and even field signals; ; Deflection means for receiving the horizontal and vertical synchronization signals and generating a sawtooth signal in synchronization with the synchronization signal to drive a deflection coil; A city driving means for receiving the two three primary color signals of the memory control means and converting them to output the current for driving the cathode of the city; According to the present invention, a two-scan simultaneous scanning method of a video signal processing device comprising a Citiity which simultaneously scans and displays two scan lines at a time according to the output signal of the Citi drive unit and the driving of the deflection coil is made. There is no need to operate with twice the frequency band, twice the deflection speed, twice the memory capacity, and twice the memory access speed, which is the problem of sequential scanning, and it can eliminate flicker, which is the problem of interlaced scanning. .

Description

Image signal processing device of 2 scan line simultaneous scanning

1 is a block diagram of a display apparatus using a conventional interlaced scanning method.

2 is a diagram showing interlaced scanning in FIG. 1;

3 is a diagram showing interlaced scanning in FIG. 1;

4 is a block diagram of a display device using a sequential scanning method.

FIG. 5 is a diagram showing a sequential scanning method in FIG.

6 is a detailed block diagram of the scan conversion section in FIG.

FIG. 7 is an output waveform diagram of each part in FIGS. 1 and 4.

8 is a detailed circuit diagram of a timing controller in FIG.

9 is an embodiment of the present invention.

FIG. 10 is a detailed block diagram of the memory control unit in FIG.

11 is a view showing an electron gun for two-scan simultaneous scan operation.

12 is a detailed circuit diagram of a timing controller in FIG.

13 is a view showing a two-scanning simultaneous scanning operation.

* Explanation of symbols for main parts of the drawings

100: image processing unit 200: synchronization separation unit

300: memory controller 310: timing controller

321-323: 1st-3rd analogue / digital converter

331-333: 1st-3rd field memory

341-343: 1st-3rd digital / analog converter

351-353: 1st-3rd switching unit

400: deflection portion 500: Citi drive unit

600: deflection coil 700: Citi

The present invention relates to a display device of a TV, and in particular, to perform a sequential scan by the two-scanning simultaneous scanning method to eliminate the flicker while the frequency band, deflection speed, memory capacity, memory access speed as the conventional interlaced scanning method The present invention relates to an image signal processing apparatus of a two-scanning simultaneous scanning method.

FIG. 1 is a block diagram of a conventional display apparatus using an interlaced scanning method. As shown in FIG. 1, an image processor 10 for receiving a composite image signal output from a tuner (not shown) and processing the same is output as an RGB signal. ; A city driving unit 11 which receives the R.G.B signal of the image processing unit 10 and converts the R.G.B signal and outputs the current to drive the cathode of the CPT 12; A synchronization separator 13 for separating horizontal (Hsync) and vertical synchronization signals (Vsync) from the composite video signal; A deflection unit 14 which receives the horizontal synchronizing signal Hysnc and the vertical synchronizing signal Vsync of the synchronizing separator 13 and generates a sawtooth wave synchronized with the deflection coil 15 to drive the deflection coil 15; The Citiity driver 11 and the Citi 12 is shown to display the screen according to the scanning of the electron gun (not shown) in accordance with the driving of the planar coil (15).

The operation of the conventional apparatus configured as described above will be described with reference to the accompanying drawings.

First, when a composite video signal is output from the tuner, it is processed by the image processor 10 and output as a three primary color signal (R.G.B). In this case, a color demodulation circuit, a color matrix circuit, and the like are built in the image processing unit 10.

The three primary color signals R.G.B are converted into currents for driving the cathodes of the Citi 12 by the Citi drive unit 11 and are applied to the Citi 12.

The synthesized video signal is separated from the horizontal (Hsynce) and the vertical synchronous signal (Vsync) by the synchronization separating unit 13 and applied to the deflection unit 14, whereby the deflection unit 14 is horizontal (Hysnc). And a sawtooth wave current synchronized with the vertical synchronization signal Vsync to drive the deflection coil 15.

When the sawtooth current flows through the deflection coil 15, a magnetic field is generated, and the magnetic field is refracted by the electron beam generated by the electron gun of the Citi 12 to be scanned on the screen.

In more detail, as shown in FIG. 2, the three primary electron beams generated by the respective electron guns form a point. The line formed by refraction from left to right is called a scanning line.

In this case, the general scanning method is an interlaced scanning method which scans while skipping one scanning line as shown in FIG. In the figure, H represents one horizontal period and N represents the number of scan lines in one field.

However, this interlaced scan results in flicker, which is particularly noticeable on large screens, and in the case of a PAL-type TV, the flicker is much larger because the field frequency is 50 Hz. There was this.

4 is a block diagram of a display apparatus using a sequential scanning method for solving the above problems. As shown in FIG. 4, a composite image signal output from a tuner (not shown) is received and processed as an RGB signal. An image processor 20; A synchronization separator 23 for separating a horizontal synchronization signal Hysnc, a vertical synchronization signal Vaync, and a field discrimination signal FS from the composite video signal; Converting the three primary color signals RGB from the image processor 20 according to the horizontal sync signal Hsync and the field discrimination signal FS from the sync separator 23 to output one frame during one field period. A scan converter 26 for outputting sequential scan signals R ", G ", and B " The deflection coil 25 is driven by receiving a horizontal synchronization signal Hysnc of the scan conversion unit 26 and a vertical synchronization signal Vsync of the synchronization separation unit 23 and generating a sawtooth signal synchronized with the synchronization signal. A deflection portion 24; The city driving unit 21 which receives the sequential scan signals R '', G '' and B '' of the scan conversion unit 26 and converts them to output the current for driving the cathode of the Citi 22. )Wow; The Citiity driver 21 and the Citi 22 to represent the screen according to the scanning of the electron gun (not shown) in accordance with the driving of the deflection coil (25).

The operation is as follows.

First, when a composite video signal is output from the tuner, it is processed by the image processor 20 and output as a three primary color signal (R.G.B). The composite video signal is also output by being separated into a horizontal synchronous signal Hsync, a vertical synchronous signal Vsync and a field discrimination signal FS by the synchronous separator 23.

The scan conversion unit 26 receiving the three primary color signals RGB of the image processing unit 20 sequentially converts them according to the horizontal synchronization signal Hsync and the field discrimination signal FS of the synchronization separation unit 23. The scan signals R '', G '', and B '' are output.

The sequential scan signals R '', G '', and B '' are converted into a current for driving the cathode of the Citi 22 by the Citi driver 21 and are applied to the Citi 22.

At this time, the deflection unit 24 receives a horizontal synchronization signal Hysnc from the scan conversion unit 26 and a vertical synchronization signal Vsync from the synchronization separation unit 23 and generates a sawtooth wave current synchronized with the synchronization signal. To drive the deflection coil 25.

When the sawtooth current flows through the deflection coil 25, a magnetic field is generated, which refracts the electron beam generated by the electron gun of the Citi 22 to be scanned on the screen.

The scan converter 26 is described in more detail as follows.

Since the scan converter 26 must sequentially scan one frame during one field period as shown in FIG. 5, the horizontal deflector 24 must also scan at twice the speed, and the sequential signal (scanned signal) R '', G '', B '') should also have a frequency component twice as high as the original signal (RGB).

In other words, since two scan lines must be scanned while one scan line is scanned, the deflection unit 24, the Citi drive unit 21, the deflection coil 25, and the Citi 22 must be able to process twice the frequency signal. .

FIG. 6 is a detailed block diagram of the scan converter 26. As shown therein, the first to third analog / digital converters respectively receive RGB signals of the image processor 20 and convert them into digital signals. (32-34) (A / D); A first-third frame memory 35-37 which receives an output signal of the first-third analog / digital conversion unit 32-34 (A / D) according to a control signal and stores / outputs the output signal thereof ; First to third digital / analog converters for receiving the outputs of the frame memories 35-37, respectively, and converting them into analog signals and outputting sequential scan signals R ″, G ″, and B ″ ( 38-40) (D / A); The timing controller 31 controls read / write of the first to third frame memories 32 to 34 according to the horizontal synchronization signal Hsync and the field discrimination signal FS.

The scanning converter 26 needs three analog / digital converters 32-34, frame memory 35-37, and digital / analog converters 38-40, respectively. To do the same signal processing for the primary colors.

The process of converting the red interlaced scanning signal R into a sequential signal R '' converts the signal G into a signal G '' and the signal B into a signal B ''. Same as the process of conversion. Therefore, the process of converting the signal R into the signal R '' will be described as an example.

For example, assuming that three primary colors (R.G.B) of the interlaced scanning method as shown in Fig. 7A are input, this signal is an interlaced scanning signal, so that the frame signal is divided into two field signals.

On the frame basis, the odd-numbered scan line is included in the odd field and the even-numbered scan line is included in the even field. At this time, the signal in the odd field is a signal that increases in the step form, and the signal in the even field is a signal that decreases in the step form.

The conventional apparatus as shown in FIG. 1 receives a signal as shown in FIG. 7A and scans it as shown in FIG. Namely, in Fig. 7A, L1-L3-L5... Scanned in odd fields in order, L2-L4-L6... Scanned in even fields in order.

On the other hand, the conventional apparatus as shown in FIG. 4 outputs three primary color signals R '', G '' and B '' which have been scanned and converted as shown in FIG. 7 (f), and scans them as shown in FIG. At this time, the scanning order is L1-L2-L3-L4-L5-L6. This is repeated in odd / even fields, and sequential scanning can eliminate flicker. At this time, the horizontal synchronization signal H '' output from the scan converter 26 is as shown in (g) of FIG.

The operation of the timing controller 31 is described below.

Signals received by the timing controller 31 as input are horizontal synchronization signals Hsync as shown in FIG. 7 (b) and field discrimination signals FS as shown by (c).

From these signals, a memory write clock (WCK), a memory write pointer (WOTR), a memory read pointer (RPTR), a memory read clock (RCK), and a sequential scan horizontal synchronization signal (H '') are generated.

(D) of FIG. 7 is a memory write output waveform diagram, and (e) is a memory read output waveform diagram. As shown therein, the speed of reading from the memory is two times faster than the writing speed of the memory.

The frame memories 35-37 are typically two-dimensional memory arrays in which addresses can be designated by two indices, such as two-dimensional variable arrays used in computer programs. This notation can be expressed as a symbol like M [X] [Y].

The memory write pointer determines the index of X.Y in the memory array represented by M [X] [Y] to determine the position to be written to the memory. The memory write pointer can consist of two counters.

Hereinafter, the configuration of the timing controller 31 will be described in more detail.

8A is a circuit (counter) for determining the X index of the memory write pointer, and b is a circuit (counter) for determining the Y index of the memory write pointer.

The X index is incremented by 1 by the write clock WCK and reset to zero by the horizontal synchronization signal Hsync. This is like a horizontal deflection.

The Y index is incremented by 1 for each horizontal sync signal Hsync, and reset to zero at the rising edge of the field discrimination signal FS. This is like a vertical interlaced scan. At this time, since the field discrimination signal FS is obtained by inverting, when storing the odd field signal in the memory, the Y index value is even.

8c and d are circuits for determining the index X and Y values of the memory read pointer. These circuits operate on the same principle as the eighth and b degrees, where each clock is twice as fast and all bits of Y are obtained at the output of the counter.

As a result, the scan conversion section 26 stores the two field signals of the interlaced scan in the form of a frame, and repeatedly reads the frame signals twice, thereby performing a scan conversion function of outputting one frame for one field period.

As described above, in the conventional interlaced scanning display device, flicker appears on a large screen. Especially, in the PAL TV, the flicker has a problem of appearing larger because the field frequency is 50 Hz, and the conventional sequential display device has flicker. The problem is solved, but since the frequency bandwidth of all the signals after the scanning converter is doubled, the frequency bandwidths of the CIF drive, horizontal deflection, horizontal deflection coil and color CRT must be doubled. There was a problem to solve the switching problem in the back section.

An object of the present invention is to solve the conventional problem by using a method that scans two scan lines at the same time at the same time to eliminate the flicker even with a normal frequency band, deflection speed, memory capacity memory access speed It has an effect.

In order to achieve the object of the present invention, a two-scan simultaneous scan type video signal processing apparatus includes: image processing means for receiving a composite video signal output from a tuner and processing the same to output a three primary color signal (R.G.B); Synchronization separating means for separating and outputting horizontal and vertical synchronization signals and field discrimination signals from the composite video signal; Memory control means for receiving the three primary color signals RGB from the image processing means and converting the three primary color signals according to the horizontal synchronization signal and the field discrimination signal and outputting two three primary color signals, i.e., odd field signals and even field signals; ; Deflection means for receiving the horizontal and vertical synchronization signals and generating a sawtooth signal in synchronization with the synchronization signal to drive a deflection coil; A city driving means for receiving the two three primary color signals of the memory control means and converting them to output the current for driving the cathode of the city; According to the output signal of the Citiity driving means and the driving of the deflection coil is configured to Citiity to scan and display two scan lines at once.

Hereinafter, an embodiment will be described with reference to the operation and effects of the present invention.

9 is an exemplary view of an embodiment of the present invention, which includes an image processor 100 which receives a composite image signal output from a tuner (not shown) and processes the synthesized image signal and outputs the synthesized image signal as an R.G.B signal; A synchronization separator 200 for separating horizontal (Hsync), vertical synchronization (Vsync) and field discrimination signals (FS) from the composite video signal; The three primary color signals R, G, and B from the image processing unit 100 and the horizontal synchronization signal Hsync and the field discrimination signal FS from the synchronization separation unit 200 are received and converted into two three colors. A memory controller 300 for outputting primary color signals R1, G1, B1, R2, G2, and B3; A deflection unit 400 which receives the horizontal (Hsync) and vertical synchronization signals (Vsync) of the synchronization separation unit (200) and generates a sawtooth signal in synchronization with the synchronization signal to drive the deflection coil (600); Citiity driving unit for receiving the two three primary color signals (R1, G1, B1, R2, G2, B3) of the memory control unit 300 and converts them to output the current to drive the cathode of the Citi 700 ( 500); When two electron guns (not shown) are scanned according to the driving of the Citiity Drive part 500 and the deflection coil 600, the Citiity 700 is displayed.

As shown in FIG. 10, the memory controller 300 receives first and third analog / digital converters 321 to 323 which receive respective RGB signals of the image processor 100 and convert them into digital signals. / D); First-third field memories 331-333 for receiving and storing / outputting the output signals of the first-third analog / digital converters 321-323 according to control signals; First to third digital / analog converters 341-343 (D / A) which receive respective outputs of the field memories 331-333 and convert them into analog signals for output; A timing controller 310 for controlling read / write of the first to third field memories 331 to 333 according to a horizontal synchronization signal Hsync and a field discrimination signal FS; Switching the RGB signal of the image processing unit 100 or the output signal of the first-third field memory (331-333) to output two three primary color signals (R1, G1, B1, R2, G2, B3) It consists of the 1st-3rd switching part 351-353.

Operation of an embodiment of the present invention configured as described above is as follows.

First, the schematic operation will be described.

When the synthesized video signal is output from the tuner, the image processor 100 processes the same and outputs the three primary color signals R, G, and B. The sync separator 200 separates the horizontal sync signal Hsync, the vertical sync signal Vsync, and the field discrimination signal FS from the composite video signal.

The deflection unit 400 applies a sawtooth wave current synchronized with the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync of the synchronization separation unit 200 to the deflection coil 600.

At this time, the memory controller 300 receives the three primary color signals R, G, and B of the image processor 100, and the two primary color signals R1, G1, B1, R2, G2, Output B3).

The CFP driver 500 processes the two three primary color signals R1, G1, B1, R2, G2, and B3 and applies them to the Citi 700. Accordingly, the Citi 700 displays a screen displayed by two electron beams that are scanned according to the output signal of the Cifity driver 500 and the deflection coil 600.

In this case, since the three primary color signals R1, G1, B1, R2, G2, and B3 output from the memory controller 300 need to be applied to the Citiity 700 as described above, the Citiity driver 500 may be used. It must be able to handle six signals.

As shown in FIG. 11, the Cititi of the present invention is configured to scan two scanning lines at a time with two electron beams.

In order to emit two beams simultaneously, two electron guns are used for each of the three primary colors red, green, and blue. These electron guns are arranged to be spaced apart by the scanning line interval in the vertical direction.

For details of the operation of the memory controller 300, first, each analog / digital converter 321-323 receives three primary color signals R, G, and B output from the image processor 100, respectively. Convert to a signal.

Accordingly, each field memory 331 to 333 stores / outputs an output signal of the analog / digital converter 341-343 under the control of the timing controller 310.

Each digital / analog converter 341-343 converts the output signals of the field memories 331-333 into analog signals and outputs the analog signals.

Then, each switch 351-353 switches the RGB signal of the image processing unit 100 and the output RGB signal of the digital / analog converter 341-343 in accordance with a control signal to output two three primary color signals R1 and G1. , B1, R2, G2, B3) are output.

In this case, the switches SW1 and SW2 switch and output the red signals R1 and R2, the switches SW3 and SW4 output the green signals G1 and G2, and the switches SW5 and SW6 the blue signals B1 and R2. Output by switching B2).

The capacity of the field memories 331-333 is half smaller than that of the conventional frame memory of FIG. In addition, there is not a read pointer and a write pointer separately, and it is designed to read first at the address indicated by the pointer (PTR) and write to the same address.

Next, the timing controller 310 controlling the field memories 331 to 333 will be described in more detail with reference to FIG. 12.

First, Fig. 12A is a circuit (counter) for outputting an x index value of a pointer designating a memory address. The operation principle thereof is increased by one by a clock signal (difference) as shown in Fig. 8C used in the prior art. Reset by horizontal sync signal (Hsync).

However, the frequency of the input clock CK is not the conventional high frequency as shown in Fig. 7e, but the clock CK as shown in Fig. 7d is used. This means that the read speed does not have to be twice as fast.

However, FIG. 12B is a circuit (counter) for outputting the Y index value of the pointer designating the memory address. The operation principle thereof is increased by 1 for each horizontal sync signal Hsync, as shown in FIG. 8D. Reset on rising edge.

For example, assuming that the interlaced scanning three primary colors signals R, G, and B are input as shown in FIG. 7A, the signals are odd-numbered scan lines L1 and L3 in the odd field as shown in FIG. 7H. , L5... Is a step-increasing signal, and as shown in (i) of FIG. 7, even-numbered scanning lines L2, L4, L6... In the even field are step-down signals.

On the other hand, each of the switches SW1-SW6 are all interlocked switches. For example, the switch SW1 is initially connected to the contact a, and the switch SW2 is connected to the contact b. It is connected. The remaining third and fourth switches SW3 and SW4 and the fifth and sixth switches SW5 and SW6 are in the same state.

The switches SW1 to SW6 are controlled by the field discrimination signal FS. Each of the contacts a is connected to the R, G, and B signals output from the image processor 100, and the contacts b are each To the output of the digital / analog converter 341-343.

On the contrary, when the odd field section passes and the even field section passes, the signal stored in the field memories 331 to 333 becomes an odd field signal. At this time, since the contact point of the switch is changed, the odd field signal inputted in the even field section is outputted through the even switch (SW2, SW4, SW6).

At this time, the odd field signals stored in the field memories 331 to 333 are outputted through the odd number switches SW1, SW3, and SW5. That is, the signals of the odd field and the signal of the even field are output at the same time.

The outputs of the odd-numbered switches SW1, SW3, and SW5 drive the first electron gun of FIG. 11 through the CITIVITY DRIVER 500, and the outputs of the even-numbered switches SW2, SW4, SW6 operate the second electron gun. Drive.

As a result, as shown in FIG. 13, two-scanning simultaneous scanning is performed.

As described in detail above, flicker, which is a problem of the interlaced scanning method, does not have to operate at twice the frequency band, twice the deflection speed, twice the memory capacity, and twice the memory access speed, which are problems of the conventional sequential scanning method. There is an effect that can be eliminated.

Claims (3)

Image processing means for receiving a composite video signal output from the tuner and processing the same to output a three primary color signal (R.G.B); Synchronization separating means for separating and outputting horizontal and vertical synchronization signals and field discrimination signals from the composite video signal; Memory control means for receiving the three primary color signals RGB from the image processing means and converting the three primary color signals RGB according to the horizontal synchronization signal and the field discrimination signal to output two three primary color signals, i.e., odd field signals and even field signals; ; Deflection means for receiving the horizontal and vertical synchronization signals and generating a sawtooth signal in synchronization with the synchronization signal to drive a deflection coil; A city driving means for receiving two three primary color signals of the memory control means and outputting them as a current for driving a cathode of the city; And an output signal of the Citiity driving means and a Citiity which simultaneously scans and displays two scan lines at a time according to the driving of the deflection coil. 2. The apparatus of claim 1, wherein the memory control unit comprises: first-third analog / digital conversion means for receiving respective R.G.B signals of the image processing unit and converting them into digital signals; First to third field memory means for receiving an output signal of the first to third analog / digital conversion means and storing / outputting the output signal according to a control signal; First-third digital / analog conversion means for receiving the output of each field memory means and converting it into an analog signal for output; Timing control means for controlling the read / write of the first to third field memory means in accordance with a horizontal synchronization signal Hsync and a field discrimination signal FS; The first and third switching means for switching the RGB signal of the image processing means or the output signal of the first to third field memory means to output two three primary colors signals Image signal processing device. 2. The apparatus according to claim 1, wherein the CFP receives two three primary color signals from the Citi driving means and simultaneously scans two scanning lines with two electron guns.