KR100190046B1 - Horizontal sync. signal input unit correction apparatus of phase sync. loop - Google Patents

Abstract

The present invention discloses a horizontal synchronizing signal compensator of a phase-locked loop (PPL) used in an on-screen display circuit.

And a horizontal synchronizing signal compensating unit of the phase locked loop. The horizontal synchronizing signal compensating unit includes a one-shot pulse generator, a direct synchronizing signal generator of the window generator, a 10-bit counter, a free run synchronizing signal generator, do.

Therefore, the apparatus for compensating for the horizontal synchronizing signal of the phase-locked loop according to the present invention adjusts the horizontal synchronizing signal input to the phase-locked loop irrespective of the synchronizing signal detection output SYD from (910-20) division of (910-20) So that the input voltage of the voltage controlled oscillator (VCO) of the phase locked loop (PLL) can be prevented from being shifted to one side. In addition, since the input voltage of the voltage controlled oscillator (VCO) of the phase locked loop becomes constant by constantly and logically compensating the horizontal synchronizing signal inputted to the phase locked loop (PLL), stable locking of the phase locked loop is performed Provides a possible effect.

Description

Phase synchronous loop horizontal synchronous signal input stage compensation device

FIG. 1 is a block diagram of a horizontal synchronizing signal input stage compensation apparatus of a phase locking loop according to the present invention.

FIG. 2 is a detailed block diagram of the horizontal synchronizing signal compensator shown in FIG.

FIG. 3 is a detailed circuit diagram of the horizontal synchronizing signal compensating unit shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (PLL) input stage compensation device used in on-screen display (OSD) circuits, and more particularly to a horizontal sync signal input stage compensation device for a phase- .

The phase-locked loop circuit includes a phase detector for comparing the phase difference between the reference signal and the comparison signal and outputting it as a voltage, a low-pass filter (LPF) for adjusting the phase-locked loop sensitivity, a voltage- controlled oscillator (VCO) and a frequency divider that generates the reference signal by dividing the generated frequency by an appropriate frequency.

A synchronous signal input to a phase locked loop (PLL) built in a conventional on-screen display circuit is a composite sync signal obtained by extracting only a sync signal from a composite video signal. .

The first is a method of generating a horizontal synchronizing signal (Hsync.) Through a phase-locked loop if a signal inputted from the outside is judged to be useful through a synchronous signal separator. Second, It is a method of internally generating a horizontal synchronizing signal (Hsync.) Without going through a phase-locked loop.

For example, when using the edge detection mode phase-locked loop, if the edge of the input signal is detected earlier than the edge of the output signal of the voltage-controlled oscillator, the voltage input to the voltage- The frequency of the output signal of the voltage controlled oscillator is increased. On the other hand, if the edge of the output frequency divider signal of the voltage controlled oscillator is detected first, the voltage input to the voltage controlled oscillator is increased until the edge of the input signal is detected, And functions to follow the frequency of the input signal by decreasing the frequency of the output dividing signal of the oscillator.

A synchronous signal detector connected to the rear end of the synchronous signal separator uses internally generated signals to discriminate the use of a synchronous signal for every one frame, so that a normal signal is input during one frame period When an abnormal signal with a very low frequency is input to the phase lock loop, the input voltage of the voltage controlled oscillator (VOC) deviates much from 2.5V.

In the case of NTSC, if the input voltage of the voltage-controlled oscillator of the phase-locked loop is designed to output a horizontal synchronous signal of 15.73 KHz which is 10 times the frequency of 4FSC (14.31 MHz) clock at 2.5 V, A problem arises in the locking operation.

In addition, if the edge of the output frequency dividing signal of the voltage controlled oscillator is detected and the input edge is not detected for a long time, the input voltage of the voltage controlled oscillator keeps rising and deviates much from 2.5 V, The input signal is forcibly generated and input to the phase locked loop occurs.

In order to solve the above problems, the present invention uses an output of a sync signal detector and a 4 FSC clock so that an input voltage of a voltage-controlled oscillator does not deviate to one side, And an object of the present invention is to provide a compensation device for inputting a horizontal synchronization signal of a phase-locked loop which can be similarly controlled.

In order to achieve the above object, there is provided a synchronous signal separator for separating a composite video signal input from the outside into a composite synchronous signal and outputting the composite synchronous signal outputted from the synchronous signal separator, (4) FSC (NTSC: 14.3 MHz) clock, and outputs a high / low level signal to the output terminal of the synchronizing signal detector and the synchronizing signal separator A horizontal sync signal input stage compensation apparatus,

The horizontal sync signal compensation unit

Shot pulse (Sep. Csync.) From the sync signal separator (Sep. Csync.), An output (SYD) from the sync detector and a 4 FSC (NTSC: 14.3 MHz) A shot pulse generator for generating a shot pulse,

A window generator for receiving a one shot pulse from a one shot pulse generator to start counting and resetting and generating a window signal,

A direct sync generator (Direct Hsync) connected to the output (Sep. Csync) of the sync signal separator and an equalization cancel signal (Eq Era Hsync) connected to the window generator to remove the equalization pulse and noise,

A counter reset unit configured to receive a one-shot one-shot pulse generated by a direct synchronization signal generator and configured as an output of a decoder for dividing 910 to reset a 10-bit synchronization counter,

10-bit synchronous counter connected to the output terminal of the counter resets and counting up to 909 in the 4FSC falling edge mode, counting from 0 when the one shot pulse is applied in the middle,

Bit synchronous counter, when the edge of the output (Sep. Csync) of the sync signal separator is not detected even during 20 clocks of the 4 FSC clock, a horizontal sync signal is forcibly generated to generate a free-run sync signal, A free run sync signal generator for generating a compensated sync signal by summing the equalization cancellation signal Eq Era Hsync output from the sync signal generator,

And a sync signal duty determiner for generating a duty reset signal to determine a positive duty of the equalization cancel signal and the free run sync signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a horizontal synchronizing signal input stage compensation apparatus of a phase locking loop according to the present invention.

In FIG. 1, reference numeral 100 denotes a synchronous signal separator, 102 denotes a synchronous signal detector, 104 denotes a horizontal synchronous signal compensator, and 106 denotes a phase locked loop.

The input terminal of the phase locked loop is connected to a synchronous signal separator 100 to which a composite video signal is input and a synchronous signal detector 102 connected to the synchronous signal separator 100 to determine whether a composite synchronous signal is available, And a phase locked loop (106) connected to the output of the horizontal synchronizing signal compensator (104). The phase-locked loop 106 divides the outputs of the phase detector, the voltage-controlled oscillator, and the voltage-controlled oscillator in the edge detection mode and outputs a comparison signal and a final horizontal synchronizing signal.

The operation of the horizontal synchronizing signal input stage compensator of the satellite synchronous loop constructed as described above will be described below.

When the composite video signal is inputted from the outside, the output (Sep Csync) of the synchronizing signal separator 100 is inputted to the horizontal synchronizing signal compensating unit 104 and the synchronizing signal detecting unit 102 through the synchronizing signal separating unit 100 Export. The number of pulses of the output (Sep. Csync) of the synchronizing signal separator 100 inputted to the synchronizing signal separator 100 inputted to the synchronizing signal detector 102 is generated internally of the synchronizing signal detector 102 The output (SYD) of the synchronizing signal detector 102 is at a high level, and when it is a usable composite synchronizing signal that is within the set range, In the synchronous signal, the output SYD of the synchronous signal detector 102 becomes low level. The horizontal synchronizing signal compensating unit 104 receives the output (Sep. Csync) of the synchronizing signal separating unit 100, the output SYD of the synchronizing signal detecting unit 102 and the 4FSC (NTSC: 14.3 MHz) And inputs the compensated horizontal synchronizing signal to the synchronizing loop 106.

FIG. 2 is a detailed block diagram of the horizontal synchronization signal compensator 104 shown in FIG.

In FIG. 2, reference numeral 200 denotes a one-shot pulse generator, 202 denotes a window generator, 204 denotes a 10-bit synchronous counter, 206 denotes a counter reset, 208 denotes a direct synchronization signal generator, And a reference numeral 212 denotes a synchronous signal duty determiner.

The horizontal sync signal compensating unit 104 includes an output Sep. Csync of a sync separator 100, an output SYD of a sync detector 102 and a 4 sync FSC (NTSC: Shot pulse generator 200 connected to the one shot pulse generator 200 and the one shot pulse generator 200 to receive a one shot pulse and to start counting and reset (Direct Hsync) 208 connected to the output (Sep. Csync) of the sync signal separator 100 and generating an equalization elimination signal Eq Era Hsync from which an equalization pulse and noise are removed, A counter reset unit 206 configured by a one-shot pulse of one period generated by the direct synchronization signal generator 208 and an output of a decoder for dividing 910, and a counter reset unit 206 connected to the output terminal of the counter reset unit 206, Is counted up to 909 and when a one shot pulse is applied in the middle, Bit sync counter 204 and an output of the 10-bit sync counter 204 and detects the edge of the output (Sep. Csync) of the sync signal separator 100 during a 20 clock time of the 4 FSC clock Generates a horizontal sync signal to generate a free run sync signal, and outputs an equalization cancellation signal Eq Era Hsync output from the direct sync signal generator 208 and a free run sync signal output from the free run sync signal generator 210, A synchronizing signal generator 210 and a decoder of the counter recalling unit 206 to change the level of the equalization cancellation signal Eq Era Hsync and to generate a duty reset signal to determine a positive duty of the equalization cancellation signal, And a duty determiner 212.

The operation of the horizontal synchronizing signal compensator of the phase locked loop constructed as shown in FIG.

First, a method of generating a compensated horizontal synchronizing signal with reference to the floating signal rising portion of FIG. 1 is roughly divided into two.

First, a window is generated to remove an equalizing pulse and noise from the output (Sep. Csync) of the synchronizing signal separator 100 when the output SYD of the synchronizing signal detector 102 is high, (Sep. Csync) of the synchronizing signal separator 100 is used as a clock to obtain a compensated horizontal synchronizing signal only at a period during which the output signal (Sep. Csync) of the synchronizing signal separator 100 is active, Run horizontal synchronizing signal forcibly to be not detected even after a predetermined time.

Second, when the output (SYD) of the synchronizing signal detector 102 is low, the output (Sep. Csync) of the synchronizing signal separator 100 is not used as a clock, but only the 4FSC clock is divided by 910, .

When the output SYD of the synchronizing signal detector 102 is low, it does not use the output Sep. Csync of the synchronizing signal separator 100 as a clock but divides only 4 FSC clocks 910 to generate a periodic horizontal synchronizing signal .

When the output SYD of the synchronizing signal detector 102 is high and the edge of the output (Sep. Csync) of the synchronizing signal separator 100 is detected by the synchronizing signal generator 208 directly, the equalization removal signal Eq Era The one shot pulse generator 200 generates a one shot pulse by one cycle of the 4 FSC clock of the equalization removal signal Eq Era Hsync. The one shot pulse is input to the window generator 202 and the counter reset unit 206 to disable the window and reset the 10-bit synchronization counter 204 in the 4FSC mode. The output of the decoder including the D flip-flop IC 17 in the window generator 202 when enumerating 890 starts counting again causes the window to be re-enabled to enable the next synchronizing signal separator 100 ) Of the output (Sep. Csync) of the clock signal. In the case of NTSC, since the horizontal synchronizing signal is 15.73 KHz which is 910 division of 4FSC (14.31 MHz), the direct sync signal generator 208 detects the edge of the output (Sep. Csync) of the sync signal separator 100, * (1 / 4FSC) = 62.159 μS, an equalization removal signal (Eq Era Hsync) is generated in which the equalization pulse and the noise signal are removed during the time since no edge signal is received. The sync signal duty determiner 212 serves to reverse the signal after the equalization cancellation signal Eq Era Hsync goes high again. When the count reaches 63 after the counting, the duty reset signal Eq Era Hsync) is determined as 63 * (1 / 4FSC) = 4.4 μS. The operation of the 10-bit counter 204 using the 4FSC Falling Edge Mode clock is as follows.

Bit synchronous counter 204 receives the one shot pulse of one FSFS cycle of the equalization removal signal Eq Era Hsync generated by the direct synchronization signal generator 208 and the output of the decoder for dividing 910, And counts from 0 when the one shot pulse is applied in the middle. Therefore, when the direct sync signal generator 208 detects the edge of the output (Sep. Csync) of the sync signal separator 100, a one shot pulse is generated to disable the window, and at the same time, The 10-bit synchronization counter 204 is reset and counting is started. Disables the window during the 890 dispensing time and waits for the edge of the output (Sep. Csync) of the synchronizing signal separator 100, which is input by Enabling the window for the 891 dispensing time. At this time, if the edge of the output (Sep. Csync) of the sync signal separator 100 is not detected during counting up to 910, counting starts again from 0, and then, even for 20 clocks of 4FSC clock, And waits for the edge of the output (Sep. Csync) At this time, if the edge of the output (Sep. Csync) of the sync signal separator 100 is not detected during counting up to 910, a free run sync signal is generated. When the edge of the output (Sep. Csync) of the sync signal separator 100 is detected again, the above operation is repeated. Therefore, when the output SYS of the synchronizing signal detector 102 is high and the signal of the output (Sep. Csync) of the synchronizing signal separator 100 is a normal signal within the 891-930 frequency division of the 4 FSC clock, Csync of the sync signal separator 100 when the signal of the output (Sep. Csync) of the sync signal separator 100 is a normal signal within the 891-930 frequency division of the 4 FSC clock, However, if the edge is not detected within 9,30 * (1/4 FSC) = 64.95 [mu] S, the operation for forcibly outputting the horizontal synchronizing signal is performed.

Secondly, when the frequency of the output (Sep. Csync) of the synchronizing signal separator 100 is out of the set range and the output SYD of the synchronizing signal detector 102 is low, the output of the synchronizing signal separator 100 (Eq. Era Hsync) is not generated by disabling the signal (Sep. Csync) and generates a free run sync signal (Free Run Hsync), which is a periodic horizontal synchronizing signal 910 divided by 4 FSC clock only Thereby generating a compensated horizontal synchronization signal.

FIG. 3 is a detailed circuit diagram of the horizontal synchronizing signal compensating unit shown in FIG.

In FIG. 3, I1, I2, I7, I11, I15, I18, I23, I24 and I30 are D flip flop ICs and I4, I5, I12, I13, I20, I21, I27 and I28 are NAND gates I14, I9 and I10 are AND gates, I6, I14, I22, I25 and I29 are NOR gates, I19 is an OR gate, I16, I31, I32 and I33 are inverter ICs, I26 is a 10 bit synchronous counter IC.

The one shot pulse generator 200 receives the outputs of the two stages of D flip flop IC I1 and D flip flop IC I2 into the AND gate IC I3 and the one shot pulses output from the AND gate IC I3 To the NOR gate IC I25 of the JK flip flop IC I8 of the window generator 202 and the counter resetting unit 206. [ The window generator 202 outputs the decoded output value from the D flip-flop IC I7 via the NAND gates I4 and I5 and the NOR gate I6 to which the count value from the 10-bit synchronous counter 204 is input, And a JK flip-flop IC (I8). The direct sync signal generator 208 generates a D flip signal through the AND gate IC I9 receiving the window signal output from the JK flip flop IC I8 and the AND gate IC I10 connected to the end of the AND gate IC I9, Flop IC I11 to output an equalization removal signal Eq Era Hsync. The free run sync signal generator 210 includes two NAND gate ICs I12 and I13 connected to the output of the 10 bit synchronous counter 204 and a NOR gate IC I14 and a D flip flop IC I15 and an inverter IC I16, and combined with the 4FSC clock (I17), a free run synchronization signal is output through a D-type flip-flop IC (I18) as a final decoder, and an equalization removal signal Eq Era Hsync) are summed in the OR gate IC I19 to generate a compensating synchronizing signal. The counter reset unit 206 includes two NAND gate ICs I20 and I21 connected to the output of the one-shot one-shot pulse generated by the direct synchronization signal generator 208 and an output of the 10 bit synchronous counter 204, and a NOR gate I22 and two stages of D flip-flops I23 and I24 are sequentially connected to serve as a decoder for dividing 910 and reset the 10-bit synchronous counter 204. [ The 10-bit synchronous counter 204 is connected to the output terminal of the counter resetter 206 and counts up to 910 in the 4FSC falling-edge mode. When the one-shot pulse is applied in the middle, the 10-

The description of the operation is the same as that of the second embodiment and therefore will be omitted.

As described above, the horizontal synchronizing signal floating portion of the phase-locked loop according to the present invention synchronizes the horizontal synchronizing signal inputted to the phase-locked loop 106 regardless of the output SYD of the synchronizing signal detector 102, 910-20) to (910 + 20) divider clock periods, it is possible to prevent the input voltage of the voltage controlled oscillator (VCO) of the phase locked loop (PLL) from being shifted to one side. In addition, since the input voltage of the voltage controlled oscillator (VCO) of the phase locked loop becomes constant by constantly and logically compensating the horizontal synchronizing signal inputted to the phase locked loop (PLL), stable locking of the phase locked loop is performed Provides a possible effect.

Claims (6)

A synchronous signal separator for separating a composite video signal input from the outside into a composite synchronous signal and outputting the composite synchronous signal, and a high / low level decoder for determining whether the composite synchronous signal input from the synchronous signal separator is available, And a horizontal synchronizing signal compensator for receiving the output of the synchronizing signal separator and the output of the synchronizing signal detector and a 4FSC (NTSC: 14.31 MHz) clock to output a compensated horizontal synchronizing signal. (SYS) of the sync signal separator (SYNC) and an output (SYD) of the sync signal detector (SYNC), and a 4FSC Shot pulse generator for generating a one-shot pulse with an input of a clock (NTSC: 14.3 MHz) clock, a first shot pulse from the one shot pulse generator, A window generator for resetting and generating a window signal, an output (Sep. Csync) of the synchronizing signal separator and a direct synchronization signal (Eq) for generating an equalization elimination signal (Eq Era Hsync) A counter reset unit configured to receive a one-shot pulse of one period generated by the direct synchronization signal generator and to output a 10-bit sync counter, the output of the decoder being for dividing 910, A 10-bit synchronous counter connected to the output terminal of the 10-bit synchronous counter and counting up to 909 of the 4 FSC falling edge mode, counting from 0 when a one shot pulse is applied in the middle, When the edge of the output (Sep. Csync) of the synchronous signal separator is not detected even during the time, a forced receipt synchronizing signal is generated, (Eq Era Hsync) output from the synchronous signal generator, and a free run sync signal generator connected to the decoder of the counter resetter to change the level of the equalization cancellation signal (Eq Era Hsync) And a synchronous signal duty determiner for generating a duty reset signal to determine a positive duty of the equalization elimination signal and the free run synchronous signal. The apparatus as set forth in claim 1, wherein the input of the horizontal synchronizing signal compensating unit uses a 4FSC (NTSC: 14.31 MHz) clock and an output of the synchronizing signal detecting unit. 2. The apparatus of claim 1, wherein a mode for generating a direct synchronization signal in accordance with an input signal and a mode for generating a free run synchronization signal irrespective of an input signal are determined by a high / low output (SYD) level of the synchronization signal detector Wherein the horizontal synchronizing signal input terminal compensation unit comprises: 2. The apparatus of claim 1, wherein when the input signal is not detected for a predetermined time in the output mode in which the direct sync signal according to the input signal is generated, the free run sync signal generator generates a free run sync signal similar to the frequency of the horizontal sync signal Wherein the phase locked loop comprises a phase locked loop and a phase locked loop. The phase-locked loop according to claim 1, wherein the counter reset unit resets a one-shot pulse of the equalization sync signal (Eq Era Hsync) and a decoder output for dividing 910 to a 10-bit sync counter through an OR gate A horizontal synchronizing signal input stage compensation device. 2. The method of claim 1, wherein the window generator is set by a one shot pulse of an equalization sync signal (Eq Era Hsync), starts counting from there, and uses a JK flip to reset to the value of the desired decode Wherein the horizontal synchronizing signal input terminal compensation unit comprises: