KR0138935B1 - Graphic control system of dual panel dual driver to control crt and lcd simultaneously - Google Patents

Abstract

The present invention relates to an LCD controller for simultaneously displaying an image on a CRT and a dual-panel dual drive LCD. The present invention relates to an extended graphic controller (1) for controlling a conventional CRT and a horizontal sync signal, a vertical sync signal, a horizontal blank signal, An LCD controller which outputs a line pulse signal, a shift clock signal, and a first line marker using a vertical blank signal, a pixel clock signal, a memory clock signal, and an LCD control information signal ( 2); Display memory (3); It is characterized in that it comprises a frame buffer (4), and when you want to display the image on the CRT and LCD at the same time can be additionally used regardless of the existing graphics controller of the portable computer using the LCD as a display device The design of the graphics controller can be simplified, and the display mode handled by the graphics controller can be larger than that of the existing controller, thereby improving the performance of the graphics system.

Description

Dual Panel Dual Drive Liquid Crystal Display (LCD) Controller

1 is a configuration diagram of a graphic control system to which the present invention is applied;

2 is a detailed configuration diagram of the extended graphic controller,

3 is a detailed configuration diagram of the LCD controller,

4 is a detailed configuration diagram of the LCD interface,

5 is a detailed configuration diagram of the line buffer.

6 is a data structure diagram used in the LCD controller,

7 is a timing diagram of the flame acceleration ON mode operation method,

8 is a timing diagram of a flame acceleration OFF mode operation method.

* Explanation of symbols for main parts of the drawings

1: Extended graphics controller 2: LCD controller

3: CRT4: LCD Module

11: Graphic controller 12: Pallet RAM

13: Multiplexer 14: Digital-to-Analog Converter

15: expansion register 21: data remapping section

22: total control unit 23: flame buffer control unit

24: LCD interface 31: line buffer

32: data path controller 33: control signal generator

41: upper line buffer 42: lower line buffer

The present invention relates to an LCD controller for simultaneously displaying an image on a cathode ray tube (CRT) and a dual-panel dual drive liquid crystal display (LCD).

The present invention is directly applied to the design of a graphic controller used in a portable PC such as a notebook PC (persONal computer) using an LCD as an indicator, and also an application for temporarily storing and manipulating image data continuously displayed regardless of the control of the controller. It can also be applied to the field.

When configuring a circuit for displaying an image on an LCD, many parts of the existing graphic controller need to be modified, similar logic circuits are overlapped, and the access time of the flame buffer and the line buffer is biased during the varnish play period. When using a portion of the display memory, there is a problem that the performance is poor.

Accordingly, the present invention has been made to solve the problems of the prior art, and provides a dual-panel dual drive LCD controller which is installed in parallel without changing the existing graphic controller and balances the access time of the frame buffer and the line buffer. The purpose is.

In order to achieve the above object, the present invention is an overall control unit for generating and outputting a control signal for the LCD display by receiving the vertical and horizontal synchronization signal, the vertical and horizontal blank signal and the LCD control information to the external graphics controller; A data remapping unit which receives digital pixel data from an external graphic controller and rearranges the data into data suitable for the shape of an LCD module under the control of the entire controller; and receives the remapped data output from the data remapping unit. Driving the LCD by receiving a frame buffer controller for inputting and outputting frame buffer data according to the control of the controller and the memory control signal, the output signals of the data remapping unit and the frame buffer controller, and the control signals provided by the entire controller. Upper and lower panel data, line pulse signal, It characterized in that it comprises soft clock signal and the first line display signal LCD interface for outputting the part.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a graphic control system having an LCD controller according to the present invention, wherein the LCD controller 2 stores pixel data in an external frame buffer (not shown). It is connected to the function to send to the LCD module (4). That is, the LCD controller 2 according to the present invention is a horizontal synchronization signal, a vertical synchronization signal, which is a timing signal of the CRT 3 from an extended graphic controller 1, a vertical synchronization signal, Receives horizontal blank signal, vertical blank signal, pixel data, pixel clock signal, memory clock for flame buffer control, LCD control information signal The upper panel data, lower panel data, display clock signal, line pulse signal, first line display required by the LCD module. marker) signal is generated and output.

As the pixel data, the digital pixel data is received as an input instead of the analog signal used in the CRT 3, because the LCD module 4 requires the input of the digital data. The above LCD control information includes information about the size and shape of the LCD module 4 (mono, color, super twisted nematic (STN), thin film transistor (TFT)), and the LCD controller mode. It includes. As a frame buffer, a random access memory (RAM) is externally used, or a part of display memory used by the extended graphic controller 1 is used as a frame buffer. In the conventional extended graphic controller, when a part of the display memory is used as a flame buffer, a communication circuit must be additionally inserted between the extended graphic controller and the LCD controller. However, the present invention can be configured without any need for adding a new function as long as there is enough space for the LCD controller to read and write pixel data, regardless of using an external frame buffer or using a part of the display memory as the frame buffer. Do.

FIG. 2 is an internal configuration diagram of the extended graphics controller 1 of FIG. 1, and the graphics controller is a basic graphics controller 11 without considering the LCD, and has an extended register storing information for LCD control in the controller. registers) (15) is used. There are two paths for the graphic controller 11 to represent image data, which can express 256 colors through the palette RAM 12, and can express 32k / 64k colors directly. In general, pallet RAM 12 is composed of 256 x 18 bits of RAM, and the 18-bit data outputted through the digital multiplexer 13. The data coming out through the multiplexer becomes the final pixel data, and the signal to be transmitted to the LCD controller 2 is output as it is, and for the CRT 5, it is output through the digital-to-analog converter 14.

3 is a block diagram showing the internal structure of the LCD controller 2 according to the present invention, and includes a horizontal sync signal, a vertical sync signal, a horizontal blank signal, a vertical blank signal, a pixel clock signal, and a memory input from the extended graphic controller 1. Receives the pixel data outputted from the entire control unit 22 and the extended graphic controller 1 by generating and outputting a control signal using a clock signal and an LCD control information signal, and rearranges the data according to the shape of the LCD module 6. A frame buffer controller 23 for receiving a data output from the data remapping unit 21, a signal output from the data remapping unit, and a signal output from the entire control unit 22, and outputting frame buffer data and a memory control signal; Receives the frame buffer data output from the CRT data and the CRT data output from the data remapping unit 21 and is controlled by the entire control unit 22. The control signals of the upper panel data, the data sub-panels, and the LCD module and a LCD module (4) LCD interface section 24 for outputting a shows the Available.

The entire controller 22 is designated with the shape and operation mode of the LCD module 4 in the LCD control information output from the extended graphic controller 1. The type of LCD module can be divided into mono and color panels, and the operation modes are designated as acceleration ON and OFF modes. The difference between the mono and the color panels is that the amount of CRT data produced by the data remapping section 21 is different. That is, the color panel requires three times the frame data capacity and the frame bandwidth compared to the mono panel, and the other control signals are the same.

FIG. 4 shows the internal structure of the LCD interface unit 24 of FIG. 3. The data path controller 32 displays the frame buffer data and the frame buffer data that have passed through the current CRT data and line buffer 31. Generate upper panel data and lower panel data according to the data width of the module. That is, as described above, the CRT data and the upper line buffer or the CRT data and the lower line buffer data are used in the frame acceleration ON mode, and the upper line buffer and the lower line buffer data are used in the frame acceleration OFF mode. If the data path of the LCD module is 16 bits (upper 8 bits, lower 8 bits), the incoming data is separated by 2, and when 8 bits (upper 4 bits, lower 4 bits) are separated by 4, it is exported. The control signal generator 33 generates a line pulse, a shift clock signal, and a first line display signal according to the signals sent from the entire controller 22. The control signals used at this time are the horizontal sync and vertical signals sent from the extended graphic controller 1. It is created using the sync, horizontal and vertical blank signals.

The line buffer 31 internally has two first in first out (FiFo) structures. The capacity of each buffer must be able to accommodate half-line data, and the operation of the buffer depends on the frame acceleration mode. The line buffer receives two write signals and writes them separately, and both buffers are shifted out by one read signal. In frame acceleration ON mode, only one of the two buffers is used.

5 shows the internal structure of the line buffer 31. The line buffer is composed of an upper half-line buffer 41 and a lower half-line buffer 42. As shown in FIG. . The upper half line buffer 41 receives the frame buffer data signal, the upper write signal, and the read signal as inputs, and outputs the upper line buffer signal. The lower half line buffer 42 is connected to the frame buffer data. It receives the lower write signal and read signal as inputs, and outputs the lower line buffer signal.

6 shows the data relationship used by the LCD controller 2, and shows the data relationship when displaying a screen having a resolution of 640x480. C1-1 to C480-2 refer to data currently displayed on the CRT 5, and F1-1 to F480-2 refer to data stored in the frame buffer of the CRT data. Therefore, if the CRT wants to display the current C2-1, F1-1 and F1-2 have the same values as C1-1 and C1-2, and F2-1 to F480-2 store the data of the previous frame. . LU1-1 through LU240-2 are data for displaying the upper panel in the LCD module 4.

The flame acceleration ON mode is a mode in which the vertical refresh rate of the LCD is twice the vertical refresh rate of the CRT. That is, when one frame is displayed on the CRT, the LCD displays the same screen twice. Considering these data concerns, the upper panel data and lower panel data of the LCD in flame acceleration ON mode can be configured as follows. If the CRT is displaying C240-2 from C1-1, LU1-1 from LU1-1 on the LCD sends the current CRT data from C1-1 to C240-2, and from LL1-1 to LL240-2. Send F480-2 from F241-1, which is the CRT data of the frame. Then if the CRT is displaying C480-2 on C241-1, LU1-1 on the LCD sends LU240-2 on this frame's CRT data F1-1 on F240-2, and on LL1-1 on LL240-2 Sends C480-2 from the current CRT data C240-1.

Frame acceleration OFF mode displays the same vertical refresh rate of LCD and CRT. The problem with supporting this mode is that CRT data is currently unavailable. That is, when the CRT scans one line, the LCD must display the half line of the upper panel and the half line of the lower panel, and thus use the data in the frame buffer instead of the current CRT data. Should be. At this time, LU1-1 on the LCD displays F1-1, and LL1-1 displays F241-1. When displaying in this manner, a line buffer 31 that reads the upper flame buffer data and the lower flame buffer data in advance from the flame buffer at the speed of sending data to the LCD module 4 is required.

FIG. 7 is a diagram illustrating an example of an operation of the frame acceleration ON mode, and illustrates an operation of the line buffer 31 at the time when the first data is displayed on the CRT. When the first line is displayed on the CRT, the LCD module 6 must write F241-1 to the lower half line buffer 42 in advance to use C1-1 and C1-2 as LU1-1 and LU1-2. The data recorded in this way is read by the data path control at time A, and the data of F241-2 is newly recorded at time B. At point C, the second data of F241-1 is read. At point D, the third data of F241-1 is going out to the lower line buffer, and this data is read by the data path controller at point E, and at point F241- As the second data of 2 is written, the fourth data of F241-1 goes out to the lower line buffer. When data is read and written in this way, at the end of one line, the data of the F241-2 is read again by the data path controller immediately after the last data of F241-2 is written. Is output. If the LCD controller only supports the frame acceleration ON mode, the line buffer 31 may have only half line capacity.

8 is a diagram illustrating an operation method in the frame acceleration OFF mode, in which two buffers are used, which will be described in detail with reference to the drawings.

For example, when the CRT displays the second line, the LCD module should display F1-2 on LU1-2 and F241-2 on LL1-2. During the blank period, F1-2 is recorded in the upper half line buffer 41 in LU1-2 in advance. It is assumed that F241-2 is previously recorded in the lower half line buffer 42 during the display period of the immediately preceding scan line. At the point in time at which the display starts, the data path controller reads the first data of F1-2 recorded during the free period from the upper line buffer and the first data of F241-2 recorded during the previous display period. At time B, the second data of F242-1 to be used in the next scan line is written to the lower half line buffer. Reading and writing data in this manner ensures that at the end of one line, all new data from the last F242-1 of f1-2 is contained. Therefore, the data required in the frame acceleration OFF mode is implemented through the line buffer.

A feature of the operating manner of the line buffer of the present invention is that it makes full use of the free period. This operation balances the overall memory bandwidth required for the flame buffers. In addition, when using a part of the display memory 3 that uses the frame buffer in the extended graphics controller 1, the LCD controller 2 uses a blank period that the extended graphics controller 1 rarely uses. Can be improved.

As described above, the present invention can be used to display images on the CRT and the LCD at the same time, so that the graphic controller of the portable computer using the LCD as a display device can be simply used. The display mode handled by the graphics controller can be larger than that of the existing controller, thereby improving the performance of the graphics system.

Claims (3)

A graphic controller for controlling images on a CRT and an LCD module at the same time, generating a control signal for an LCD display by receiving a vertical / horizontal sync signal, a vertical / horizontal blank signal, and LCD control information from an external graphic controller. An overall control unit 22; A data remapping unit (21) which receives digital pixel data from the external graphic controller and rearranges the digital pixel data into data corresponding to the shape of the LCD module under the control of the entire controller; A flame buffer control unit 23 which receives the remapped data output from the data remapping unit and inputs and outputs flame buffer data according to the control of the entire control unit and the memory control signal; And The output signal of the data remapping unit and the flame buffer control unit is input, and the control signal provided from the entire control unit is input to output upper / lower panel data, line pulse signal, shift clock signal, and first line display signal for driving the LCD. And an LCD interface unit (24). 2. The line buffer 31 of claim 1, wherein the LCD interface 24 receives a frame buffer data and a control signal input from the flame buffer controller and the entire controller, and outputs a line buffer signal and a lower line buffer signal. ); A data path controller 32 receiving CRT data input from the data remapping unit 21, an upper line buffer signal from the line buffer, and a lower line buffer signal and outputting upper panel data and lower panel data; And a control signal generator (33) for receiving a control signal input from the entire control unit and outputting a line pulse, a shift clock signal, and a first line display signal. 3. The apparatus of claim 2, wherein the line buffer comprises: an upper line buffer 41 which receives a frame buffer data signal, an upper write signal, and a read signal as inputs and outputs an upper line buffer signal; And a lower line buffer (42) for receiving the frame buffer data, the lower write signal, and the read signal as inputs, and outputting a lower line buffer signal.