KR0135528B1 - Method for forming a contact via - Google Patents

Abstract

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Description

Contact / via formation method and structure

1 is a vertical cross-sectional view having an oxia layer formed on a silicon substrate or metal layer and a contact / via formed through the oxide layer,

2 is a view showing a structure in which a thin oxide layer is formed on the structure of FIG.

3 is a vertical cross-sectional view of FIG. 2 with the oxide top layer etched away to form sidewall oxide in the contact / via,

4 shows a structure in which a thin layer of refractory metal is formed on the structure of FIG.

5 is a vertical cross-sectional view of the structure of FIG. 4 in which the refractory metal is converted into a barrier layer of the refractory material,

6 is a vertical sectional view of the structure of FIG. 5 having a layer of refractory material formed by CVD on the boundary layer,

6A and 6B are vertical cross-sectional views showing a modification method for forming a CVD layer of the refractory material of FIG. 6, in which a polysilicon layer is formed on the structure of FIG. 5 to form a silicide layer, and a refractory metal layer is formed thereon;

7 is a vertical sectional view of the structure of FIG. 6 having a metal layer sputtered by PVD technology on the substrate.

＊ Description of symbols for main parts of the drawings ＊

12: oxide 14: beer

16,18 side wall 19 contact / via

20: insulation layer 22, 24 sidewall oxide layer

26: fire resistant metal layer 28: TiSi ₂ layer

30: TiN layer 36: polysilicon layer

38: metal layer

TECHNICAL FIELD The present invention relates to contacts and vias (VIA) that are used in semiconductor processes, and more particularly to enhancing step coverage of contacts and vias.

In a semiconductor process, one of the critical process steps is the interconnection between two conductive layers of different levels, which are separated into an insulating layer, especially when one of the conductive layers is an upper metal layer.

The underlying conductive layer is now covered with an oxide layer, and contacts or vias are formed in the oxide layer to expose the surface of the underlying conductive layer in the selected area.

The upper conductive layer is then patterned and connected to the underlying conductor through contacts or vias.

The underlying conductor is made of polysilicon, metal or silicon surface itself.

To ensure the connection between the two layers, it is important that the contact contact area between the underlying metal or silicon has a low resistance without changing its properties, especially if the material is silicon.

It is also necessary to make the resistance between the contact contact area itself and the upper metal layer also have a low resistance value.

One disadvantage of past process technology was the void of the top metal layer appearing on the contact surface or on the vertical surface of the via.

This can come from many factors.

One factor unique to the process is the uneven coverage when sputtering or PVD techniques are used to deposit the metal layer.

Since this is an anisotropic process, a considerably thin metal layer is formed on the vertical wall where the vertical surface of the contact opening or via is thickened along the upper edge of the contact opening or via. The voids typically appear along this vertical surface. This problem can be solved using CVD.

However, CVD processes are not usually suitable for the type of metal required at the top level, such as aluminum metallization processes.

The detailed description and claims of the present invention consist of a method of forming a contact between two conductive layers of different levels.

The silicon substrate or first conductive layer forms a lower level conductor.

This layer is covered with an intermediate level oxide layer.

An opening is formed through this oxide layer and a uniform layer of refractory material is deposited on this structure to cover the sidewall of the opening with a uniform thickness.

This conducts between both levels separated by an intermediate level oxide layer.

The metal layer is then sputtered on the top surface to connect between the top portion of the layer of refractory material and other structures on the top level.

In another embodiment of the present invention, a refractory material is deposited on the bottom surface of the opening adjacent the lower surface and the entire surface of the middle level oxide layer.

Barrier metal is then deposited between the uniform layer of the refractory material and the lower conduction level.

In another embodiment of the present invention, a sidewall oxide layer is formed on the sidewall of the opening with an inclined profile. The inclined profile extends from the narrow portion of the upper level to the large portion of the lower level, with a larger opening at the upper level.

This provides a further step towards forming a uniform layer of refractory material.

In a more preferred embodiment, the refractory material is tungsten silicide (WSi ₂ ).

DETAILED DESCRIPTION The present invention will be described in detail with reference to the accompanying drawings in order to facilitate a thorough understanding of the invention.

FIG. 1 shows a vertical cross-sectional view of the intermediate level oxide 12 formed on the semiconductor structure 10.

In a preferred implementation, the semiconductor structure 10 is silicon. However, to illustrate the present invention, structure 10 represents a first level conductor, which is described in detail below. Oxide layer 12 is usually referred to as a medium level oxide having a thickness of about 5000-10000 kPa. After the formation of the oxide 12, a contact or via 14 is formed in the oxide layer 12, which will hereinafter be referred to as the via 14.

As can be seen in the figure, the via 14 has two vertical side walls 16 and 18, patterning the surface of the oxide layer 12 by a photoresist (PR) operation, and not covering by anisotropic plasma etching. By etching oxides to form vertical sidewalls 16 and 18. After the via 14 is formed, a uniform layer of insulating material 20 is formed by forming the vertical side walls 16 and 18. After the via 14 is formed, a uniform layer of insulating material 20 is applied to the via 14 and the oxide layer 12 to uniformly coat the bottom surface of the vertical side walls 16 and 18 and the contact / via 19. Deposition on).

The solyon layer 20 is advantageously formed by depositing SiO ₂ or SiO ₃ N ₄ .

It is deposited using a low temperature reaction process using prior art or CVD techniques.

The layer 20 is formed to a thickness of several thousand micrometers, preferably 2000 micrometers.

As described above, the layer 20 adheres to the shape of the vias 14 and is attached to the vertical side walls 16 and 18.

As shown in FIG. 3, the insulating layer 20 has a structure in which the sidewalls 16 and 18 are respectively covered with relatively thick sidewall oxide layers 22 and 24, and is removed by anisotropic etching.

If the thickness of the insulating layer 20 was 2000 kPa, it is about 2000 kPa near the side surface bottom surface 19 of the sidewall oxides 22 and 24 and slightly thinner near the top surface of the oxide layer 2t.

Therefore, sidewall oxide layers 22 and 24 will have a sloped surface rather than a vertical surface.

As will be explained below, this appears as a round arc surface to form a conductive layer in the via 14.

The insulating layer 20 may be anisotropically removed by various techniques.

Preferably, an etching method is used in which the insulating layer 20 is etched only in the vertical direction without significant undercutting or side etching.

Sidewall oxides are widely used in this field for various purposes.

One purpose is to seal sidewalls on various conductive structures, such as the gates of MOS transistors, or to provide spacers from vertical walls in ion implantation techniques. The sidewall oxide formation process is described in detail in US Pat. No. 4,356,040, filed October 26, 1982 by Horng-Sen Fu, et, al., Incorporated herein by reference.

After the formation of the sidewall oxide layers 22 and 24, a thin layer of refractory metal 26 is sputtered onto the substrate at a thickness of about 500 microseconds.

In a preferred specific implementation, the refractory metal used is Ti.

At this time, Ti requires a rapid thermal anneal (RTA) in an N ₂ or NH ₃ atmosphere, which causes a TiSiO ₂ layer 28 near the surface of the silicon substrate 10 proximate to the bottom 19 of the via 14. Resulting in the formation of the TiN layer 30 on the remainder of the via 14, the outer surface of the sidewall layers 22, 24 and the top surface of the oxide layer 12.

When Ti in the Ti layer 26 is reacted in an N ₂ atmosphere to form TiSi ₂ , this process results in two reactions appearing on the silicon.

The first reaction is the formation of TiN that grows down from the gaseous state, and the second reaction is the formation of TiSi _{2 that} grows up from the silicon contact region.

Since these two reactions have different activation energies, the TiN / TiSi ₂ thickness ratio is temperature sensitive.

However, in the TiN layer 30, a predetermined amount of TiN is formed on the silicon, which results in thinner than the remaining TiN layer 30 on the oxide layer.

Both the TiSi ₂ layer 28 and the TiN layer 30 become conductive due to the TiSi ₂ layer 28 proximate to the bottom 19 of the via 14 forming the boundary metal and the portion of the TiN layer 30. .

The formation of layers 28 and 30 is shown in FIG.

It should be noted that if the lower level conductor lies on the bottom 19 of the via 14 and the lower level conductor is not made of silicon or does not contain silicon, then the TiSi ₂ layer 28 is not formed.

The purpose of the TiN layer 30 is to provide a barrier for providing a connection between the layers subsequently formed and the underlying layer, such as silicon.

However, if the underlying layer is a metal such as aluminum, TiN should be sputtered directly on the aluminum surface instead of Ti's RTA process.

For example, if metal is deposited directly on silicon, spikes or tunneling will occur, which is well known in the art.

After the TiN layer 30 is formed on the bottom surface 19 of the via 14, a uniform conductive layer 32 is formed on the TiN layer 30 to a thickness of about 2000 microns.

CVD techniques are used to form uniform layers. In this embodiment, WSi2 is deposited by the CVD method.

Of the various silicides, WSiO ₂ is currently the only one that can be conveniently deposited using CVD to give a uniform layer.

In contrast, sputtering materials such as aluminum to give the conductive layer require a PVD process.

This is an anisotropic process that gives severe step coverage near the vertical surface.

Therefore, it is an important feature of the present invention to use any process to form a highly conductive layer on the sidewalls of the vias 14.

As will be described in detail below, an important part of the conductivity is the portion of the homogeneous layer 32 proximate to the outer surface of the sidewall oxide layers 22 and 24 and the portion separated by the TiN layer 30 therefrom.

This provides a means of evangelism.

The property of the uniform 32 and thus the step coverage is improved by using sidewall oxide layers 22 and 24 which have been worked with inclined spacers.

Although in the preferred embodiment the WSi ₂ is deposited directly by the CVD technique, it should be understood that various techniques can be used to deposit highly conductive layers.

For example, polysilicon may be used, which is suitable for CVD processes but its sheet resistance is so large that it worsens the conductive properties of the conductor.

Another technique that can be used is shown in FIGS. 6A and 6B.

In FIG. 6A, the Ti layer 34 is sputtered onto the substrate at a temperature of about 100 ° C. and about 800 kPa in vacuum.

The process is followed by a doped polysilicon or undoped polysilicon layer 36 deposited with CVD techniques at a thickness of about 1500 microns.

At this time, the substrate undergoes an RTA process at about 950 ° C. for about 30 seconds to form TiSi ₂ .

The TiSi ₂ region is about 2000-3000 mm thick.

Although TiSi ₂ is used in this embodiment, other silicides such as MOSi ₂ or TaSi ₂ may be used.

After the TiSi ₂ formation reaction, the conductive layer 32 will be formed of TiSi ₂ .

Thin films deposited by the PVD method are mainly applied to thick films because of their nonuniform disadvantages.

This condition has been alleviated to some extent by using a thin film (ie Ti) as a PVD process and covering the CVD film (ie polysilicon).

Referring to FIG. 7, after the conductive layer 32 is formed, the metal layer 38 is sputtered on the layer 32.

In a preferred implementation, metal layer 38 is aluminum sputtered to about 5000-8000 mm thick.

It can be seen that the aluminum layer 38 has a relatively constant thickness at the portion placed on the oxide layer 12.

However, the portion lying on the via 14 is variable in thickness. This thickness is due to the anisotropic nature of the sputtering process.

Although there is a continuous coverage in the vias 14, there is a possibility that voids may still appear.

The likelihood of voids is somewhat lost due to the layers 22 and 24, which are inclined surfaces, and the uniform layer 32 is inclined rather than pointed edges or steps.

However, since the bottom 19 of the via 14 is a TiN layer 30 and a uniform WSi2 layer 32, providing a conductive connection, whether or not there are sharp edges or steps appearing in the aluminum layer 38 It doesn't matter.

As described above, in the case of the purpose of connecting the silicon surface and the metal layer 38, or in the case of the underlying conductive layer, the only part of the homogeneous layer 30, 32 that provides a conductive connection is from the top to the bottom. It is a part that extends to the level. This area is therefore necessary to give a reliable connection between the metal layer 38 and the bottom surface 19 of the via 14.

Although the horizontal surfaces of the homogeneous layers 30 and 32 of TiN and WSi2 do not serve to provide a conductive connection between the metal layer 38 and the bottom surface 19 of the vias 14, they are adopted and in some cases It also provides an improved electromigration resistance metal system.

In summary, the present invention provides a process for enhancing the reliability of step coverage and via / contact opening.

The process utilizes sidewall oxide spacers formed on the bottom surface of the via / contact opening and then forming a boundary layer on the bottom surface of the via / contact opening and then formed on the vertical wall of the via / contact opening.

A homogeneous layer of refractory material, such as silicide, is then deposited for the structure to uniformly cover the surface of the via / contact opening that includes the external representation of the sidewall spacers.

The sidewall spacer is provided with an inclined surface extending at an angle to the bottom surface of the via / contact opening.

At this time, the metal layer is sputtered on the uniform layer to provide a conductive connection between the upper level and the lower level to overcome the step coverage problem of the sputtering process.

Although the present invention has been described in detail, various changes, modifications and variations can be made without departing from the spirit of the invention.

Claims (19)

Forming an insulating layer 12 over the conductive silicon region 10; Forming an opening (14) having substantially vertical sidewalls (16) (18) in said insulating layer so that a portion (19) of the conductive silicon region is exposed; Forming a uniform insulating layer 20 over and in the opening; Forming a sidewall spacer regions 22 and 24 along the vertical sidewall opening and etching anisotropically uniformly layered to expose the conductive silicon regions, and anisotropically etching the uniformly insulating layer to expose the sidewall spacer regions, and Sidewall spacer regions are thicker near the conductive silicon region than at the upper surface of the insulating layer; Forming a fire resistant metal layer 26 over the insulating layer, the sidewall spacer region and the exposed conductive silicon region; The old patent bath is heated in a nitrogen atmosphere, where part of the refractory metal layer is converted to refractory metal silicide 28 over the exposed conductive silicon region and the remainder of the refractory metal layer is converted to refractory metal nitride 30. Become; Forming a uniform conductive layer 32 comprising the refractory metal over the refractory metal nitride; And forming aluminum (38) over the uniformly conductive layer. 2. The method of claim 1, wherein after the step of forming the aluminum layer (38), the aluminum layer is patterned for interconnection. 2. The semiconductor as claimed in claim 1, wherein the step of forming the uniform conductive layer (32) further comprises depositing tungsten silicide over the refractory metal nitride (30) using chemical vapor deposition. A contact formation method for an integrated circuit device. The method of claim 1, wherein the forming of the uniform conductive layer comprises: depositing a second refractory metal layer (34) on the refractory metal nitride (30); Depositing a polycrystalline silicon layer 36 over the second refractory metal layer; And heating the structure to convert the polycrystalline silicon and the second refractory metal layer into a refractory metal silicide layer (32). The method according to any one of claims 1 to 4, wherein the refractory metal layer (26) is a titanium layer. 5. The method of claim 4, wherein the second refractory metal layer (34) comprises titanium. The contact forming method of a semiconductor integrated circuit device according to any one of claims 1 to 4, wherein the uniform conductive layer of the refractory metal has a substantially uniform thickness. 5. The method of claim 1, wherein the refractory metal silicide is titanium silicide. 6. 5. The method of claim 1, wherein the refractory metal nitride (30) is titanium. The layer of claim 1, wherein the aluminum layer 38 overlies the uniform conductive layer over the insulating layer, wherein the refractory metal silicide layer 28 and the refractory metal nitride layer ( 30) and a conductive connection from the conductive silicon region (10) to the aluminum layer at all times through the uniform conductive layer. In an integrated circuit, an opening (14) extending through an insulating layer with substantially vertical sidewalls (16) (18) and wherein a portion (19) of the first level conductor is exposed within the opening; Insulating side wall spacer regions (22) and (24) covering the sidewalls of the opening, wherein the sidewall spacer regions are thicker near the first level silicon conductor than the upper surface of the insulating layer; A refractory metal silicide layer 28 covering the exposed portion of the first level silicon conductor; A refractory metal nitride layer 30 covering a part of the upper surface of the refractory metal silicide layer, the sidewall spacer region and the insulating layer; Insulating layer 12 comprising a uniform conductive layer 32 comprising a refractory metal covering the refractory metal nitride 30, the second level metal conductor is composed of aluminum covering the uniform conductive layer 12 Contact structure for connecting the first level silicon conductor (10) and the second level metal conductor (38) separated by. 12. The contact structure of claim 11, wherein the uniform conductive layer comprises a refractory metal silicide. 13. The contact structure of claim 12, wherein the uniform conductive layer (32) has a substantially uniform thickness. The contact structure according to claim 12 or 13, wherein the uniform conductive layer (32) comprises tungsten dissilicide. The contact structure according to claim 12 or 13, wherein the uniform conductive layer (32) comprises titanium silicide. The contact structure according to any one of claims 11 to 13, wherein the refractory metal silicide layer (28) comprises titanium silicide. The contact structure according to any one of claims 11 to 13, wherein the refractory metal nitride layer (30) comprises titanium nitride. 17. The contact structure of claim 16, wherein the refractory metal nitride layer comprises titanium nitride. 12. The refractory metal silicide layer (28) and refractory metal nitride layer (12) are disposed on the uniform conductive layer (32) on the insulating layer (12). 30) and a conductive connection from said first level conductor to said second level conductor through said uniform conductive layer.

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