KR0133273B1 - Semiconductor memory device - Google Patents

Abstract

The dynamic random access memory element has a data line pair DL shared between a plurality of memory cell arrays 21a / 21b, and the column address decoder unit 22d shares one associated bit line pair with one of the column selectors. By combining with a pair of data line pairs, the data line pairs do not increase with memory capacity.

Description

Semiconductor memory device

1 is a block diagram showing an arrangement of a dynamic random access memory device of the prior art.

2 is a circuit diagram showing the arrangement of sense amplifier circuits and column selectors included in prior art dynamic random access memory elements.

3 is a block diagram showing the arrangement of another prior art dynamic random access memory element.

4 is a block diagram showing an arrangement of a dynamic random access memory device according to the present invention.

5 is a logic diagram showing the arrangement of a column address decoder unit included in a dynamic random access memory element according to the present invention.

6 is a block diagram showing an arrangement of a dynamic random access memory device according to the present invention.

7 is a block diagram showing an arrangement of another dynamic random access memory element according to the present invention.

8 is a circuit diagram showing some column selection units included in another dynamic random access memory element.

9 is a block diagram showing an arrangement of another dynamic random access memory element according to the present invention.

＊ Explanation of symbols on main parts of drawing

20: single semiconductor chip 22: addressing system

23: data transfer system 23a, 23b: sense amplification unit

23c: single read circuit 23d: single write circuit

24: control system

The present invention relates to semiconductor memory devices, in particular semiconductor memory devices having pairs of data lines shared between all memory cell arrays.

A typical example dynamic random access memory element is illustrated in FIG. 1 of the drawings and mainly comprises two memory cell arrays 1a and 1b, an addressing system 2, a data transfer system 3 and a control system 4; have.

The memory cell array 1a includes a plurality of memory cells MA11, MA1m, MALn, MA21, MA2m, MA2n, MA3m, MA3n, MA4m, and MA4n. It consists of MA1m, MA1n, MAm1, MAmm and MAmn, and these many memory cells MA11 to MAmn are arranged in a matrix. Similarly, the memory cell array 1b is implemented with a matrix of memory cells MB11 through MBmn. Each memory cell MA11 to MAmn and MB11 and MBmn are implemented with a series combination of n-channel enhanced switching transistor Qn1 and storage capacitor SC1, each memory cell storing data bits in the form of charge.

The addressing system 2 is classified into a row addressing sub-system and a column addressing sub-system. The row addressing sub-system (not shown) comprises a row address buffer unit, a row address decoder / wordline driving unit 2a and a plurality of wordlines WL1, WL2, WL3, WL4, ..., WL1 and WLm These multiple word lines WL1 and WLm are associated with rows of memory cell arrays 1a and 1b respectively. Row addresses are assigned to word lines WL1 through WLm, respectively. The row address buffer unit temporarily stores the row address to generate a row address predecoded signal.

The row address and thus the row address predecoded signal select one of the word lines WL1 through WLm. The row address decoder / word line driving unit 2a receives the row address predecoded signal to drive the selected word line to an active high voltage level. However, other word lines stay at the inactive undervoltage level. The word lines WL1 through WLm are connected to the gate electrode of the n-channel enhanced switching transistor Qn1 of the associated row, respectively. The selected wordline then causes the n-channel enhanced switching transistor Qn1 of the associated row to turn on, and data is written into or read from the storage capacitor SC1.

The column selection sub-system includes two memory cell arrays 1a and 1b and a column address decoder unit 2b and two column selection units 2a and 2b, respectively, associated with each other.

The column selection units 2c and 2d are simultaneously activated by the column address decoder unit 2b and perform a selective operation on the associated memory cell arrays 1a and 1b.

The data transfer system 3 comprises two sets of bit line pairs BA1, BAm and BAn and BB1, BBm and BBn, two sense amplification units 3a and 3b, two pairs of data lines DA1 and DB1, two readout circuits 3c and 3d) and two write circuits 3e and 3f. Each bit line pair BA1 through BAn and BB1 through BBn consists of left and right bit lines BLa and BLb, and the bit line pair BA1 through BAn and BB1 through BBn each represent a row of memory cells of the array 1a and a memory of the array 1b. It is associated with a column of cells. The left and right bit lines BLa and BLb of each bit line pair are selectively connected to the drain node of the n-channel enhanced switching transistor Qn1 in the associated column, and each bit line pair is a row of memory cells selected from the memory cell array 1a or 1b. Transfers the data bits in the form of the potential difference of the column selection unit 2c or 2d associated therewith.

The sense amplification units 3a and 3b are associated with the memory cell arrays 1a and 1b, respectively, and include sense amplification circuits SA1 / SAm / SAn and SB1 / SBm / SBn, respectively. The sense amplifier circuits SA1 to SAn and SB1 to SBn are connected to the bit line pairs BA1 to BAn and BB1 to BBn, and the column selection units 2c and 2d are one of the bit line pairs SA1 to SAn and the bit line pairs SB1 to SBn. One is connected to a pair of data line DA1 and a pair of data line DB1 respectively under the control of the column address decoder unit 2b.

That is, column addresses are each assigned to a column of memory cells in each array. The column address is temporarily stored in the column address buffer unit (not shown), and the column address buffer unit generates a column address predecoded signal from the column address bits. The column address decoder unit 2b receives the column address predecoded signal and supplies two column address decoded signals to the column selection units 2c and 2d, respectively. Each column address decoded signal selects one of the column addresses, and causes the associated column selection units 2c and 2d to select one of the bit line pairs BAS1 to BAn or one of the bit line pairs BB1 to BBn.

As described in detail in FIG. 2, each of the sense amplifying circuits SA1 to SAn and SB1 to SBn is a first series combination of n-channel enhanced switching transistor Qn2 and p-channel enhanced switching transistor Qp3, and n- And a second series combination of the channel enhanced switching transistor Qn4 and the p-channel enhanced switching transistor Qp5, the first and second series combining portions being coupled in parallel between the power supply voltage lines SAN and SAP. Reference sign SA is commonly used for all sense amplifier circuits. The supply voltage line SAP is pulled up to the electrostatic source voltage level and the other supply voltage line SAN is pulled down to the ground voltage level. The common drain nodes N1 and N2 are respectively coupled to the left and right bit lines BLa and BLb, and the common drain nodes N1 and N2 are connected to the gate electrodes of the switching transistors Qn2 and Qp3 and the gate electrodes of the switching transistors Qn4 and Qp5, respectively.

Each column selection unit 2c and 2d is implemented by a plurality of pairs of n-channel enhanced switching transistors Qn6 and Qn7, and only one pair of n-channel enhanced switching transistors Qn6 and Qn7 is shown, and sense amplification circuit SA Related to. The n-channel enhanced switching transistors Qn6 and Qn are coupled between the data lines DA1 or DB1 associated with the left and right bit lines BLa and BLb, respectively. The column address decoded signal is supplied to the gate electrodes of the n-channel enhanced switching transistors Qn6 and Qn7.

As described above, data is transferred in the form of a potential difference between the shape selected memory cells and the column selection units 2c and 2d and amplified by the sense amplifier circuits SA1 to SAn and SB1 to SBn. That is, when the power supply voltage lines SAN and SAP supply the power supply voltage and the ground voltage to each sense amplifier circuit, the voltage levels at the common drain notes N1 and N2 are rapidly amplified by the first and second series combinations. One of the column address decoded signals is supplied to the gate electrodes of the n-channel enhanced switching transistors Qn6 and Qn7, and the n-channel enhanced switching transistors Qn6 and Qn7 are simultaneously turned on and amplified from the common drain nodes N1 and N2. Transfer the potential difference to the associated data line pair DA1 or DB1.

The read circuits 3c and 3d receive the potential difference on the associated data line pair DA1 and DB1 and generate an output data signal in the read operation. On the other hand, the write circuits 3e and 3f generate a potential difference from the input data signal, and supply this potential difference to one of the data line pairs DA1 and DB1 in the write operation.

The control system 4 includes a timing generator (not shown) for generating an internal timing control signal, switching units 4a and 4b, and the like. The switching units 4a and 4b receive the write enable signal WE indicating the write mode, and connect the data line pairs DA1 and DB1 to the write circuits 3h and 3i. Furthermore, the switching units 4a and 4b connect the data line pairs DA1 and DB1 to the read circuits 3f and 3g when the write enable signal WE is disabled. Thus, each data line pair DA1 or DB1 is associated with a set of write and read circuits 3c / 3d or 3e / 3f, and the switching unit 4a or 4b optionally associates the data line pair DA1 or DB1. It is connected to a write and read circuit (3f / 3h or 3g / 3i). The switching units 4a and 4b or the write and read circuits 3c to 3f can be selectively enabled by the accessed memory cell arrays 1a or 1b.

The arrangement of data input / output facilities shown in FIG. 1 is uneconomical because the data line pairs DA1 and DB1 require the same number of switching units 4a and 4b. In order to simplify the circuit arrangement, the switching units 14a and 14b are connected in series as shown in FIG. 3, and the pair of write and read circuits 15a and 15b are shared between all data line pairs DA1 and DB1. do. The prior art dynamic random access memory element shown in FIG. 3 is similar to that shown in FIG. 1 except for the series of shared write and read circuits 15a and 15b and the switching units 14a and 14b, Other elements are denoted by the same reference numerals indicating corresponding elements, and detailed descriptions thereof are omitted.

The switching unit 14a responds, for example, to the block decoded signal BL representing either memory cell array 1a or 1b, and the switching unit 14B responds to the write enable signal WE. The switching units 14a and 14b combine the write or read circuit 15a or 15b with the data line pairs DA1 and DB1 by a combination of the block select signal BL and the write enable signal WE.

As described above, the prior art dynamic random access memory element shown in FIG. 1 requires a plurality of pairs of data lines DA1 and DB1 respectively associated with the memory cell arrays 1a and 1b, and these data line pairs DA1 and DB1 increases as the memory cell arrays 1a and 1b, or the memory capacity becomes larger. The write and read circuits 3c / 3e and 3d / 3f increase to the data line pair DA1 and DB1. As a result, the semiconductor chip expands nonlinearly as the memory capacity becomes larger, and accordingly, the prior art dynamic random access memory device shown in FIG. 1 has a low yield.

On the other hand, the prior art dynamic random access memory element shown in FIG. 3 has a smaller rate of increase than the prior art dynamic random access memory element shown in FIG. 1 because only one pair of write and read circuits has all the data. This is because line pairs are shared between DA1 and DB1. However, memory cell arrays 1a and 1b still require their own data line pair DA1 and DB1, and data line pair DA1 and DB1 increase as memory cell arrays DA1 and DB1 become larger. Moreover, switching units 14a and 14b require more complex control signals.

[Summary of invention]

Thus, an important object of the present invention is to provide a semiconductor memory device having a small amount of chips without complicated control signals.

To this end, the present invention proposes to have a plurality of column selection means for connecting one of the data transfer paths to the data line pair so that the data line pair is shared among the plurality of memory cell arrays.

According to the present invention, a semiconductor memory device includes a) a plurality of memory cells each having a plurality of addressable memory cells each assigned a row address and a column address shared between a plurality of memory cell arrays, the plurality of memory cells assigned each block address An array, b) row addressing means for selecting a row of memory cells from each memory cell array in response to the first address bits, and c) a plurality of sets of data transfer paths, each coupled with a plurality of memory cell arrays, to transfer data bits. d) column address decoder means for selecting one of the data transfer paths included in the plurality of data transfer paths in response to the second address bits, e) in response to the second address bits; Are coupled between multiple sets of data transfer paths and data line pairs, respectively, A plurality of column selection means operable to combine data line pairs in one of said data transfer paths under the control of said means, g) a readout circuit for generating an output data signal from one data bit, and h) one data bit from an input data signal. And a switching means operative to couple the data line pair with one of the read circuit and the write circuit.

The features and advantages of the semiconductor memory device according to the present invention will become apparent from the following description with reference to the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Example 1

In FIG. 4, the dynamic random access memory device embodying the present invention is fabricated on a single semiconductor chip 20, and mainly comprises a plurality of memory cell arrays 21a and 21b, as similar to the dynamic random access memory device of the prior art. An addressing system 22, a data transfer system 23, and a control system 24.

The memory cell array 21a is composed of a plurality of memory cells MA11, MA1m, MA1n, MA21, MA2m, MA2n, MA31, MA3m, MA3n, MA41, MA4m, MA4n, MA11, MA1m, MA1n, MA1n, MAm1, MAmm and MAmn. The plurality of memory cells MA11 to MAmn are arranged in a matrix. Like the memory cell array 21a, the memory cell array 21b is implemented with a matrix of memory cells MB11 through MBmn. Each of memory cells MA11 through MAmn and MBmn is implemented by a series combination of n-channel enhanced switching transistors and storage capacitors, similar to memory cells of the prior art, each memory cell storing data bits in the form of charge. . The block address is assigned to the memory cell arrays 21a and 21b, and one of the memory cell arrays 21a or 21b is selected as the block address bit in every access.

The addressing system 22 is classified into a row addressing sub-system, a column addressing sub-system, and a block selection subsystem. The row addressing sub-system includes a row address buffer unit 22a, a row address decoder / wordline driving unit 22b and a plurality of word lines WL1, WL2, WL3, WL4 .., WL1 and WLm. The plurality of word lines WL1 through WLm are shared between the memory cell arrays 21a and 21b. Row addresses are assigned to word lines WL1 to WLm and memory cell rows, respectively, and row addresses are shared between memory cell arrays 21a and 21b. That is, the memory cells MA11 to MAmn of the row respectively correspond to the memory cells MB11 to MBmn of the row, and each row address identifies one of the memory cells MB11 to MBmn as well as one of the memory cells MA11 to MAmn of the row.

The row address buffer unit 22a temporarily stores the row address bits and is supplied to the row address predecoded row address decoder / wordline driving unit 22b, and the row address decode / wordline driving unit 22b is a row address. One of the word lines WL1 to WLm is selected together with the row address indicated by the bit. When one of the word lines WL1 to WLm is selected, the row address decoder / word line driving unit 22b drives the selected word line to an active high voltage level. However, other word lines remain inactive low voltage level. The word lines WL1 through WLm are coupled with the gate electrodes of the n-channel enhanced switching transistors of the memory cells in their respective associated rows. The selected word line then causes the n-channel enhanced switching transistor of the associated row to turn on and the data bits are written to or read from the storage capacitor.

The column selection sub-system includes a column address buffer unit 22c, a column address decoder unit 22d, and two column selection units 22e and 22f respectively associated with the two memory cell arrays 21a and 21b. Column addresses are assigned to columns of memory cells of each memory cell array 22a and 22b, respectively. The column address buffer unit 22c temporarily stores the column address bits and generates a column address predecoded signal. The column address decoder unit 22d generates a column address decoded signal in response to the column address predecoded signal. The column selection units 22e and 22f include transfer gates TA1 to TAn and transfer gates TB1 to TBn, respectively, and transfer gates TA1 to TAn and TB1 to TBn respectively represent columns of memory cell array 21a and memory cell array 21b. Is provided in relation to the heat. The transfer gates TA1 to TAn and TB1 to TBn are arranged similarly to the prior art, and each transfer gate is implemented by a pair of n-channel enhanced switching transistors.

The block select sub-system includes a block address buffer / decoder unit 22g, and the block address buffer / decoder unit 22g is assigned to either of the memory cell arrays 21a or 21b for generating the block enable signal EBL1. Respond to block address bits indicating the completed block address. The block enable signal EBL1 is supplied to the column address decoder unit 22d, causing the column address decoder unit 22d to generate a single column address decoder signal as understood from the description below.

The column address decoder unit 22d is arranged as shown in FIG. 5, and the column address predecoded signal, the block address decoded signal and the complementary block address decoded signal are respectively PA1 to PAX / CPA1 to CPAx, EBL and It is attached with CEBL. The column address predecoded signals CPA1 through CPAx are complementary to the column address predecoded signals PA1 through PAx. The column address decoder unit 22d is classified into two sections 22h and 22i, and sections 22h and 22i are implemented by AND gate arrays ADA1 to ADAn and AND gate arrays ADB1 to ADBn, respectively. AND gates ADA1 to ADAn and AND gates ADB1 to ADBn are coupled to transmission gates TA1 to RAn and TB1 to TBn through decoded signal lines YA1 to YAn and YB1 to YBn, respectively, and decoded signal lines YA1 to YAn and YB1 to Pass one column address decoded signal of YBn.

The column address predecoded signals PA1 to PAx and CPA1 to CPAx are optionally supplied to the AND gates ADB1 to ADBn as well as the AND gates ADA1 to ADAn, and the column address predecoded signals PA1 to PAx and CPA1 to CPAx are section 22h. Dispensing with is identical to dispensing with section 22i. For example, the column address predecoded signals PA1 through PAx are supplied to the AND gates ADA1 through ADAn, and the corresponding AND gate ADB1 is supplied by the column address predecoded signals PA1 through PAx. Similarly, the column address predecoded signals PA1 through PAx are distributed not only to AND gate ADAn but also to AND gate ADBn. For this reason, a logical one level column address predecoded signal is supplied to both AND gates.

However, the block address decoded signal EBL and the complementary block address decoded signal CEBL are supplied to sections 22h and 22i, respectively, and either of the AND gates ADA1 to ADAn or ADB1 to ADBn is enabled. Thus, one of the two selected AND gates generates a column address decoded signal.

In FIG. 4, the data transfer system 23 comprises two sets of bit line pairs BA1, BAm and BAn and BB1, BBm, and BBn, two sense amplification units 23a and 23b, a pair of data lines DL, a single read circuit 23c and a single write circuit 23d. Each of the bit line pairs BA1 to BAn and BB1 to BBn consists of left and right bit lines BLa and BLb, and the bit line pairs BA1 to BAn and BB1 to BBn each represent a row of memory cells of the array 1a and a memory of the array 1b. It is associated with a column of cells. The left and right bit lines BLa and BLb of each bit line pair are selectively coupled with the drain node of the n-channel enhanced switching transistor Qn1 in the associated column, each bit line pair having an associated column select unit 22e or 22f, and a memory cell array. The data bits are transferred in the form of a potential difference of a row of memory cells selected from 21a or 21b. Thus, the bit line pairs BA1 through BAn and BB1 through BBn serve as multiple sets of data transfer paths.

The sense amplification units 23a and 23b are respectively associated with the memory cell arrays 21a and 21b and include sense amplification circuits SA1 / SAm / SAn and SB1 / SBm / SBn, respectively. The sense amplifier circuits SA1 to SAn and SB1 to SBn are combined with BA1 to BAn and BB1 to BBn on the bit lines, and the column selection units 2c and 2d are connected to the bit line pairs SA1 to SAn under the control of the column address decoder unit 22d. And SB1 to SBn are combined with a pair of data lines DL.

The read circuit 23c generates an output data signal in response to the potential difference generated on the data line pair DL. On the other hand, the write circuit 23d generates a potential difference from the input data signal, and supplies the potential difference to the data line pairs to the DL.

The control system 24 includes a controller 24a and a switching unit 24b that respond to external control signals. The controller 24a not only sequentially generates a timing control signal (not shown) but also shifts the dynamic random access memory element between the write mode, the read mode and the refreshing mode. One of the external control signals WE indicates an operation mode, and the controller 24a generates an IWE from the external control signal WE, which generates a mode control signal indicating either the write or read mode.

The switching unit 24b selectively couples the read circuit 23c and the write circuit 23d and the data line pair DL by the logic level of the mode control signal IWE in response to the mode control signal IWE.

Read sequences and write sequences are briefly described below. When the block and matrix address bits select memory cell MA11, the precharging circuitry (not shown) first selects all bit line pairs BA1 through BAn and BB1 through at the intermediate voltage level between the electrostatic source voltage level and the ground voltage level. Equalizes the left and right bit lines BLa and BLb of BBn. When the mode control signal IWE commands the operation random access memory element in a read operation, the row address decoder / word line driving unit 22b drives the word line WL1 above the electrostatic source voltage level, and the right bit line BLa is a memory cell. And storage capacitors of MA11 through MA1n and MB11 through MB1n. The voltage level on the right bit line BLa proceeds slightly up and down depending on the data bits stored, and small potential differences occur on the bit line pairs BA1 to BAn and BB1 to BBn, respectively. The bit line pairs BA1 to BAn and BB1 to BBn transfer small potential differences to the sense amplifier circuits SA1 to SAn and SB1 to SBn, and the small potential differences are generated by the sense amplifier circuits SA1 to SAn and SB1 to SBn.

The block address buffer / decoder unit 22g shifts the block address decoded signal EBL to the constant high voltage level corresponding to the logic one level, and the section 22h is enabled. The column address buffer unit 22c shifts the column address predecoded signals PA1 to PAx to a logic one level, and only the AND gate ADA1 shifts the decoded signal line YA1 to a logic one level or a constant high voltage level.

With the column address decoded signal on the decoded signal line YA1, the transfer gate TA1 turns on and conveys the potential difference to the data line pair DL. The mode control signal IWE causes the switching unit 24b to couple the read circuit 23c with the data line pair DL. Thus, the potential difference on the data line pair DL reaches the read circuit 23c, and the read circuit 23c generates an output data signal from the potential difference.

On the other hand, when the mode control signal IWE appears in the write operation, the write circuit 23d generates a potential difference from the input data signal, and the switching unit 24b couples the data line pair DL and the write circuit 23d. Thus, the potential difference is transferred to the data line pair DL, and the transfer gate TA1 in turn transfers the potential difference to the bit line pair BA1.

The row address decoder / word line driving unit 22b drives the word line WL1 above the constant high voltage level. The potential difference on the data line pair DL is transferred to the bit line pair BA1 through the transfer gate TA1, and a data bit indicated by the potential difference is generated and stored in the memory cell MA11. Different potential differences in different bit line pairs are stored back in different memory cells.

As described above, the random access memory element according to the present invention has only one data line pair DL, and the data line pair DL is shared between all the memory cell arrays 21a and 21b. Although the number of memory cell arrays is increased, only one data line pair selectively transfers data bits for any one of the memory cell arrays, and the rate of increase is less than that of prior art dynamic random access memory elements. Moreover, only the switching unit 24b couples one of the read and write circuits 23c and 23d with the data line pair DL, and the selection between the read circuit 23c and the write circuit 23d is simple. Therefore, the dynamic random access memory element according to the present invention is manufactured on a small semiconductor chip without sacrificing simple control of the switching unit 24b.

Example 2

In FIG. 6, another dynamic random access memory element embodying the present invention is provided with a shared sense amplifier circuit. The sense amplification circuits SA1 to SAn and the sense amplification circuits SB1 to SBn are selectively located on two sides of the memory cell arrays 21a and 21b, the column selection unit is divided into two sections, and the transfer gates TA1 to TAn and TB1 to TBn Is also located on two sides of the memory cell arrays 21a and 21b.

Therefore, the data line pair DL, the column address decoder unit 22d, the switching unit 24b, the read circuit 23c and the write circuit 23d are doubled. However, the redundant data line pair DL is still shared between the memory cell arrays 21a and 21b, and the column address decoder unit 22d is a data line in which one transfer gate TA1 to TAn and TB1 to TBn have a potential difference doubled. Pass on pair DL.

The other components are similar to those of the first embodiment, and the read and write sequences are similar to those of the first embodiment. For this reason, it is no longer described below to avoid undesirable repetition.

The dynamic random access memory element shown in FIG. 6 similarly achieves the same advantages as the first embodiment.

Example 3

In FIG. 7, another dynamic random access memory element embodying the present invention is provided with a read data line pair DLr and a write data line pair DLw. The read data line pair DLr and the write data line pair DLw are exclusively used by the read circuit 23c and the write circuit 23d, and no switching unit is included therein. The mode control signal IWE is supplied directly to the column selection units 22e and 22f, and the column selection units 22e and 22f selectively combine the bit line pairs selected by the read and write data line pairs DLr and DLw. However, the other components are similar to those of the first embodiment, and the description is omitted for the sake of simplicity.

8 illustrates the transfer unit TG by the column selection units 22e and 22f associated with one sense amplifier circuit SA. The transfer unit TG comprises two series combinations of n-channel enhanced switching transistors Qn31 / Qn32 and Qn33 / Qn34 coupled between the associated bit line pairs B1a and BLb and the write data line pair DLw, and the constant power voltage line Vdd and read data. Two series combinations of n-channel enhanced switching transistors Qn35 / Qn36 and Qn37 / Qn38 coupled between the line pair DLr. The mode control signal IWE is applied to the gate electrodes of the switching transistors Qn31 and Qn33, and the bit lines BLa and BLb are coupled with the gate electrodes of the n-channel enhanced switching transistors Qn37 and Qn35, respectively.

In the write mode, the mode control signal IWE advances upward to the constant high voltage level, and the potential difference on the write data line pair DLw is transferred to the bit lines BLa and BLb.

In the read mode, the mode control signal IWE remains within the ground voltage level, and the potential difference on the bit lines BLa and BLb causes the n-channel enhanced switching transistors Qn35 and Qn37 to turn on and off complementarily. At that time, the constant power supply voltage level is supplied to one read data line, and the other read data line is grounded. Thus, the potential difference is transferred to the read data line pair DLr.

The read and write sequence is similar to that of the first embodiment, and the third embodiment also has the same advantage, since the read data line pair DLr and the write data line pair DLw do not increase with the memory capacity.

In this regard, one data line pair is incremented instead of the switching unit. However, the data line pair occupies a smaller area than the switching unit, and the semiconductor chip size is reduced.

Example 4

In FIG. 9, another dynamic random access memory element embodying the present invention is described. The dynamic random access memory element shown in FIG. 9 is similar to the first embodiment except for the row address decoder / word line driving units 31a and 31b exclusively used for the memory cell arrays 21a and 21b. With two row address decoder / word line driving units 31a and 31b, two different rows are addressable, and the combination portion of the second embodiment is doubled from two memory cells with two data bits having different row addresses. Read data line pair DL.

While specific embodiments of the invention have been described, various modifications may be made to those skilled in the art without departing from the spirit and scope of the invention. For example, two or more memory cell arrays 21a and 21b may be included in the dynamic random access memory device according to the present invention, and the present invention can be applied to any type of semiconductor memory device. Dynamic random access memory elements can be included in large scale integrated units along with other functional blocks.

Claims (9)

A semiconductor memory device comprising: a) a plurality of arrays of memory cells, each block address assigned, each array having a plurality of addressable memory cells assigned a row address and a column address, respectively; A plurality of cell arrays, shared among a plurality of memory cell addresses; b) row addressing means for selecting a row of memory cells from each memory cell array in response to a first address bit; c) a plurality of sets of data transfer paths, each coupled with said plurality of memory cell arrays, to carry data bits; d) pairs of data lines shared between said plurality of memory cell arrays; e) column address decoder means for selecting one of the data transfer paths included in the plurality of data transfer paths in response to a second address bit; f) a plurality of column selection means respectively coupled between the plurality of sets of data transfer paths and data line pairs to combine one of the data transfer paths with the data line pairs under the control of the address decoder means; g) read circuitry for generating an output data signal from one of said data bits; h) a write circuit for generating one of said data bits from an input data signal; i) switching means operative to couple a data line pair with one of a read circuit and a write circuit; Semiconductor memory device comprising a. 2. The semiconductor memory device according to claim 1, wherein said row addressing means is executed by a single row address decoder means shared between said plurality of memory cell arrays. 3. The semiconductor memory device according to claim 2, wherein said data transfer paths are each executed by a plurality of pairs of bit lines to transfer potential differences to said plurality of column selection means. 4. The semiconductor memory of claim 3 further comprising a plurality of sense amplifier units each having a plurality of sets of sense amplifier circuits associated with the plurality of memory cell arrays and coupled to the plurality of bit line pairs, respectively. device. 5. A semiconductor memory device according to claim 4, wherein all sense amplifier circuits of each sense amplifier unit are located on a predetermined side of an associated memory cell array. 5. The sensing circuit of claim 4, wherein sense amplifier circuits of each sense amplifier unit are selectively located on both sides of an associated memory cell array, and wherein each of the plurality of column selection means is selectively located on both sides of the associated memory cell array. And a data line pair divided into two data line portions respectively coupled with the two selector portions. 2. The semiconductor memory device of claim 1, wherein the data line pair is used for both read and write operations. The data line pair of claim 1, wherein the data line pair has an exclusive read line used in a read operation and an exclusively used write line in a write operation, wherein the switching means are incorporated in each of the plurality of column selection means. A semiconductor memory device, characterized in that. 2. The semiconductor memory device according to claim 1, wherein said row addressing means comprises a plurality of column address decoder means respectively associated with said plurality of memory cell arrays.