KR0128896B1 - Apparatus of remote transeiver with cascade connection - Google Patents

Abstract

A remote transmission apparatus connected by a cascade is disclosed. The remote transmission apparatus connected by the cascade comprises: connecting a plurality of remote devices(200a - 200f) connected with a cascade to a controller(100) and transmitting serial data from the controller(100) to the remote devices(200a - 200f); detecting a start bit from the controller(100) and receiving the serial data from the controller(100); and transmitting a response signal to the controller(100) when the reception of the corresponding serial data is completed. Thereby, the remote transmission apparatus connected by a cascade may improve the reliability of transmission protocol by transmitting data irrespective of external noise.

Description

Cascaded Remote Transceiver

1 is a connection diagram between a conventional remote device and a control device.

FIG. 2 is a block diagram showing the configuration of the asynchronous communication junction shown in FIG.

3 is a schematic connection diagram between a control device and a remote device according to the present invention.

4 is a block diagram of a control device of FIG.

5 is a block diagram of the configuration of the remote device in FIG.

6 is a detailed block diagram of the reception data detector of FIG.

FIG. 7 is a detailed block diagram of the response information transmitter of FIG.

8 is a timing diagram of data transmission and reception of a remote transceiver according to the present invention.

* Explanation of symbols for main parts of the drawings

100: controller 110: CPU

120: parallel / serial converter 130: serial / parallel converter

140: transceiver 200a to 200b: remote device

210: first transceiver 220: reception data detector

221: data latch portion 222, 223, 224: frequency division circuit portion

230: serial / parallel converter 240: data transmitter

250: response information transmitter 251: first flip-flop

252: second flip-flop 253: third flip-flop

254: first buffer 255, 256, 260: response information receiving unit

270: second transceiver

The present invention relates to a remote transceiver for transmitting and receiving data to and from an exchange system. In particular, the present invention relates to a data transmission / reception protocol by preventing errors in serial data reception and transmission of response completion data in a cascaded remote transceiver. The present invention relates to a cascaded remote transceiver connected with improved reliability. Conventionally, as can be seen in the attached Figure 1, the control device 10 and the remote device 20 is a predetermined number of asynchronous communication matching unit (11, 21) for accurately exchanging asynchronous communication data transmitted and received irregularly It is provided with the above and is connected one-to-one through the RC-232C cable to transmit and receive data, the asynchronous communication matching unit (11, 21), as can be seen in Figure 2 of the accompanying drawings, RC-232C interface chip ( CPU (B) which writes and reads data transmitted and received by applying enable signal for operation preparation to A) and is transmitted / received to RC-232C interface chip (A) according to control signal of CPU (B). It consists of an address decoder C for applying a chip select signal for processing data. At this time, a clock of 9600bps is applied to the RC-232C interface chip A from a clock divider not shown.

The conventional remote transceiver configured as described above has an address decoder (C) according to a control signal of the CPU (B) in a state where a clock of 9600bps is applied to the RC-232C interface chip (A) from a clock division circuit unit (not shown). When the chip select signal CS is detected by the RC-232C interface chip A, the RC-232C interface chip A enters an operation standby state.

First, in order to transmit predetermined data from the control device 10 to the remote control device 20 side, the CPU B in the asynchronous communication matching section 11 of the control device 10 has a 9600 bps clock from the clock divider circuit part (not shown). The enable signal E and the write signal are applied to the applied RC-232C interface chip A, and the chip select signal CS is applied through the address decoder C to provide the RC-232C interface chip ( When the 8-bit parallel data is recorded after selecting the communication port of A), the corresponding asynchronous communication matching unit 21 of the remote device 20 via the RC-232C cable is connected to the serial data according to the clock of 9600 bps applied from the clock division circuit unit. To send).

In addition, the RC-232C interface chip A in the remote device 20 converts the serial data received from the control device 10 into parallel data D0 to D7 according to a clock signal of 9600bps applied from the clock division circuit unit. Similar to the transmission operation of the control device 10, the CPU B in the asynchronous communication matching section 21 of the remote device 20 selects a chip from the enable signal E, the read signal read and the address decoder C. The data received from the control device 10 by the signal CS is read. Therefore, the remote device 20 performs the operation requested by the control device 10 according to the received data under the control of the CPU B, and transmits necessary information corresponding thereto to the control device 10 side.

As described above, the conventional remote transceiver requires a plurality of RC-232C interface chips to transmit and receive data, and since the number of communication ports provided with the control device is limited, it is impossible to transmit or receive data for a predetermined number of remote devices. There is a problem, and the RC-232C interface chip has a limitation in communication distance (15m), and when the control device and the remote device transmit and receive data unilaterally, only data is transmitted. There is a problem that frequently. The present invention has been made in view of the above-described problems, and an object thereof is to allow a control device to communicate with a plurality of remote devices through a single communication port, and to transmit or receive serial data to control a remotely installed device. When sending data to multiple devices, or when the control device sends data, the data is sent with the first bit as the start bit, and the remote transmitting / receiving device can receive the data only after detecting the start bit. Upon completion, the response information is transmitted to the control device, thereby eliminating reception of the data, thereby improving the reliability of the data transmission / reception protocol.

A feature of the present invention for achieving the above object is, in the remote transceiver for transmitting and receiving serial data, by connecting a plurality of remote devices (200a to 200f) connected by the cascade to the control device 100, the control device The remote device 200a to 200f detects the start bit from the control device 100 and receives the serial data from the control device 100. When the reception is completed, the control device 100 transmits a response signal. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a schematic connection diagram of a control device and a remote device according to the present invention. As can be seen from the figure, a plurality of remote devices 200a to 200f having the same hardware structure and a control device 100 for applying data transmission and control signals to the remote devices 200a to 200f are provided. Connected to the cascade, the signal line (h, i, j, k, of the cascade connecting the control device 100 and the remote device 200a to 200f or the remote device 200a and the remote device 200f, l, m is composed of one signal line (1 line). On the other hand, the plurality of remote devices (200a to 200f) connected to the caste and the control device for data transmission and reception, as can be seen in Figure 4, the accompanying drawings, control the data transmission and reception operations and a plurality of remote devices CPU 110 for inputting / outputting data transmitted / received to / from 200a to 200f, parallel / serial converter 120 for converting parallel data output from the CPU 110 into serial data, and cascaded data. Transceiver 140 for transmitting a plurality of remote devices 200a to 200f connected by ID, and serial / parallel converter 130 for converting serial data TXD received from remote devices 200a to 200f into parallel data. It consists of.

Each of the remote devices 200a to 200f includes a first transceiver 210 and a first transceiver 210 for receiving data applied to the control device 100 as shown in FIG. 5. Receive data detector 220 for detecting data RXD received through the serial, parallel / parallel converter 230 for converting the received serial data into parallel data, and the first transceiver 210 from the control device 100 The data transmission unit 240 for transmitting the data received through the cascade and then transmitted via the second transceiver 270 to the remote device, and the data received from the next remote device 200 via the second transceiver 270 The response information receiver 260 detects response information about the reception completion, and the response information transmitter 250 transmits the received response information to the control device 100 through the first transceiver 210.

In addition, the reception data detection unit 220 of the remote apparatuses 200a to 200f, as shown in FIG. 6 of the accompanying drawings, receives data received according to a clock of 9600bps for data reception a predetermined number of times, for example. A data latch unit 221 latched four times, a detection unit 223 for detecting data along a predetermined clock for receiving data, for example, a clock of 1200 bps, if the latched reception data is normal start bit data; A divider circuit portion 224 divides the clock and supplies a 9600bps clock to the data latch portion 221 side.

On the other hand, the response information transmitter 250 of the remote apparatuses 200a to 200f transmits the response signal of the low state applied from the response information receiver 260 as shown in FIG. 7 to the attached clock signal TXCLK. To receive the first flip-flop 251 and the output signal Q of the first flip-flop 251 as a data signal according to the transmission clock signal TXCLK. Sending the response information receiving data to the second flip-flop 252, the third flip-flop 253 received as its own data and delayed for a predetermined time according to the transmission clock signal TXCLK, and outputted. The first buffer 254 outputs the response information of the second flip-flop 252 in response to the gate signal, and the response information of the third flip-flop 253 according to the gate signal inverted through the inverter 256. It consists of a second buffer 255 to transmit to the remote device.

The operation of the present invention having the function as described above will be described with reference to FIG.

As can be seen in FIG. 3, when the control device 100 transmits data to the cascaded remote devices 200a to 200f, the CPU 110 of the control device 100 can be seen as in FIG. When the parallel data of one byte to be transmitted is converted into serial data through the parallel / serial converter 120 and the data signal TXD is transmitted to the remote device 200a through the transceiver 140, FIG. As can be seen from the received data detector 220 of the remote device 200a detects the data signal (RXD) received through the first transceiver 210, the received data detector 220 is 6 and 8 As can be seen from the waveform diagram of FIG. 1, the first transceiver 210 is removed from the control device 100 in a state where a clock a of 9600 bps is generated from the frequency divider circuit 224 and continuously applied to the data latch unit 221. The first bit among the data RXD received through In the low state as shown in (b), the data latch unit 221 checks the received data four times with a clock of 9600bps as shown in (c) of FIG. 8 to confirm whether the input 1200bps data bit is the start bit. Latch. If the data latched four times through the data latch unit 221 is in a low state, it is confirmed that the received data is a normal start bit instead of error data, and the reception data clock generator 222 of FIG. As shown in FIG. 1, a 1200bps clock signal for data detection is generated and applied to the data detection unit 223, and applied to the data detection unit 223. The data detection unit 223 is applied to a 1200bps signal applied from the reception data clock generation unit 222. In accordance with the clock signal, the serial data received from the control device 100 is detected through the first transceiver 210 of FIG. 5 (FIG. 8 (W)).

In addition, the remote device 200a having received the serial data from the control device 100 is controlled by the operation as described above through the first transceiver 270 of FIG. 5 to the next remote device 200b connected by cascade. Serial data from the control device 100 is transmitted to the final remote device 200f in the manner described above via the second transceiver 270 of the device 100.

When the data reception is completed, the remote devices 200a to 200f include 1 byte of data, such as data received from the control device 100, after 1 clock of 1200bps is received as shown in (8) of FIG. . The first bit is the start bit and the last bit is the end bit. A response information transmitter 250 for transmitting the response information data for the data reception completion of the remote apparatuses 200a to 200f to the control apparatus 100 is shown in FIG. 7 of the accompanying drawings. Each remote device 200a to 200f that has completed data reception from the control device 100 has a low start bit and a low state after one clock of the data reception completion point, as shown in (G) of FIG. Send a response bit. When the remote device 200f transmits a start bit and a response bit to the remote device 200e, since there is no remote device connected to the cascade below the remote device 200f, data in a high state is transmitted, and the remote device 200e is transmitted. Only the start bit and its response bit are placed in D5 as in (8). Therefore, each remote device 200a to 200f transmits a response bit transmitted from its rear end remote device connected by the cascade to the start bit and the response bit, and to its front end remote device connected by the cascade.

For example, referring to the remote device 200f in FIG. 3, the first flip is opened because the gate of the first buffer 254 shown in FIG. 7 is opened by a predetermined control signal as shown in FIG. 8. The start and response bits in the low state through the flop 251 and the second flip-flop 252 are transmitted to the remote device 200e at the front end through the first buffer 254 with the gate open. The predetermined control signal such as) is inverted by the inverter 256 and then opens the gate of the second buffer 255 so that the next control device (i.e., a high state because there is no remote device in FIG. The reception data RXD 'is transmitted to its front end remote device 200e through the opened second buffer 255. In this manner, when the information on the completion of data reception is transmitted to the control device 100, the control device 100 transmits the data RXD received through the transceiver 140 as parallel data through the serial / parallel converter 130. Since it is converted and applied to the CPU 110, the CPU 110 checks whether or not data is received from the remote devices 200a to 200f.

As described above, in the present invention, since the control device and a plurality of remote devices are connected by a cascade to transmit and receive data, the control device can transmit and receive data with a plurality of remote devices through a single communication port, and is a device installed remotely. When sending serial data to control the data, sending the same data to multiple devices, or controlling the functioning of the remote device from the control device, the remote device senses the start bit to correctly receive the data sent by the control device. After the data is detected and the reception is completed, reception completion information is provided so that data can be transmitted and received regardless of external noise such as time delay and clock anxiety, thereby improving the reliability of the transmission / reception protocol.

Claims (5)

In the remote transceiver for transmitting / receiving serial data, a plurality of remote devices 200a to 200f connected by cascade are connected to the control device 100 so that the serial data output from the control device 100 can be transmitted to the remote device ( 200a to 200f), the remote device 200a to 200f detects the start bit from the control device 100, receives serial data from the control device 100, and transmits the corresponding serial data. When the reception is complete, the remote transceiver connected to the cascade, characterized in that for transmitting a response signal to the control device (100) side. The apparatus of claim 1, wherein the control device 100 controls a data transmission / reception operation and converts the CPU 110 into input / output data and converts parallel transmission data applied from the CPU 110 into serial data. The converter 120, a serial / parallel converter 130 for converting the received serial data into parallel data and applying the same to the CPU 110, and serial data from the parallel / serial converter 120 to the remote device. Transceiver 140 that transmits to the remote device 200a side adjacently connected to itself from 200a to 200f and applies the received serial data from the remote device 200a to the serial / parallel converter 130 side. Remote transceiver connected to the cascade, characterized in that it comprises a. The apparatus of claim 1, wherein the remote apparatuses 200a to 200f detect a first transceiver 210 for inputting and outputting serial data through a first terminal, and receiving serial data applied through the first transceiver 210. A reception data detector 220, a serial / parallel converter 230 for converting the reception serial data detected by the reception data detector 220 into parallel data, and a reception serial data detected by the reception data detector 220; The data transmission unit 240 to transmit and receive the serial data received from the data transmission unit 240, the second transceiver 270 for transmitting and receiving the serial data from the second terminal through the second transceiver to receive the data The response terminal 260 for receiving a response signal indicating completion of reception, and the response signal applied from the response information receiver 260 via the first transceiver 210 to the first terminal side. Cascading a remote communication apparatus connected Jethro comprising the response information transmitter 250 for transmission. 4. The clock of the frequency divider circuit 224 according to claim 3, wherein the reception data detector 220 controls the frequency divider circuit 224 to generate a predetermined clock and the reception serial data input through the first transceiver 210. A data latch unit 221 for determining whether error data is input by latching a predetermined number of times according to a signal, and a reception for generating a predetermined clock signal for data detection when the data latched in the data latch unit 221 is normal. A data clock generator 222 and a data detector 223 for detecting received serial data latched by the data latch 221 according to a clock of the received data clock generator 222; Cascaded remote transceiver. 4. The first flip-flop 251 according to claim 3, wherein the response information transmitter 250 delays a response signal applied from the response information receiver 260 by a predetermined time according to the transmission clock signal TXCLK. A second flip-flop 252 for receiving the output signal of the first flip-flop 251 as a data signal and delaying the output signal for a predetermined time according to the transmission clock signal TXCLK, and the second transceiver 270 from the second terminal. And a third flip-flop 253 that receives the received data RXD applied through the response information receiver 260 as data and delays the predetermined time according to the transmission clock signal TXCLK and outputs the delayed signal. Accordingly, the signal of the second flip-flop 252 is inverted through the first buffer 254 and the inverter 256 through the first transceiver 210 as a response signal and applied to the gate. According to the signal, the signal of the third flip-flop 253 to the first transceiver 210 And a second buffer (255) for outputting a response signal to the first terminal through the cascade.