KR0123686Y1 - A bipolar transistor - Google Patents

Abstract

The present invention provides a semiconductor substrate of a first conductivity type, a first buried layer of a second conductivity type formed in a predetermined portion on the semiconductor substrate, and a first channel stop layer formed on a side surface of the first buried layer on the semiconductor substrate. By chemical vapor deposition on the first isolation layer and the first isolation layer formed by thermal oxidation without using a mask on the entire surface of the semiconductor substrate including the conductive buried layer and the first and second buried layers. A second isolation layer made of a deposited silicon oxide film includes a device isolation layer formed by patterning the first buried layer to expose the first buried layer, and a device formation layer selectively epitaxially grown on the exposed first buried layer. Therefore, instead of using an ion layer of the same conductivity type as the substrate as the device isolation layer, an oxide film is used to reduce the size of the chip by reducing the design rule.Isolation is achieved by selectively growing the epi layer inside the trench by forming a trench. By minimizing the width of the layer, it is possible to design a minimized transistor, which improves the operating characteristics of the device. In particular, in the case of TTL, the size of the transistor is minimized to significantly improve the speed characteristics, while the oxide film as a device isolation layer is used as a locus. Since it is not formed using a process, it is possible to prevent the size reduction of the device formation region by Buzzvik, thereby reducing the size of the transistor, and because the surface is flattened because Buzzvik is not formed, Resolve the coverage problem.

Description

Bipolar transistor

1 is a view for explaining each step of the method for forming the structure of a conventional bipolar transistor.

2 is a view for explaining each step of the method for forming the structure of the bipolar transistor of the present invention.

* Explanation of symbols for main parts of the drawings

10,30 semiconductor substrate 11,31 first mask layer

12,32 first buried layer 13 epi layer

14,33: second mask layer 15,39: element formation layer

16 device isolation ion layer 17,40 base region

18,41 emitter area 19,42 collector area

20,43: top insulating layer 21,44: metal wiring layer

34: second buried layer 35: first insulating layer

36: second insulating layer 37: first insulating layer

38: second isolation layer

The present invention relates to a bipolar transistor, and more particularly, to a bipolar transistor that is suitable for minimizing chip size.

The structure of a conventional bipolar transistor is formed on the semiconductor substrate 10 at a predetermined depth with a predetermined distance, as shown in FIG. 1G, and includes a device isolation ion layer 16 containing high concentration impurities of the same conductivity type as the substrate. A buried layer 12 of the opposite conductivity type to the substrate formed between the device isolation ion layers to a predetermined thickness deeper than the depth of the device isolation ion layer, and an epitaxial layer of the opposite conductivity to the substrate formed on the buried layer. an element formation layer 15 formed of a layer, a base region 17 formed at a predetermined depth and a predetermined width inside the element formation layer, an emitter region 18 formed at a predetermined depth inside the base region, and an epi layer. A collector region 19 formed at a predetermined depth and a predetermined width at a predetermined distance from the base region, and located above the element isolation region, element formation layer, base region, collector region, and emitter region described above. A device upper insulating layer 20 in which contact holes are formed so that the switch region, the emitter region and the collector region can be connected to the outside, and the metal wiring layer 21 formed from the upper surface of each region to the upper portion of the insulating layer through the contact holes. It consisted of

The method of manufacturing the bipolar transistor of this structure is the same as that of the first diagram.

First, as shown in FIG. 1A, an insulating film is formed on a semiconductor substrate (p-sub) 10 and patterned to expose a predetermined portion by a photolithography method to form a first mask layer 11. In addition, after depositing Sb ₂ O ₃ on the exposed portion of the semiconductor substrate 10 where the first mask layer 11 is not formed, the buried layer (NBL: n buried) having a conductivity type opposite to that of the substrate is diffused. layer 12 is formed.

Next, as shown in FIG. 1B, the first mask layer 11 is removed. The epi layer 13 is formed on the upper surface of the semiconductor substrate 10 on which the buried layer 12 is formed. In the process of forming the epitaxial layer 13, impurities doped in the buried layer 12 are also diffused into the epitaxial layer 13.

Next, as shown in FIG. 1C, an insulating film is formed on the semiconductor substrate 10 and patterned to form the second mask layer 14.

Next, as shown in FIG. 1D, the device isolation layer 16 is formed by implanting ions of opposite conductivity type (n-type) from the substrate 10 using the second mask layer 14 as a mask. . At this time, the device isolation layer 16 is formed in contact with the buried layer 12 to be electrically connected. By forming the device isolation layer 16, an element formation region is defined in the epi layer 13. 15) is formed. Then, the second mask layer 14 remaining on the semiconductor substrate 10 is removed.

Next, as shown in FIG. 1E, the base region 17 is formed by performing base ion implantation on a predetermined portion of the element formation layer 15.

Next, as shown in FIG. 1 (f), emitter and collector ions are implanted to form the emitter region 18 in the base region 17 and the collector region 19 in the element formation layer 15.

Next, as shown in FIG. 1G, the device isolation layer 16, the device formation layer 15 defined by the device isolation layer 16, the base region 17 formed in the device formation layer 15, and A device upper insulating layer 20 is formed on the entire surface of the semiconductor substrate 10 on which the collector region 19 and the emitter region 18 formed in the base region 17 are formed. The device upper insulating layer 20 is patterned to form a contact hole so that the base region 17, the emitter region 18, and the collector region 19 can be connected to the outside, and the metal is filled in the contact hole. The wiring layer 21 is formed through a step.

In the conventional bipolar transistor having such a structure, the isolation area is increased during implantation after ion implantation by implanting the opposite conductivity type ion into the substrate for device isolation, thereby increasing the chip size due to the design rule between the base and the isolation region. Had

The present invention provides a bipolar transistor capable of minimizing an area for isolation through selective epitaxial growth and forming an element in contact with an isolation region by isolation of an element by an oxide film, thereby reducing an increase in chip size.

In a bipolar transistor in which a collector, a base, and an emitter region are formed in an element formation layer of a semiconductor substrate according to the present invention for achieving the above object, a semiconductor substrate of a first conductivity type and a predetermined portion on the semiconductor substrate are formed. A semiconductor substrate comprising a first buried layer of a second conductivity type, a second buried layer of a first conductivity type used as a channel stop layer formed on a side surface of the first buried layer on the semiconductor substrate, and the first and second buried layers. A second isolation layer formed of a first isolation layer formed by thermal oxidation without using a mask on the entire surface and a silicon oxide film deposited by chemical vapor deposition on the first isolation layer is patterned to expose the first buried layer. A device isolation layer and a device formation layer selectively epitaxially grown on the exposed first buried layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The bipolar transistor of the present invention, as shown in (i) of FIG. 2, has a first buried layer 32 of a conductivity type opposite to the substrate 10 formed inside the semiconductor substrate 30 and a side surface of the first buried layer 32. The second buried layer 34 of the same conductivity type as the substrate 10 formed of the channel stop layer and the first isolation layer 37 and the second isolation layer 38 formed on the second buried layer 34 are formed. And a device isolation layer 39 formed of an epitaxial layer in the device region defined by the device isolation layer. In this case, the first isolation layer 37 of the device isolation layer is formed of a silicon oxide film, and the second isolation layer 38 is formed of a silicon oxide film deposited by chemical vapor deposition (hereinafter, referred to as CVD). Let's do it.

The bipolar transistor of the present invention is formed by the following manufacturing method.

First, as shown in FIG. 2A, an insulating film is formed on a semiconductor substrate (p-sub) 30, and the insulating film is patterned by a photolithography method to form a first mask layer 31. In addition, after depositing Sb ₂ O ₃ on the exposed portion of the semiconductor substrate 30 where the first mask layer 31 is not formed, a buried layer (NBL: n buried) having a conductivity type opposite to that of the substrate is diffused. layer 32 is formed.

Next, as shown in FIG. 2B, the first mask layer 31 is removed. Then, an insulating film is formed on the semiconductor substrate 30 and patterned to form the second mask layer 33, and then, as a mask, ion implantation of impurities of the same conductivity type into the semiconductor substrate 10 is performed to stop the channel. A second buried layer 34 used as a layer is formed.

Next, as shown in FIG. 2C, the second mask layer 33 is removed. The first insulating layer 35 covering the first buried layer 32 and the second buried layer 34 by thermally oxidizing the upper portion of the semiconductor substrate 30 while activating the first buried layer 32 and the second buried layer 34. ).

Next, as shown in FIG. 2D, a silicon oxide film is deposited on the first insulating layer 35 by CVD to form a second insulating layer 36.

Next, as shown in FIG. 2E, the second and first insulating layers formed on the semiconductor substrate 30 are anisotropically etched by defining element formation regions. At this time, etching is performed until the first buried layer 35 is exposed. Thus, the first isolation layer 37 and the second isolation layer 38 are formed.

Next, as shown in FIG. 2 (f), the epitaxial layer is selectively grown on the exposed first buried layer 32. At this time, the epi layer is grown to the height of the second isolation layer 38 while filling between the first and second isolation layers 37 and 38 on the first buried layer 32 to form the element formation layer 39. Let's do it.

Next, as shown in FIG. 2G, base ion implantation is performed to form a base region 40 in a predetermined portion of the element formation layer 39.

Next, as shown in FIG. 2 (h), emitter and collector ion implantation are performed to form the emitter region 41 in the base region 40 and the collector region 42 in the element formation layer 39.

Next, as shown in FIG. 2 (i), the second isolation layer 38 of the device isolation layer, the device formation layer 39 defined by the device isolation layer, and the base region 40 formed in the device formation layer 39. ) And an upper insulating layer 43 formed on the front surface of the semiconductor substrate 30 having the collector region 42 and the emitter region 41 formed in the base region 40. The bipolar transistor of the present invention is manufactured by forming a contact hole so that the emitter region 41 and the collector region 42 can be connected to the outside, and filling the contact hole with a metal to form the metal wiring layer 44.

The present invention reduces the size of the chip by reducing the design rule by using an oxide film instead of using the same conductive ion layer as the semiconductor substrate as the device isolation layer. In addition, by forming a trench and selectively growing an epitaxial layer therein, the width of the isolation layer can be minimized, thereby minimizing the width of the isolation layer, thereby improving the operation characteristics of the device. Minimized to significantly improve speed characteristics.

In addition, since the oxide film as the device isolation layer is not formed by the LOCOS process, the size of the device formation region can be prevented by BuzzBi, so that the size of the transistor can be reduced, and the surface is flattened because BuzzBi is not formed. Therefore, there is an effect that can solve the step coverage (step coverage) problem that occurs when forming a multi-layer metal wiring layer.

Claims (1)

A bipolar transistor in which a collector, a base, and an emitter region are formed in an element formation layer of a semiconductor substrate, the bipolar transistor comprising: a semiconductor substrate of a first conductivity type, a first buried layer of a second conductivity type formed in a predetermined portion on the semiconductor substrate; A second buried layer of a first conductivity type, which is used as a channel stop layer formed on the side of the first buried layer on the semiconductor substrate, and a heat treatment without using a mask on the entire surface of the semiconductor substrate including the first and second buried layers. A device isolation layer formed by patterning the first isolation layer to expose the first buried layer, the second isolation layer including a first isolation layer formed by oxidation and a silicon oxide film deposited on the first isolation layer by a chemical vapor deposition method; 1. A bipolar transistor comprising a device forming layer selectively epitaxially grown on a buried layer.