KR0118552Y1 - Data output buffer circuit for bicmos device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a data output buffer of a bi CMOS device in a semiconductor integrated circuit.

2. The technical problem to be solved by the invention

In a data input / output buffer having a data input / output common pad, a data output buffer that is not destroyed even if a voltage higher than an internal power supply voltage is applied from another chip.

3. Summary of solution of design

The data output buffer further includes a protection circuit 20 for increasing the immunity of the pull-up transistor 6 to the reverse voltage Vre applied to the output terminal 12, the protection circuit 20 further comprising a pull-up transistor 6 First output control signal to control The logic 'low' voltage level is increased by the voltage Vbe above the ground level (GND) and applied to the base of the pull-up transistor.

4. Important uses of the devise

It is used in data output buffers with common input / output pads in one-chip semiconductor devices.

Description

Data output buffer circuit of BiCMOS device

1 is a data output buffer circuit diagram of a conventional BiCMOS device.

2 is a data output buffer circuit diagram of a BiCMOS device of the present invention.

The present invention relates to a BICMOS device of a semiconductor integrated circuit, and more particularly, to a data input / output buffer that protects an internal circuit when a voltage greater than a predetermined power supply voltage is applied to a data input / output buffer supplied with a constant power supply voltage.

The data input / output buffer is divided into data input buffer and data output buffer in BiCMOS device. The output terminal of the data output buffer and the input terminal of the data input buffer are connected to one data input / output pad (or data input / output pin). Therefore, the data applied to the BICMOS device is input to the data input buffer through the data input / output pad, and the data output from the data output buffer of the BICMOS device is provided to the outside through the data input / output pad.

A data output buffer of a CMOS device is disclosed on pages 237 to 238 of the book title BiCMOS TECHNOLOGY AND APPLICATIONS, published by Antono R. Alvarez in 1989. The data output buffer of the BSIMOS device disclosed on page 238 has an NPN bipolar transistor for pull-up and an en-channel transistor for pull-down, and has noa gates for applying control signals to the base of the bipolar transistor and the gate of the en-channel transistor. have.

FIG. 1 shows a circuit having the same function as the data output buffer of the BiCMOS device described above, and replaces the noah gates with inverters 2 and 4. Referring to FIG. 1, the data output buffer circuit is composed of an NPN bipolar transistor 6 for pull-up and an enmo transistor 8 for pull-down. To the collector of the NPN bipolar transistor 6 for pull-up, a power supply voltage Vcc, for example, 3 volts of a bicymos device is applied. The common terminal of the resistor 10 connected to the emitter of the pull-up bipolar transistor 6 and the N-channel MOS transistor 8 is the output node 12 of the data output buffer. This output node 12 is connected to the data input / output pad of BiCMOS. The data output buffer is a three-state buffer and has a first output control signal. And second output control signal A DOUT signal corresponding to logic 'high''low' and 'high impedance' states is output to the output node 12 in response to a predetermined logic state.

The data input / output pad applies an input voltage applied from the outside to the data input buffer. Since the input terminal of the data input buffer is commonly connected to the output terminal of the data output buffer, the input voltage is also applied to the data output buffer. The data output buffer maintains a high impedance state when the input voltage is applied, wherein the first and second output control signals of the data output buffer are used. , Are all 'high' states.

However, in the circuit of the data output buffer described above, the CMOS device is destroyed when an input voltage equal to or greater than the power supply voltage Vcc, that is, a reverse voltage Vre (for example, about 5 volts) is applied to the output node 12 through the data input / output pad. There is a problem that can be destroyed or destroyed. An operation in which this problem occurs will be described in detail with reference to FIG. Now in FIG. 1, when the data output buffer is in the high impedance state, the first and second inverters 2 and 4 have first and second output control signals. , Are all applied in the 'high' state, and thus the inverter 2 applies the 'low' state to the pull-up NPN bipolar transistor 6, and the inverter 4 applies the 'low' state to the enmo transistor 8 for pull-down. ) Is applied. At this time, the 'luer' state applied to the transistors 6 and 8 is a ground level, that is, a '0' volt (DOU = 0). The pull-up NPN bipolar transistor 6 and the pull-down transistor 8 are not operated in the 'low' state. On the other hand, a reverse voltage Vre (for example, about 5 volts) equal to or greater than the power supply voltage of the data output buffer is applied from the data output pad, and the reverse voltage Vre is applied to the emitter and the base of the pull-up bipolar transistor 6 through the resistor 10. do. Since the breakdown voltage Vbrk of the pull-up bipolar transistor 6 is about 4.5 V to 5 V, the pull-up bipolar transistor 6 will be destroyed if the reverse voltage Vre is similar to or higher than the breakdown voltage Vbrk. Can be destroyed. That is, when a reverse voltage Vre of about 5 volts is applied from the outside, the pull-up bipolar transistor 6 may be destroyed or destroyed.

Accordingly, an object of the present invention is to provide a data output buffer circuit of a BiCMOS device which operates reliably even in a state where a voltage higher than an internal power supply voltage is applied from the outside in a semiconductor integrated circuit.

Another object of the present invention is to provide a data output buffer circuit that protects a BiCMOS device even when a voltage is applied above an internal power supply voltage.

It is still another object of the present invention to provide a data output buffer circuit that is not destroyed even when a voltage is applied over a power supply voltage of the data output buffer circuit.

Another object of the present invention is to provide a data output buffer circuit including a protection circuit for increasing the immunity of a pull-up transistor of the data output buffer circuit.

In accordance with the above object, the present invention provides a pull-down transistor for controlling a pull-up operation according to a first output control signal in a semiconductor integrated circuit, a common pad of a data input / output buffer common pad and the pull-up and pull-down transistor. And a protection circuit for reducing the level of reverse voltage applied from the output terminal to the pull-up transistor at least lower than the breakdown voltage level of the pull-up transistor from the output terminal. Circuit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals are used for the same elements in the drawings as much as possible. According to an embodiment of the present invention, the external input voltage applied to the data input / output pad of the BiCMOS device is, for example, a voltage level of at least higher than the power supply voltage level of the data output buffer, for example, 3 volts, for example, about 5 volts.

2 shows an embodiment of a data output buffer circuit of a BiCMOS device according to the present invention. The data output buffer circuit of the present invention further includes a protection circuit 20 for increasing the resistance of the pull-up transistor 6 of FIG. 2 to the reverse voltage Vre applied to the output terminal 12 of the data output buffer. The protection circuit 20 has a first output control signal as shown in FIG. It is characterized in that the voltage level of the logic 'low' state is applied to the base of the pull-up bipolar transistor 6 by raising the voltage level Vbe higher than the ground level GND, that is, '0' volts. When the configuration of the circuit 20 is described in detail, the gates of the MOS transistors 22 and 24, which are CMOS inverters, are connected to the first output control signal. The NPN bipolar transistor 26 is connected between the output terminal 30 of the MOS transistors 22 and 24 connected to the base of the pull-up bipolar transistor 6 and the drain of the MOS transistor 24 in common. . In the NPN bipolar transistor 26, an emitter is connected to a drain of the NMO transistor 24 having a base and a collector connected to the output terminal 30 and a source grounded. In addition, a resistor 28 to which a power supply voltage Vcc is applied is connected to an output line between the output terminal 30 of the Morse transistors 22 and 26 which are the CMOS inverters and the base of the pull-up transistor 6. The protection circuit 20 is configured to include the CMOS inverters 22 and 24 and the bipolar transistor 26, but the first output control signal is applied. Only the bipolar transistor 26 can be used in accordance with the logic state of the above, and this alone is sufficient to achieve the object of the present invention. That is, the bipolar transistor 26, the first output control signal And the first output control signal located between the pull-up transistor 6 And the first output control signal located between the pull-up transistor 6 A transistor is commonly connected to a base, the collector is connected to the base of the pull-up transistor 6, and an emitter is connected to ground. In addition, a resistor 28 to which a power supply voltage Vcc is applied is connected to the output terminal 30 of the MOS transistors 22 and 26 which are the CMOS inverters.

Now, the operation of the present invention will be described in detail with reference to the configuration of the protection circuit 20 of FIG. 2, in which the first output control signal when the data output buffer is in the high impedance state. Is applied in a 'high' state and the enmo transistor 24 is turned on. At this time, the PIO transistor 22 is turned off. In this state, the power supply voltage Vcc connected with the resistor 28 has a leakage current when the 'low' level of the resistor 28 and the output terminal 30 of the CMOS inverters 22 and 24 is long. Since it may not be maintained as much as Vbe to compensate for this so that the output terminal 30 maintains the Vbe level. The resistor 28 has a sufficient high impedance value so that only a weak current flows to compensate for the amount that can be lost by the leakage current. As a result, the output terminal 30 of the CMOS inverters 22 and 24 becomes a 'low' state. However, the 'low' state at this time maintains a level of Vbe higher than the conventional ground level GND, that is, '0' volts. This is the first output control signal This is because the junction voltage Vbe between the base and the emitter in the NPN bipolar transistor 26 exists even if the discharge path to the reference potential is formed by applying the 'high' state. Therefore, the voltage level DOU of the logic 'low' state at the output terminal 30 becomes GND + Vbe volts (GND: ground level). On the other hand, in the high impedance state of the data output buffer, the pull-down transistor 8 is turned off, and a reverse voltage Vre, for example, about 5 volts from the outside is applied to the pull-up transistor 6 through the output terminal 12 of the data output buffer. . Since the voltage held at the base of the pull-up transistor 6 is Vbe while the reverse voltage Vre is applied to the base and emitter of the pull-up transistor 6, the pull-up transistor 6 has a reverse voltage of Vre-Vbe. The effect is reduced. It can be seen that the reverse voltage applied to the pull-up transistor 6 is, for example, about 5 volts-0.7 volts, that is, about 4.3 volts, which is about 20 percent reduced from the original reverse voltage of about 5 volts. As a result, the breakdown voltage Vbrk of the pull-up transistor 6 is about 4.5-5 volts and the reduced reverse voltage is about 4.3 volts, so the pull-up transistor 6 is not destroyed. In addition, the pull-up transistor 6 has a margin of tolerance of 0.2 volts to 0.7 volts when the breakdown voltage Vbrk is applied. The pull-up transistor 6 has increased immunity by a reduced reverse voltage.

As described above, the data output buffer of the present invention reduces the voltage level to a reverse voltage that can be sufficiently endured by the internal circuit even if a reverse voltage of the internal power supply voltage is applied, thereby increasing the immunity of the internal circuit preventing the reverse voltage. have. In addition, even if an internal power supply voltage is applied, the data output buffer of the present invention has an advantage of performing reliable operation without being destroyed.

Claims (6)

A semiconductor integrated circuit comprising: a pull-up transistor for controlling a pull-up operation in accordance with a first output control signal, a pull-down transistor for controlling a pull-down operation in accordance with a second output control signal, and located between the pull-up and pull-down transistors. And an output terminal connected to a data input / output buffer common pad and located between the first output control signal and an input terminal of the pull-up transistor, and when a reverse voltage is applied to the pull-up transistor through the output terminal, the reverse voltage level is applied. And a protection circuit for lowering the breakdown voltage level of the pull-up transistor at least lower than the breakdown voltage level of the pull-up transistor. The method of claim 1, wherein the protection circuit is located between the first output control signal and the base of the pull-up transistor, a base and a collector are commonly connected to the first output control signal, the collector for the pull-up And a resistor connected to the base of the transistor, the transistor having an emitter connected to ground, and a resistor connected to the collector of the transistor and receiving a power supply voltage. The output terminal of claim 1, wherein the protection circuit is connected to an input common and is connected to the first output control signal, and comprises a CMOS inverter comprising an N-channel transistor and a P-channel transistor, and an output terminal of the CMOS inverter connected to the pull-up transistor. The transistor is connected to the collector and the base in common, the transistor of the emitter connected to the drain of the CMOS inverter N-channel transistor, and the resistor connected to the output terminal of the CMOS inverter is applied to the power supply voltage, characterized in that Data output buffer circuit of Morse device. 4. The data output buffer circuit as claimed in claim 3, wherein the resistance has a high impedance value sufficient to compensate for a leakage current. In the BiCMOS device, a pull-up transistor for controlling the pull-up operation by the first output control signal, a pull-down transistor for controlling the pull-down operation by the second output control signal, and positioned between the pull-up and pull-down transistors A data output buffer including an output terminal connected to a common pad of a data input / output buffer, said data output buffer being located between said first output control signal and an input terminal of said pull-up transistor, wherein a level of reverse voltage applied from said output terminal to said pull-up transistor is adjusted. And a circuit for maintaining a 'low' state level of the first output control signal to a predetermined voltage higher than the ground level so as to drop at least lower than the breakdown voltage level of the pull-up transistor. Output buffer circuit. 6. The data output buffer circuit as claimed in claim 5, wherein said voltage is 0.7 volts.