KR0183588B1 - An external form testing device of video head-chip - Google Patents

Abstract

The present invention relates to an apparatus for inspecting the appearance of a video head chip, wherein the vertical line counter circuit unit counts the interval between vertical lines generated from the vertical line generating circuit unit at a high clock frequency, and the vertical line output from the vertical line counter circuit unit. A vertical inter-line computing unit for multiplying the countered data at a predetermined magnification, a horizontal inter-line counter circuit unit for counting the interval between the horizontal lines generated from the horizontal line generating circuit unit at a high clock frequency, and outputting from the horizontal inter-line counter circuit unit. A chip select signal for character information data generation by a horizontal interline calculation unit for multiplying the countered data between the horizontal lines at a predetermined magnification, and the data counted from line to line from each of the vertical line operation circuits and the horizontal line operation; OSD circuit to output serial clock and serial data By measuring the appearance state and damage parts of the head chip image input by CCD camera with reference line and measurement line, the measured result is output on the monitor screen, In discriminating, it is possible to maximize the productivity as well as improve the reliability of the product by improving the efficiency of the worker's head chip external inspection.

Description

Video head chip visual inspection device

The present invention relates to a video head chip visual inspection apparatus, and in particular, the appearance state of the head chip image input to the CCD camera and the damage portion of the appearance is measured by the reference line and the measurement line shown on the monitor and the measured results are displayed on the screen. The present invention relates to a video head chip visual inspection apparatus capable of improving the quality of a video head chip as well as doubling the appearance inspection efficiency of an operator to improve productivity.

In general, a video head is wound around a core with a very narrow gap on one side. The head of the video head is equipped with a head chip that picks up the magnetized signal as an electrical signal on the video tape, and plays a role of inputting and outputting signals for playing and recording the video tape. In addition, the video head chip is worn out by friction with the video tape, and if it is soiled by foreign matters such as dust, it adversely affects the image quality. As such, the video head chip, which plays a decisive role in video quality, must thoroughly control quality from the production stage by measuring not only electrical characteristics but also appearance specifications and tolerances thereof.

As described above, the conventional apparatus for inspecting the appearance of a video head chip is a CCD (CHARGE COUPLED DEVICE) camera 71 configured to input a subject as an image signal by using a head chip 70 placed in a specific jig as an image pickup device as shown in FIG. 1. ), A multiplier 72 for enlarging a video signal input to the CCD camera 71 at a constant magnification, and a monitor 72 for outputting a video signal of a head chip enlarged at a constant magnification by the multiplier 72 to a screen. )

As described above, referring to the operation of the apparatus for inspecting the appearance of the conventional video head chip, the operator places the head chip 70 in a specific jig to inspect the appearance inspection of the head chip 70 in the process line. Then, in the CCD camera 71 provided at a certain distance from the head chip 70, the shape of the object, that is, the video head chip 70, is formed on the image pickup tube of the CCD camera 71 by input of power. At this time, the subject input to the image pickup tube of the CCD camera 71 is converted into a constant electric video signal and input to a multiplier 72 that amplifies the video signal at a constant magnification. Then, the multiplier 72 amplifies the input video signal at a predetermined magnification and inputs it to the monitor 73 outputting the screen. Therefore, the input video signal displayed on the monitor 73 is confirmed on the screen, and the operator grasps the appearance state of the head chip 70 to sort out the defective head chip and the good head chip.

However, in the conventional video head chip visual inspection apparatus as described above, an operator visually inspects the head chip by visual inspection while simply looking at the image of the head chip at a high magnification. Therefore, the appearance specification of the head chip, that is, the width of the chip, depends on the visual inspection of the operator. Length. There was a problem in that the reliability of the product itself was deteriorated due to the difficulty in quality control due to the uncertainty of the acceptance judgment as well as the determination of the tolerance of the chip which caused the gas.

The present invention has been made to solve the above-mentioned problems, the data of measuring the appearance specifications of the head chip using the reference line and the measurement line on the monitor in determining the quality of the product through the inspection of the processed head chip appearance The purpose of the present invention is to provide a video head chip visual inspection apparatus that can improve the reliability of the product as well as maximize productivity by improving the efficiency of the head chip visual inspection by checking the value.

The present invention for achieving the above object is a counter between the vertical line between the vertical line generated from the vertical line generating circuit unit counter clock unit and the vertical line output from the counter between the vertical line counter circuit unit A vertical inter-line computing unit for multiplying data at a predetermined magnification, a horizontal inter-line counter circuit unit for counting the interval between the horizontal lines generated from the horizontal line generating circuit unit at a high clock frequency, and a horizontal output from the horizontal inter-line counter circuit unit. A chip select signal for generating character information data by means of horizontal line interpolation unit for multiplying the countered data between lines at a constant magnification, and data counted between lines in each of the vertical line operation circuit and horizontal line operation circuit. It consists of OSD circuit part to output clock and serial data It shall be.

1 is a block diagram illustrating a conventional video head chip visual inspection;

2 is an overall block diagram illustrating a video head chip visual inspection of the present invention;

3 (a) is a block diagram illustrating a count between vertical lines according to the present invention;

3 (b) is a block diagram illustrating a count between horizontal lines according to the present invention;

4 is a block diagram illustrating the calculation of horizontal and vertical lines according to the present invention;

Figure 5 (a) is a state diagram of the display on the monitor where each line according to the present invention is displayed and data is displayed due to the OSD,

5 (b) is a timing chart for chip selection, serial clock, and serial data input according to the present invention.

Explanation of symbols for main parts of the drawings

1: Head chip 2: CCD camera

3: OSD circuit section 4: Video signal synthesis section

5 monitor 6 synchronization generating unit

7: vertical line generating circuit part 8: vertical line counter circuit part

9: Vertical circuit operation circuit 10: Vertical magnification regulator

11: horizontal line generating circuit part 12: horizontal line counter circuit part

13: horizontal line operation circuit part 14: horizontal magnification controller

15: data operation unit 16: vertical exclusive ogate

17: vertical clock counter 18: vertical oscillator

19: vertical data latch portion 20: horizontal exclusive ogate

21: horizontal clock counter 22: horizontal oscillator

23: horizontal data latch portion 24: multi-channel portion

25: selection control unit 26: switch unit

27: vertical binary multiplier 28: vertical decimal conversion unit

29: horizontal binary multiplier 30: horizontal decimal conversion unit

31 RAM 32 Vertical Display

33: horizontal display unit

As shown in FIG. 2, the present invention adds a CCD camera 2 for inputting an image of the video head chip 1 as an image signal, and a calculated data value to the image signal input to the CCD camera 2, OSD (On Screen Display) circuit section 3 for display on the monitor 5, video of the head chip input to the OSD circuit section 3, the video signal between each line and the multiplication operation data to the video signal A signal synthesizing section 4, a synchronizing generator 6 for inputting a signal for vertical synchronism and a horizontal synchronizing signal to the CCD camera 2, and a vertical and horizontal synchronizing signal generated by the synchronizing generator 6; A vertical line generating circuit unit 7 which receives a vertical line and generates a vertical line, and a vertical interline counter circuit unit which counts a vertical line generated from the vertical line generating circuit unit 7, that is, a distance between a reference line and a measuring line at a high clock frequency ( 8) and output to this vertical line counter circuit section 8 Connected between the vertical line interoperation circuit section 9 for multiplying the multiplied by the value adjusted in the vertical magnification controller 10 for adjusting the counter signal between the direct lines at a constant magnification and the synchronization generating circuit section 6; A horizontal line generating circuit section 11 for generating a horizontal line as a synchronization signal inputted and a horizontal line output from the horizontal line generating circuit section 11, that is, a distance between a reference line and a measuring line at a clock frequency of about 32 KHz. Multiply by the horizontal line counter circuit unit 12 for counting, the counter signal outputted from the horizontal line counter circuit unit 12, and the value adjusted in the horizontal magnification controller 14 for amplifying at a constant magnification. It consists of the horizontal line between the operation circuit portion (13).

The video signal synthesizing unit 4 is connected to a monitor 5 for outputting a combined video signal of an input head chip image signal, a vertical horizontal line signal, and an OSD output data. In addition, the vertical line between the operation circuit unit 9 is connected to the vertical magnification controller 10 for adjusting the vertical line at a constant magnification, and the horizontal line between the operation circuit unit 13 and the horizontal magnification adjuster for adjusting the horizontal line at a constant magnification. (14) is connected.

As shown in FIG. 3 (a), the vertical line counter circuit section 8 includes a vertical exclusive orifice 16 for setting the width between the reference line and the measurement line generated in the vertical line generating circuit section 7, A vertical clock counter unit 17 that receives the frequency of the vertical oscillator 18 oscillating a frequency of about 10.5 MHz in the interval between the two lines set by the exclusive oragate 16 and counts the clock frequency at the clock frequency, and the vertical clock counter unit It consists of a vertical data latch unit 19 for storing the frequency data signal counted in (17).

The vertical data latch unit 19 is connected to a vertical interline calculation circuit unit 9 that receives a counter data signal and adjusts it at a predetermined magnification.

In addition, as shown in (b) of FIG. 3, the horizontal line-to-line counter circuit part 12 includes a horizontal exclusive ogate 20 for setting a width between the reference line and the measurement line generated in the horizontal line generating circuit part 11; A horizontal clock counter 21 for counting the width section between the lines set by the horizontal exclusive orifice 20 at a clock frequency of the horizontal oscillator 22 oscillating at a frequency of about 32 KHz, and the horizontal clock counter 21 It consists of a horizontal data latch unit 23 for storing the data signal counted from.

The horizontal data latch unit 23 is connected with a horizontal line inter-operation circuit unit 13 which receives a counter data signal and adjusts it at a predetermined magnification.

In addition, the vertical inter-line arithmetic circuit 9 and the horizontal inter-line arithmetic circuit 13 consist of a data operator 15 instead of a separate circuit in the vertical inter-line counter circuit 8 and the horizontal inter-line counter circuit 12. The selection control unit 25 selects the vertical and horizontal line data as shown in FIG. A multi-channel unit 24 which switches are switched to input data counted by the vertical line-to-line counter circuit unit 8, and a switch which is switched to input vertical line counted data by switching of the multi-channel unit 24 The unit 26 and the data inputted by the switching of the switch section 26 and the data inputted from the vertical magnification controller 10 which magnifies the vertical line signal to a predetermined level are multiplied by a binary number. Is a vertical binary multiplier 27, a vertical decimal converting unit 28 for converting binary data inputted to the vertical binary multiplier 27 into decimal data and outputting the data as 4 bytes; It consists of a RAM 31 for sequentially storing the data of 4 bytes output from the decimal conversion unit 28.

And a horizontal binary multiplier 29 for multiplying the data input by the switching of the switch section 26 and the data input from the horizontal magnification controller 14 which multiplies the horizontal line signal with a binary number. A horizontal decimal converter 30 for converting binary data input to the multiplier 29 into a decimal number and outputting 4 bytes of data; and 4 bytes of data output from the horizontal decimal converter 30. It consists of a RAM 31 for sequentially storing.

Next, the operation of the present invention having the above configuration will be described.

First, when the video head chip 1 is placed in a specific jig, an image of the head chip 1 is input to the CCD camera 2 focused at a constant distance. Then, the image signal input to the CCD camera 2 is input to the OSD circuit section 3, and the vertical synchronization signal and the horizontal synchronization signal generated from the synchronization generator 6 are input to each circuit terminal to synchronize. At this time, this synchronization signal is input to the vertical line generating circuit section 7 to generate a reference vertical line and a measuring vertical line. Therefore, the signals of the reference vertical line and the measurement vertical line generated by the vertical line generating circuit portion 7 are inputted to the vertical line counter circuit portion 8 to count the interval between the line signals at a high clock frequency (approximately 10.5 MHz). It is to output data value.

That is, as shown in FIG. 3 (a), the reference vertical line signal and the measurement vertical line signal output from the vertical line generation circuit unit 7 are input to the vertical exclusive ogate 16. Then, the vertical exclusive ogate 16 sets the width between the vertical lines and inputs the vertical clock counter 17. Then, the vertical clock counter unit 17 counts the section between the reference line and the measurement line as the frequency (about 10.5 MHz) oscillated from the vertical oscillator 18. At this time, the data counted by the vertical clock counter unit 17 is stored in the vertical data latch unit 19.

Therefore, the countered data of the vertical line section output from the vertical data latch section 19 is input to the vertical line intercomputing circuit section 9, and in this vertical line intercomputing circuit section 9, the counted data signal and the vertical magnification adjuster ( In step 10), a signal adjusted at a predetermined magnification is input to perform a multiplication operation, and the resulting data is input to the OSD circuit unit 3.

At the same time, as shown in (b) of FIG. 3, the horizontal line generating circuit unit 11 receiving the synchronization signal generated by the synchronization generating unit 6 generates a reference horizontal line and a measurement horizontal line. Therefore, the signals of the reference horizontal line and the measurement horizontal line generated by the horizontal line generating circuit unit 11 are input to the counter circuit unit 12 between the horizontal lines. Then, the horizontal line-to-counter circuit unit 12 counts the interval between input line signals at a set clock frequency (about 32 KHz).

That is, the reference horizontal line signal and the measurement horizontal line signal output from the horizontal line generation circuit unit 11 are input to the horizontal exclusive ogate 20 to set the width between the horizontal line signals and input to the horizontal clock counter unit 21. do. Then, the horizontal clock counter unit 21 receives the frequency (about 32KHz) oscillated from the horizontal oscillator 22 to count the horizontal line section. At this time, the data counted by the horizontal clock counter unit 25 is stored in the horizontal data latch unit 23.

Therefore, the counted data between the horizontal lines output from the horizontal data latch unit 23 is input to the horizontal line inter-operation circuit unit 13, and the data signal between the horizontal lines counted in the horizontal line-to-line operation circuit unit 13 and the horizontal magnification. The controller 14 receives a signal adjusted at a predetermined magnification and performs a multiplication operation, and the result value is input to the OSD circuit unit 3.

On the other hand, the vertical interline computation circuit 9 and the horizontal interline computation circuit 13 multiplying the data input to the OSD circuit section 3 actually select alternately the counter data between the vertical lines and the counter data between the horizontal lines. While the signal is calculated and the output is composed of an integral data operation unit 15 to send sequentially one by one, as shown in Figure 4 when the vertical inter-line counter data of the vertical inter-line counter circuit unit 8 is inputted, the selection control unit In the multichannel unit 24 which performs switching operation under the control of 25, the vertical counter data is input to the vertical binary multiplier 27 by turning on the switch unit 26. In this case, a vertical magnification adjusting unit 10 is connected to the vertical binary multiplier 27 so that the input vertical inter-counter counter data is adjusted to a predetermined level to perform a binary operation and is input to the vertical decimal converting unit 28. . Therefore, the vertical decimal converting section 28 stores the data (4 bytes in total) converted from binary data into a decimal number in the RAM 31.

Then, in order to input the signal of the horizontal line counter circuit unit 11 as the control signal of the selection control unit 25, the multi-channel unit 24 is channel switching. Therefore, the switch unit 26 is switched to the horizontal binary multiplier 29 so that the horizontal counter data is input to the horizontal binary multiplier 29 of the data operator 15. At this time, the horizontal binary multiplier 29 is connected to the horizontal magnification adjusting unit 14 to perform binary operation with the input horizontal counter data, and then input the binary data to the horizontal decimal converter 30 to convert the binary data into decimal data. Is converted to. Then, the horizontal decimal conversion unit 30 stores the output data (4 bytes in total) in the RAM 31.

As such, data between the vertical and horizontal lines stored in the RAM 31 is sequentially input to the one-chip microcomputer (not shown) of the OSD circuit unit 3, and this data is a synchronization signal. It is input to the video signal synthesizing section 4 together with the count signal between lines and the video signal of the head chip.

That is, the data operation unit 15 inputs the measurement data between the lines to the OSD circuit unit 3 by the adjusted magnifications input from the vertical magnification controller 10 and the horizontal magnification controller 14. As shown, the one-chip microcomputer of the OSD circuit unit 3 inputs the input data together with the serial data input (SIN: character data signal) and a predetermined delay time for the chip select signal CS and the chip select signal CS. That is, the serial clock (SCK) signal having a delay time of about 2mS is controlled. At this time, the serial data input (SIN) is synchronized by the serial clock (SCK) and the operator operates the adjusting unit installed in the vertical line generating circuit portion 7 and the horizontal line generating circuit portion 11, the program of the one chip microcomputer according to the serial timing chart Each vertical and horizontal lines are interlocked to change the video signal of the head chip 1. The synchronization signal and the counter signal between each line are the video signal of the head chip and the chip selection signal CS inputted from the OSD circuit section 3. The serial clock signal SCK and the serial data SIN are received and mixed by the video signal synthesis unit 4 and output to the monitor 5. That is, as shown in FIG. 5A, a reference vertical line and a reference horizontal line for setting a position to be measured of the head chip 1 are displayed at a predetermined position on the screen of the monitor 5, and the head chip is displayed. The measurement vertical line and the measurement horizontal line, which are the measurement lines up to the portion to be measured in (1), are displayed, and the vertical display part 32 and the horizontal display part 33 are arranged at predetermined positions on the upper part of the monitor 5 to measure the measured head chip. Appearance The measured values on the vertical and horizontal sides are displayed.

In the present invention, the head chip is positioned at each reference line displayed on the monitor in the appearance inspection of the head chip, and the respective measurement lines are positioned at positions up to the portion to be measured by operating the interlocking adjustment part of each line counter circuit. Thus, data values, such as the appearance specifications of the head chip, that is, the width, length of the chip, and the tolerance of chips generated by the chip, are displayed on the screen. Therefore, the operator can check the value displayed on the screen to accurately determine whether the head chip or not, and the accurate quality control has the effect of maximizing productivity as well as improving the reliability of the product itself.

Claims (3)

A synchronization generator 6 for applying a synchronization signal to an image signal output from the CCD camera 2, and a vertical line generation circuit unit 7 for generating a vertical line by receiving the synchronization signal generated by the synchronization generator 6; And a horizontal interline counter circuit unit 8 for counting the interval between the vertical lines generated from the vertical line generation circuit unit 7 and a horizontal line for receiving a synchronization signal generated from the synchronization generation unit 6 to generate a horizontal line. A horizontal interline counter circuit unit 12 for counting the interval between the line generating circuit unit 11, the horizontal lines generated by the horizontal line generating circuit unit 11, the vertical interline counter circuit unit 8, and a horizontal interline counter The data operation unit 15 for calculating the data output from the circuit unit 12 and the data selected by the data operation unit 15 calculate and output a chip select signal, serial clock and serial data for character information data generation. The OSD circuit section 3, and a video in which the chip select signal, the serial clock and the serial data output data signal from the OSD circuit section 3, the video signal of the head chip, and the counted line signal of the counter circuit section between each line are mixed. A video head chip visual inspection apparatus comprising: a signal synthesizing unit (4) and a monitor (5) for outputting a composite video signal inputted to the video signal synthesizing unit (4) on a screen. The vertical line interpolator (9) according to claim 1, wherein the data operator (15) multiplies the counter data between the vertical lines output from the vertical line counter circuit unit (8) at a predetermined magnification, and between the horizontal lines. A video head chip visual inspection apparatus, comprising: a horizontal line inter-operation circuit unit 13 for multiplying the countered data between horizontal lines output from the counter circuit unit 12 at a predetermined magnification. 2. The monitor (5) according to claim 1, wherein the monitor (5) comprises a vertical display section (32) for displaying data between measured vertical lines and a horizontal display section (33) for displaying data between horizontal lines measured at the monitor (5). Video head chip visual inspection device, characterized in that.