KR0181961B1 - Method of forming contact plug of semiconductor device - Google Patents
Method of forming contact plug of semiconductor device Download PDFInfo
- Publication number
- KR0181961B1 KR0181961B1 KR1019910014939A KR910014939A KR0181961B1 KR 0181961 B1 KR0181961 B1 KR 0181961B1 KR 1019910014939 A KR1019910014939 A KR 1019910014939A KR 910014939 A KR910014939 A KR 910014939A KR 0181961 B1 KR0181961 B1 KR 0181961B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- insulating film
- contact plug
- insulating
- contact hole
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 10
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- -1 USG Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical group 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
소정기판상에 제1절연막을 형성하고 제1절연막의 소정부분에 접촉구를 형성한후 상기 접촉구가 매몰되도록 도전층을 형성한다. 그다음 상기 제1절연막상의 도전층을 제거하여 접촉구 상부에 도전막대를 형성한후 제2절연막을 형성한다. 그후 제2절연막을 에치백하여 도전막대의 상부를 노출시켜 도전체로 완전히 채워진 접촉플러그를 형성한다. 따라서 애스팩트비가 큰 접촉구의 경우에도 접촉구 내에 보이드, 단락등의 결함이 생기지 않도록 도전체로 완전히 채워진 접촉플러그를 얻을 수 있으며, 또한 반도체 기판상에 서로다른 도전형의 확산영역을 가진 접촉구를 동시에 도전체로 매몰하여 접촉플러그를 형성하므로 공정이 간단하다.After forming a first insulating film on a predetermined substrate and forming a contact hole in a predetermined portion of the first insulating film, a conductive layer is formed to bury the contact hole. Next, the conductive layer on the first insulating layer is removed to form a conductive rod on the contact hole, and then a second insulating layer is formed. Thereafter, the second insulating layer is etched back to expose the upper portion of the conductive rod to form a contact plug completely filled with the conductor. Therefore, even in the case of a contact with a large aspect ratio, a contact plug completely filled with a conductor can be obtained in order to prevent voids, short circuits, and the like from occurring in the contact. Since the contact plug is formed by embedding with a conductor, the process is simple.
Description
제1a~e도는 종래기술에 따른 접촉플러그 제조공정도.Figure 1a to e is a contact plug manufacturing process according to the prior art.
제2a~c도는 이 발명에 따른 접촉플러그 제조공정도이다.2a to c is a manufacturing process of the contact plug according to the present invention.
이 발명은 반도체장치의 접촉플러그 제조방법에 관한 것으로, 특히 애스팩트 비(Aspect ratio)가 큰 반도체장치의 접촉구(Contact hole)에서의 접촉플러그(Contact plug)제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a contact plug of a semiconductor device, and more particularly, to a method of manufacturing a contact plug in a contact hole of a semiconductor device having a large aspect ratio.
최근 반도체 제조기술의 발달과 반도체 장치의 고집적화 추세에 따라 반도체 장치가 소형화, 경량화 되어가고 있다. 더우기 반도체 장치가 고집적화 되어감에 따라 소자의 면적축소의 속도가 두께축소의 속도를 훨씬 앞서가고 있다. 특히, 반도체기판과 금속배선, 금속배선과 금속배선등을 수직으로 연결하는 접촉구의 지름이 1㎛ 이하의 크기로 감소하고 애스팩트비가 1이상으로 증가하게 되어 접촉구의 매몰이 반도체장치의 효율과 신뢰성에 큰 영향을 미치게 되었다. 애스팩트비가 1이상인 접촉구의 경우 금속으로 직접 접촉구를 매몰시키면 금속배선의 단차피복성(Step coverage)이 나빠지고 심하면 단선의 경우도 발생하게 된다. 이를 개선하기 위해 접촉구를 경사 식각하는 방법, 반도체기판과 같은 도전형의 불순물로 도핑된 다결정 또는 비정질 실리콘으로 매몰하는 방법 또는 금속 실리사이드로 매몰하는 방법등 여러가지 방법이 활발이 연구되고 있다.Recently, with the development of semiconductor manufacturing technology and the trend of high integration of semiconductor devices, semiconductor devices are becoming smaller and lighter. Moreover, as semiconductor devices become more integrated, the area reduction rate of the device is much ahead of the thickness reduction rate. In particular, the diameter of the contact hole connecting the semiconductor substrate and the metal wiring, the metal wiring and the metal wiring vertically is reduced to the size of 1 μm or less, and the aspect ratio is increased to 1 or more, so that the contact hole is more efficient and reliable. Has had a big impact. In the case of a contact hole having an aspect ratio of 1 or more, if the contact hole is directly buried with metal, the step coverage of the metal wiring becomes worse, and in the case of severe disconnection, the contact hole may occur. In order to improve this, various methods such as a method of oblique etching of contact holes, a method of embedding with polycrystalline or amorphous silicon doped with a conductive impurity such as a semiconductor substrate, or a method of embedding with a metal silicide have been actively studied.
제1a~e도는 종래기술에 따른 접촉플러그 제조공정도이다. 제1a도를 참조하면, 반도체기판(1)상에 절연막(3)을 형성하고, 상기 절연막(3)상에 감광막 패턴(5)을 형성한다. 그다음 상기 절연막(3)의 노출된 부분을 제거하여 접촉구(6)를 형성한후 상기 반도체기판(1)의 노출된 부분에 상기 접촉구(6)를 통해 이온주입 또는 확산등의 방법으로 금속배선과의 옴믹(Ohmic)접촉을 위한 확산영역(7)을 형성한다.1a to e is a manufacturing process of the contact plug according to the prior art. Referring to FIG. 1A, an insulating film 3 is formed on a semiconductor substrate 1, and a photosensitive film pattern 5 is formed on the insulating film 3. Then, the exposed portion of the insulating film 3 is removed to form the contact hole 6, and then a metal such as ion implantation or diffusion through the contact hole 6 is exposed to the exposed portion of the semiconductor substrate 1. A diffusion region 7 for ohmic contact with the wiring is formed.
제1b도를 참조하면, 상기 감광막패턴(5)을 제거하고, 상기 절연막(3)의 상부에 화학기상도포(Chemical Vapor Deposition) 법으로 확산영역(7)과 같은 도전형의 불순물로 도핑된 실리콘층(9)을 접촉구(6)가 매몰되도록 형성한다. 이때 상기 실리콘층(9)은 다결정 또는 비정질 실리콘층으로 형성한다. 그 다음, 상기 실리콘층(9)의 상부에 물리증착 또는 화학기상도포에 의해 Ti, W, Co 및 Mo등의 고융점 금속으로 제1금속층(11)을 형성한다.Referring to FIG. 1B, the photoresist film pattern 5 is removed and silicon doped with a conductive impurity such as the diffusion region 7 by a chemical vapor deposition method on the insulating film 3. The layer 9 is formed such that the contact hole 6 is buried. In this case, the silicon layer 9 is formed of a polycrystalline or amorphous silicon layer. Next, the first metal layer 11 is formed of a high melting point metal such as Ti, W, Co, and Mo by physical vapor deposition or chemical vapor deposition on the silicon layer 9.
제1c도를 참조하면, 상기 실리콘층(9)과 제1금속층(11)을 열처리등의 방법으로 실리사이드화하여 제1실리사이드층(12)을 형성한다.Referring to FIG. 1C, the silicon layer 9 and the first metal layer 11 are silicided by a method such as heat treatment to form the first silicide layer 12.
제1d도를 참조하면, 상기 제1실리사이드층(12)을 에치백(etch back)하여 절연막(3)을 노출시킨다. 그다음 상기 접촉구(5)내의 실리콘층(9)을 실리사이드화 하기위한 제2금속층(14)을 Ti, W, Co 및 Mo등 고융점 금속재료를 사용하여 물리증착 또는 화학기상도포 법으로 형성한다. 이때 제2금속층(14)의 두께는 접촉구(5)내의 실리콘층(9)을 완전히 실리사이드화 할수있는 정도로 한다. 그러나 확산영역(7)이 얕은 접합(Shallow Junction)일 경우가 많으므로 금속 실리사이드가 확산영역을 관통하지 않도록 한다.Referring to FIG. 1D, the first silicide layer 12 is etched back to expose the insulating layer 3. Then, the second metal layer 14 for silicidating the silicon layer 9 in the contact hole 5 is formed by physical vapor deposition or chemical vapor deposition using high melting point metal materials such as Ti, W, Co, and Mo. . At this time, the thickness of the second metal layer 14 is such that the silicon layer 9 in the contact hole 5 can be completely silicided. However, since the diffusion region 7 is often a shallow junction, the metal silicide does not penetrate the diffusion region.
제1e도를 참조하면, 상기 구조의 실리콘층(9)과 제2금속층(14)을 열처리등의 방법으로 실리사이드화하고 절연막(3)상부의 실리사이드화 하지 않은 제2금속층(14)을 제거하여 접촉플러그(15)을 형성한다.Referring to FIG. 1E, the silicon layer 9 and the second metal layer 14 of the structure are silicided by a method such as heat treatment, and the unsilicided second metal layer 14 on the insulating film 3 is removed. The contact plug 15 is formed.
상기 종래기술에 의한 접촉플러그 제조방법은 애스팩트비가 매우 큰 접촉구의 경우 실리콘층으로 접촉구를 매몰할때 오버행(Over hang)에 의해 접촉구의 중앙에 보이드(Void)가 형성되어 접촉플러그의 누설전류가 증가하거나 단락이 발생하는등 반도체 장치의 신뢰성 및 효율을 저하시키는 문제점들이 있었다. 또한 접촉구내의 실리콘층을 완전히 금속 실리사이드화 하는 것이 어려워 실리콘층을 확산영역과 같은 도전형의 불순물로 도핑하여야 하므로 서로다른 도전형의 확산영역이 존재하는 기판에 접촉플러그를 만들 경우 공정이 복잡한 문제점이 있었다.In the method of manufacturing a contact plug according to the related art, in the case of a contact hole having a very large aspect ratio, a void is formed in the center of the contact hole by overhanging when the contact hole is buried with a silicon layer, and the leakage current of the contact plug is caused. There is a problem that decreases the reliability and efficiency of the semiconductor device, such as increases or short circuit occurs. In addition, it is difficult to completely silicide the silicon layer in the contact hole. Therefore, the silicon layer must be doped with a conductive type impurity such as a diffusion region. Therefore, the process is complicated when a contact plug is formed on a substrate having different conductivity type diffusion regions. There was this.
따라서, 이 발명의 목적은 접촉구내의 보이드 및 단락등의 결함생성을 방지하고 공정이 간단하여 신뢰성 및 효율을 향상시킬 수 있는 반도체 장치의 접촉플러그 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a contact plug of a semiconductor device which can prevent the generation of defects such as voids and short circuits in a contact hole and can improve the reliability and efficiency by a simple process.
상기와 같은 목적을 달성하기 위하여 이 발명은 반도체 장치의 제조방법에 있어서, 소정기판의 상부에 제1절연막을 형성하고 제1절연막의 소정부분에 접촉구를 형성하는 공정과, 상기 접촉구가 매몰되도록 도전층을 형성한후 상기 제1절연막 상부의 도전층을 제거하여 도전막대를 형성하는 공정과, 상기 제1절연막 및 도전막대의 전표면에 제2절연막을 형성하는 공정과, 제2절연막의 상부를 식각하여 상기 도전막대의 상부를 노출시키는 공정으로 이루어진다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a first insulating film on an upper portion of a predetermined substrate and forming a contact hole in a predetermined portion of the first insulating film; Forming a conductive rod by removing the conductive layer on the first insulating film after forming the conductive layer, forming a second insulating film on all surfaces of the first insulating film and the conductive rod, Etching the upper portion to expose the upper portion of the conductive rod.
이하 도면을 참조하여 이 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a~c도는 이 발명에 따른 접촉플러그 제조공정도이다.2a to c is a manufacturing process of the contact plug according to the present invention.
제2a도를 참조하면, 소정기판(21)상에 제1절연막(23)을 2000Å 이하의 두께로 형성한후 통상의 사진식각 공정에 의해 제1절연막(23)의 소정부분에 접촉구를 형성한다. 이때 상기 기판(21)으로는 반도체 또는 금속기판이 사용되며 또한 제1절연막(23)은 산화규소나 질화규소 또는 USG(Undoped Silicate Glass), BPSG(Boro-Phospho Silicate Glass), PSG(Phospho Silicate Glass) 및 BSG(Boro Silicate Glass)등 유리재질 절연물질이 사용된다. 상기 제1절연막(23)의 두께는 도전체로 직접 접촉구를 매몰하는 후속공정 진행시 도전층의 단차피복성이 악화되지 않는범위 즉, 애스팩트비(Aspect ratio)가 작은 범위에서 적당히 조절한다. 또한, 상기 기판(21)으로 반도체를 사용할 경우 노출된 기판(21)상에 통상의 방법으로 확산영역을 형성한다. 그 다음 상기 접촉구가 매몰되도록 도전체중에서 Al, Ti, Ta, W 및 Mo등 금속을 물리증착 또는 화학기상도포법으로 금속층(25)을 형성한다. 이때, 상기 금속층(25)의 두께는 접촉플러그의 두께와 같은 정도로 형성한다. 그후 상기 접촉구를 매운 금속층(25)의 상부에 감광막 패턴(27)을 형성한다.Referring to FIG. 2A, after forming the first insulating film 23 on the predetermined substrate 21 to have a thickness of 2000 GPa or less, a contact hole is formed in a predetermined portion of the first insulating film 23 by a normal photolithography process. do. In this case, a semiconductor or metal substrate is used as the substrate 21, and the first insulating layer 23 may be formed of silicon oxide, silicon nitride, or USG (Undoped Silicate Glass), BPSG (Boro-Phospho Silicate Glass), or PSG (Phospho Silicate Glass). And glass insulating materials such as BSG (Boro Silicate Glass). The thickness of the first insulating layer 23 is appropriately adjusted in a range in which the step coverage of the conductive layer is not deteriorated during the subsequent process of embedding the contact hole directly into the conductor, that is, the aspect ratio is small. In addition, when a semiconductor is used as the substrate 21, a diffusion region is formed on the exposed substrate 21 by a conventional method. Then, the metal layer 25 is formed by physical vapor deposition or chemical vapor deposition of metals such as Al, Ti, Ta, W, and Mo in the conductor so that the contact hole is buried. At this time, the thickness of the metal layer 25 is formed to the same extent as the thickness of the contact plug. Thereafter, the photoresist pattern 27 is formed on the metal layer 25 filled with the contact hole.
제2b도를 참조하면, 상기 감광막 패턴(27)에 의해 노출된 금속층(25)을 제1절연막(23)이 노출되도록 식각하여 접촉구를 매운 금속막대(26)를 형성한다. 그 다음 상기 제1절연막(23)의 상부에 금속막대(26)가 완전히 감싸이게 산화규소나 질화규소 또는 BPSG, BSG, USG 및 PSG등 유리재질 절연물질을 제2절연막(29)을 형성한다. 이때 상기 제2절연막(29)의 두께는 제1절연막(23)에 의해 노출된 금속막대(26)의 두께와 같거나 약간 크게 형성한다. 또한, 제1절연막(23)과 제2절연막(29)의 재질이 같을 필요는 없다.2B, the metal layer 25 exposed by the photoresist layer pattern 27 is etched to expose the first insulating layer 23 to form a metal rod 26 filled with contact holes. Next, a second insulating layer 29 is formed of silicon oxide or silicon nitride or a glass insulating material such as BPSG, BSG, USG, and PSG so that the metal rod 26 is completely enclosed on the first insulating layer 23. In this case, the thickness of the second insulating layer 29 is equal to or slightly larger than the thickness of the metal rod 26 exposed by the first insulating layer 23. In addition, the material of the first insulating film 23 and the second insulating film 29 need not be the same.
제2c도를 참조하면, 상기 제2절연막(29)의 상부를 통상의 에치백(etch back)공정에 의해 제거하여 금속막대(26)의 상부를 노출시킨다. 이때 상기 제1 및 제2절연막(23)(29)에 둘러싸인 금속막대(26)가 기판(21)과 상부구조를 수직으로 연결하는 접촉플러그가 된다.Referring to FIG. 2C, the upper portion of the second insulating layer 29 is removed by a normal etch back process to expose the upper portion of the metal rod 26. In this case, the metal rod 26 surrounded by the first and second insulating layers 23 and 29 may be a contact plug that vertically connects the substrate 21 and the upper structure.
상술한 바와 같이 소정기판상에 제1절연막을 형성하고 제1절연막의 소정부분에 접촉구를 형성한 후 상기 접촉구가 매몰되도록 도전층을 형성한다. 그 다음 상기 제1절연막상의 도전층을 제거하여 접촉구 상부에 도전막대를 형성한후 제2절연막을 형성한다. 그후 제2절연막을 에치백하여 도전막대의 상부를 노출시켜 도전체로 완전히 채워진 접촉플러그를 형성한다. 따라서 이 발명은 애스팩트비가 큰 접촉구의 경우에도 접촉구내에 보이드 및 단락등의 결함이 생기지 않도록 도전체로 완전히 채워진 접촉플러그를 얻을수 있다. 또한 이 발명은 동일 반도체 기판상에 서로다른 도전형의 확산영역을 가진 접촉구를 동시에 매몰하여 접촉플러그를 형성하므로 공정이 간단한 이점이 있다.As described above, after forming a first insulating film on a predetermined substrate and forming a contact hole in a predetermined portion of the first insulating film, a conductive layer is formed to bury the contact hole. Next, the conductive layer on the first insulating layer is removed to form a conductive rod on the contact hole, and then a second insulating layer is formed. Thereafter, the second insulating layer is etched back to expose the upper portion of the conductive rod to form a contact plug completely filled with the conductor. Therefore, the present invention can obtain a contact plug completely filled with a conductor so that no defects such as voids and short circuits occur in the contact hole even in the case of a contact hole having a high aspect ratio. In addition, the present invention has a simple process because the contact plug is formed by simultaneously buried contact holes having different conductive diffusion regions on the same semiconductor substrate.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910014939A KR0181961B1 (en) | 1991-08-28 | 1991-08-28 | Method of forming contact plug of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910014939A KR0181961B1 (en) | 1991-08-28 | 1991-08-28 | Method of forming contact plug of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930005119A KR930005119A (en) | 1993-03-23 |
| KR0181961B1 true KR0181961B1 (en) | 1999-04-15 |
Family
ID=19319249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910014939A KR0181961B1 (en) | 1991-08-28 | 1991-08-28 | Method of forming contact plug of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0181961B1 (en) |
-
1991
- 1991-08-28 KR KR1019910014939A patent/KR0181961B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930005119A (en) | 1993-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5607879A (en) | Method for forming buried plug contacts on semiconductor integrated circuits | |
| US5838051A (en) | Tungsten policide contacts for semiconductor devices | |
| US4562640A (en) | Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits | |
| JP3481965B2 (en) | Method of forming integrated circuit submicron contact and structure forming part of semiconductor device | |
| US6603166B2 (en) | Frontside contact on silicon-on-insulator substrate | |
| KR100277377B1 (en) | Formation method of contact/through hole | |
| US5633196A (en) | Method of forming a barrier and landing pad structure in an integrated circuit | |
| US5599736A (en) | Fabrication method for polysilicon contact plugs | |
| JP2720796B2 (en) | Method for manufacturing semiconductor device | |
| JPH03218626A (en) | Wiring contact structure of semiconductor devices | |
| US6495408B1 (en) | Local interconnection process for preventing dopant cross diffusion in shared gate electrodes | |
| JPH11186225A (en) | Formation of tapered contact hole, formation of tapered polysilicon plug and taepred polysilicon plug | |
| JPH08288236A (en) | Method of creating low leakage contact | |
| US6812142B1 (en) | Method and interlevel dielectric structure for improved metal step coverage | |
| KR0181961B1 (en) | Method of forming contact plug of semiconductor device | |
| US6239015B1 (en) | Semiconductor device having polysilicon interconnections and method of making same | |
| US6900118B2 (en) | Method for preventing contact defects in interlayer dielectric layer | |
| US8076235B2 (en) | Semiconductor device and fabrication method thereof | |
| US20040058519A1 (en) | Method for forming bit line contact | |
| KR100539443B1 (en) | Method for forming a metal line in semiconductor device | |
| KR20000072897A (en) | method of manufacturing semiconductor device | |
| KR100191710B1 (en) | Metal wiring method of semiconductor device | |
| KR19990030935A (en) | Contact Forming Method of Semiconductor Device for Reducing Contact Resistance | |
| JPH10223897A (en) | Semiconductor device and manufacturing method thereof | |
| KR100321141B1 (en) | Method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19910828 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19960205 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19910828 Comment text: Patent Application |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19981028 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19981210 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 19981210 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20011107 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20021108 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20031107 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20040331 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20051109 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20061128 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20061128 Start annual number: 9 End annual number: 9 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20081110 |