KR0181839B1 - A clock generator in a plasma display panel television - Google Patents

Abstract

The present invention relates to a clock generator of a plasma display panel television, comprising: a sync signal separator (30) for outputting a horizontal sync signal by separating a sync signal from an input composite video signal; A synchronization signal generator 32 for generating a horizontal synchronization signal according to a control signal that distinguishes NTSC, PAL, and SECAM when no signal is input; Data for selecting one horizontal synchronizing signal according to a control signal for distinguishing a non-signal signal from a horizontal synchronizing signal separated by the synchronizing signal separator 30 and the horizontal synchronizing signal generated by the synchronizing signal generator 32. Selector 34; And a phase locked loop 36 for receiving a horizontal sync signal selected by the data selector 34 and generating a clock synchronized with the horizontal sync signal. According to the present invention, a plasma display panel television is provided. By using the horizontal synchronizing signal for each television system, a clock signal synchronized with the horizontal synchronizing signal can be generated.

Description

Plasma Display Panel TV Clock Generator

Fig. 1A is a waveform diagram showing a horizontal blanking period.

(b) is a waveform diagram showing a vertical blanking period;

2A is a waveform diagram of a composite video signal input to a sync separator.

(b) is a waveform diagram of a composite synchronization signal output from the synchronization separator.

(c) is a waveform diagram of a vertical sync signal output from a sync separator.

3 is a basic block diagram of a phase locked loop.

Fig. 4A is an output waveform diagram of the phase comparator in the synchronization process.

(b) is a graph showing a synchronization holding range and a frequency introduction range.

5 is a block diagram of a clock generator of the plasma display panel television according to the present invention.

* Explanation of symbols for main parts of the drawings

30: sync signal separator 32: sync signal generator

34: data selector 36: phase locked loop

36-1: Phase Comparator 36-2: Loop Filter

36-3: voltage controlled oscillator 36-4: N divider

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator of a plasma display panel television, and more particularly to a clock generator configured to generate a clock synchronized with a horizontal sync signal (H Sync) of each television system in a plasma display panel television. will be.

Plasma Display Panel (hereinafter referred to as PDP) is a flat panel display device using Penning gas for discharge phenomenon. Neon or Helium gas of relatively high air pressure (over 100 Torr) is used. It refers to a display device using a light emitting phenomenon according to the discharge between the narrow electrode coated with the base-based gas as a dielectric material, inherently has a performance suitable for computer terminals, educational systems and the like, and has been practically used as a computer display.

The penning gas is mainly Ne + Xe, Ne + He + Xe, and the reason for using such a mixed gas is that the discharge start voltage can be lowered when the mixed gas is more than one gas component. The discharge start voltage depends on the type of gas, the fanning gas pressure, and the structure and shape of the panel (PASCHEN'S LAW).

PDPs are suitable for large-area display devices and can be colorized, so access to flat wall-mounted televisions has been made.

CRTs, which still hold a strong position in the field of displays, have some major drawbacks. That is, since the CRT itself has a fresco structure, the size of the CRT itself is large, the operating voltage is high, and a voltage of about 10,000 V is required, and a display distortion occurs.

In order to solve such drawbacks of the CRT, flat panel display devices having a matrix structure have been studied.

By adopting the matrix structure, the display distortion is solved, the planar structure is adopted to solve the problem of large size, and the problem of high voltage is solved by not using the high voltage driving electron beam.

Planar display devices include an electroluminescent display device (EL), a light emitting diode display device (LED), and a plasma display panel (PDP), which are active elements, and a liquid crystal display device (LCD) and an electrochromic display, which are passive elements. Device ECD and the like.

Among them, the AC type PDP has been attracting attention as an active memory display panel capable of large display with high resolution.

Looking at the types of PDP can be classified as follows.

First, the PDPs are classified into AC type PDP (indirect discharge type) and DC type PDP (direct discharge type) according to the type of driving voltage applied to the discharge cell.

That is, the AC type PDP is driven by the square wave AC voltage or the pulse voltage, while the DC type PDP is driven by the DC voltage.

In general, the two PDPs have a different structure. In the AC type PDP, the electrode is covered by the dielectric of the glass, whereas in the DC type PDP, the electrode is exposed as it is and a discharge current flows while the discharge voltage is applied.

The AC type PDP has a memory function inside the cell, but the DC type PDP has a merit such that gray scale is added to facilitate image display.

Secondly, there are two types of memory, in which the panel itself stores display information, and a refresh type that reads it out of the panel with a memory of display information and displays it repeatedly on the panel.

Third, according to the shape of the display, the panel has a lattice-shaped electrode, and the intersection of each electrode constitutes a pixel, and the degree of freedom is relatively high, and the dot matrix type that displays characters and figures is more freedom by the relationship between the points. There is a segment type used for small display.

Fourth, according to the type of the addressing mechanism of the display discharge spot, the self-scan PDP and the self-scanning PDP, which is a functionalized panel display that provides the self-scanning function of the discharge point to the matrix type that independently addresses the cells in any place, There is a shift PDP.

PDP has the following advantages over other display devices.

Since PDP does not discharge below a certain voltage (Firing voltage), such a nonlinearity eliminates the limitation on the number of plasma display lines, which enables large-scale production and multiplexing technology for reducing the number of driving circuits.

The large matrix display has a memory function, which is necessary to eliminate high brightness and flicker, while the CRT has a lifespan of 20,000 hours, while the PDP has a lifespan of 50,000 hours.

PDP is suitable for mass production because there is no easily broken parts except glass, and its simple structure makes it possible to manufacture large panels and has a resolution of 100 Line / inch or more due to strong nonlinearity.

Since the discharging material is a gas, the refractive index value is 1, which means that the light is not extinguished by the internal reflection and the external light is not reflected or scattered by the display material.

In addition, unlike other flat panels, the PDP is sealed with glass above 400 ° C, which means that the plasma display can operate even under high humidity conditions or the presence of reactive gases. The change is only caused by the circuit.

In the above, the plasma display panel (PDP) has been described. Next, various television systems and synchronization signals of the television will be described.

The terrestrial broadcasting television system is classified into three methods, NTSC (National Television System Committee), PAL (Phase Alternation by Line), and SECAM (SEquentiel Couleur A Memoire).

Color difference signal transmission method according to color method is amplitude modulation of 3.579545MHz color carrier with quadrature and π / 2 phase modulation for I (In-phase) and Q (Quadrature) color difference signal in MTSC broadcasting, and RY (red signal in PAL method). Luminance signal is modulated by the orthogonal, π / 2 phase modulation, and the RY (intensity modulation) is performed by inverting the polarity of the color carrier at each scan line. D _R ) and BY (D _B ) color difference signals are transmitted in a linear sequential manner by frequency modulation with two different color carriers f _OR = 4.40625 MHz (284 f _H ) and f _OB = 4.25 MHz (272 f _H ) have.

Depending on the method, the scanning player (H), horizontal frequency (KHz), vertical frequency (Hz), images per second, interlaced scanning, aspect ratio of the screen, image modulation, voice modulation (KHz), image band (MHz), The following describes the voice carrier (MHz), channel band (MHz), color carrier (MHz) and the station used.

On the other hand, in general, since a television receiver system disassembles a screen in order from the transmitter side, the receiver side receives it in order and reassembles it. Therefore, the disassembly and assembly speeds of the transmitter side and the receiver side must be completely the same. The frequencies of must be exactly the same, and the starting point of the scan must be exactly the same, which means that the phases must be the same.

Therefore, the transmitting side produces and sends a video signal and simultaneously generates a synchronization signal, so that the starting point of the receiving side scan and the scanning speed are completely coincident with the transmitting side.

If the speed of the vertical scan is not fully synchronized and the speed of the vertical scan is changed, the screen moves up or down, and the speed of the vertical scan is the same as the transmitting side, but if the phase is different, the screen is divided into two and then the top and bottom are changed.

In addition, when the speed of horizontal scanning is different, the screen is scattered sideways and the lines flow to the right or left side. When the horizontal scanning speed is the same but the phases are different, one screen is divided into two and the left and right positions are changed.

The horizontal synchronizing signal H sync and the vertical synchronizing signal V sync are signals that are inserted to match the scanning timing of the transmitting side and the scanning timing of the receiving side, and these synchronization signals are each in the blanking period of the television video signal. Included.

Among the various television systems, the MTSC system will be described with reference to (a) of FIG. 1 showing a waveform diagram showing a horizontal blanking period, and (b) of FIG. 1 showing a waveform diagram showing a vertical blanking period. As shown in (a) of FIG. 1, the horizontal blanking period (H blanking) extends before and after the horizontal sync signal (H sync), so that the video signal is blocked by the receiver reliably during this period, thereby preventing unnecessary images on the screen. This is to prevent the reproduction.

The brightness of the video signal is determined by the amplitude. If the reference is different for each H, the brightness changes. Therefore, the receiver is equipped with a pedestal clamp circuit to maintain a constant feedback level for each H. .

As shown in (b) of FIG. 1, there are five pulses (Serration) in the vertical synchronization, which are at H / 2 intervals because the information of H / 2 is needed since the scanning of the even field starts with H / 2. have.

(A) of FIG. 2 shows a waveform diagram of the composite video signal input to the sync separator, and (b) of FIG. 2 shows a waveform diagram of the composite sync signal output from the sync separator. c) is a waveform diagram of the vertical sync signal output from the sync separator. When a composite video signal as shown in (a) of FIG. 2 is input to the currently used sync separator, the composite sync signal output is performed. At the (Composite Sync Output) terminal, the signal waveform below the black level of the composite video signal from which the video signal is removed is regenerated like the waveform (b) of FIG. 2, and at the vertical sync output terminal, the (c) As shown in the waveform, a vertical sync signal is output at the rising edge of the first pulse within the vertical sync period.

Meanwhile, a phase-locked loop (PLL) to be used in the present invention is to adjust an output frequency and a phase of a phase locked loop to an input frequency and a phase of a phase locked loop by using a feedback signal. In other words, it refers to a circuit that detects a phase difference between an input signal, that is, a standard signal, and the oscillation output of the voltage controlled oscillator to determine the frequency and phase of the voltage controlled oscillator.

The basic operation of the phase-locked loop to ensure that the output frequency always matches the input frequency is as follows.

3 is a basic block diagram of a phase locked loop, which includes a phase comparator 22 (Phase Comparator or Phase Detector: PC), a loop filter 24 (Loop Filter: LF), and a voltage controlled oscillator 26 (Voltage Controlled Oscillator: VCO), and a phase locked rope circuit can be used to create an oscillating circuit with any frequency.

The phase comparator 22 has a function of generating a voltage that can correspond to the phase difference between two input signals and is generally composed of a circuit such as a multiplier demodulator.

The loop filter 24 is a low pass filter that is an important factor for determining the synchronous characteristics or the response characteristics of the phase locked loop as well as the function of removing the high frequency components generated by the phase comparator 22.

The voltage controlled oscillator 26 is an oscillator whose oscillation frequency changes by a control voltage, and its output is added to the phase comparator.

As shown in FIG. 3, V (t) and θ are input signal voltages and their phases, V (t) and θ are output signal voltages and their phases of the voltage controlled oscillator 26, and V (t) are phases. The output voltage of the comparator 22, V (t) is the control voltage of the voltage controlled oscillator 26, F (s) is the voltage transfer function of the loop filter 24.

When V (t) is applied to the phase comparator 22, the phase comparator 22 generates V (t) corresponding to the phase difference between V (t) and V (t), and V (t) is a loop filter 24. The high frequency component is removed, and only the low frequency component becomes V (t), which is the control voltage of the voltage controlled oscillator 25, and V (t) is such that the frequency difference between V (t) and V (t) becomes small. The control oscillator 26 is controlled.

At this time, in the synchronous state, the frequency of the voltage controlled oscillator 26 corresponds to the frequency of the input signal, but the phase difference is equal to the frequency of the voltage controlled oscillator 26 at the oscillation frequency V (t) = 0. It exists as an error voltage (control phase error) for shifting from the oscillation frequency of the voltage controlled oscillator 26 to the frequency of the input signal.

In a phase locked loop, a synchronous process of moving from an asynchronous state to a synchronous state is important.

In the absence of an input signal, the output voltage of phase comparator 22 is zero and the loop is open.

The frequency and phase of the input signal do not coincide with the frequency and phase of the voltage controlled oscillator 26 because at some point in time the input signal is applied and therefore is not in sync.

As a result, the synchronization is approached by the frequency during the pull-in process, and then the synchronization is completed during the phase lock-in process.

When the frequency of the input signal and the voltage controlled oscillator 26 are different, a beetle signal corresponding to the frequency difference between the two signals is generated as the output of the phase comparator 22, and if this beetle frequency is below a certain value, it is synchronized.

(A) of FIG. 4 is an output waveform diagram of the phase comparator in the synchronization process, and (b) of FIG. 4 is a graph showing the synchronization holding range and the frequency introduction range, as shown in (a) of FIG. When the input signal is within the synchronization range of the phase-lock loop, the frequency of the voltage-controlled oscillator approaches the frequency of the input signal in a positive half-cycle, and away from it in the negative half-cycle.

This causes the positive half period to change more slowly than the negative half period, and the overall DC level is positive.

The DC voltage controls the voltage controlled oscillator in the direction of decreasing the frequency difference.

Here, the synchronization holding range (Hold-in range or Lock range) and the frequency introduction range (Pull-in range), which are important factors in the upper right sync loop, can be defined as follows.

Considering that the phase-locked loop is in sync, when the input signal frequency is gradually moved away from the frequency oscillator's frequent oscillation frequency f, if the frequency of the synchronization is set to f and f as shown in Fig. 4B, respectively, (B) is defined as ff.

On the other hand, when the phase-locked loop is in an asynchronous state and the input signal frequency is gradually approached to f, if the synchronized frequencies are f and f as shown in Fig. 4B, respectively, the frequency introduction range B is ff. define.

As described above, television systems have different standards such as NTSC system, PAL system and SECAM system depending on the color system. In order to implement PDP televisions capable of receiving all three types of television system, A clock synchronized with the horizontal synchronizing signal is required.

Accordingly, an object of the present invention is to provide a clock generating apparatus of a plasma display panel television which is devised to satisfy the above necessity and is adapted to generate a clock signal synchronized with a horizontal synchronizing signal in each television system.

Clock generation apparatus of the present invention for achieving the above object,

A sync signal separator for separating a sync signal from an input composite video signal and outputting a horizontal sync signal;

A synchronization signal generator for generating a horizontal synchronization signal according to a control signal that distinguishes NTSC, PAL, and SECAM when no signal is input;

A data selection unit for selecting one horizontal synchronization signal according to a control signal for distinguishing a flow signal from a non-signal among the horizontal synchronization signal separated by the synchronization signal separation unit and the horizontal synchronization signal generated by the synchronization signal generator; And

And a phase locked loop for generating a clock synchronized with the horizontal sync signal selected by the data selector.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

5 is a block diagram of a clock generating apparatus of a plasma display panel television according to the present invention, wherein the clock generating apparatus of the present invention separates a synchronous signal from an input composite video signal to generate a horizontal sync signal (H sync). A synchronization signal separation unit 30 for outputting a; A sync signal generator 32 generating a horizontal sync signal H sync according to a control signal A for distinguishing NTSC, PAL and SECAM when no signal is input; A control signal for distinguishing a non-signal from a horizontal sync signal H sync separated by the sync signal separator 30 and a horizontal sync signal H sync generated by the sync signal generator 32. A data selector 34 for selecting one horizontal synchronizing signal according to B); And a phase locked loop 36 which receives the horizontal sync signal selected by the data selector 34 and generates a clock synchronized with the horizontal sync signal.

Here, the phase locked loop 36 includes: a phase comparator 36-1 for generating a voltage corresponding to a phase difference between two input signals; A loop filter 36-2 which removes the high frequency components generated by the phase comparator 36-1 and converts them into direct current components; A voltage controlled oscillator 36-3 whose oscillation frequency is changed by a control voltage output from the loop filter 36-2; And an N divider 36-4 which divides the output frequency of the voltage controlled oscillator 36-3 by an integer N and sends it to the phase comparator 36-1.

Next, the operation and effects of the present invention configured as described above will be described in detail.

For example, the LM 1881 (Video Sync Separator manufactured by National Semiconductor) can be used to separate the sync signal. When a composite video signal is input to the input terminal of the LM 1881, the output terminal of the LM 1881 is complex. Various signals such as a sync signal, a vertical sync signal, a burst signal, an odd / even field signal (odd / even), and the like are output. Sync) only.

When the composite video signal according to each television system is input to the synchronization signal separation unit 30, a horizontal synchronization signal is output. When a non-signal containing no video information is input, the synchronization signal generation unit 32 performs NTSC, PAL, and SECAM. Generates a horizontal sync signal (H sync) according to the control signal (control signal A) that distinguishes.

In the data selector 34, a flow signal and a non-signal are output from a horizontal sync signal H sync separated by the sync signal separator 30 and a backward flat sync signal H sync generated by the sync signal generator 32. One horizontal synchronization signal is selected according to a control signal B that distinguishes it. When the control signal B indicates a flow signal, the horizontal synchronization signal from the synchronization signal separation unit 30 is selected. On the contrary, when the control signal B indicates no signal, the horizontal synchronization signal from the synchronization signal generator 32 is selected.

The phase lock loop 36 receives the horizontal sync signal selected by the data selector 34 and generates a clock synchronized with the horizontal sync signal. More specifically, the phase comparator 36-1 performs the data selector. Generates a voltage corresponding to a phase difference between the horizontal synchronizing signal from (34) and the input signal from the N divider (36-4) at the next stage, wherein the high frequency component generated by the phase comparator (36-1) When it is removed through the low pass filter of the loop filter 36-2, the DC level is reached, and the oscillation frequency of the voltage controlled oscillator 36-3 is controlled by the control voltage of the DC level output from the loop filter 36-2. Is changed, and the oscillation frequency is divided by the integer N in the N frequency divider 36-4 and then output to the phase comparator 36-1.

As a result, the output terminal of the voltage controlled oscillator 36-3 generates a clock signal that is forcibly synchronized with the horizontal synchronizing signal.

As described above, according to the present invention, a clock signal synchronized with the horizontal synchronizing signal can be generated by using a horizontal synchronizing signal for each television system in implementing a PDP television.

Claims (2)

A sync signal separator 30 for separating a sync signal from an input composite video signal and outputting a horizontal sync signal; A synchronization signal generator 32 for generating a horizontal synchronization signal according to a control signal that distinguishes NTSC, PAL, and SECAM when no signal is input; Data for selecting one horizontal synchronizing signal according to a control signal for distinguishing a non-signal signal from a horizontal synchronizing signal separated by the synchronizing signal separator 30 and the horizontal synchronizing signal generated by the synchronizing signal generator 32. Selector 34; And a phase-locked loop (36) for receiving a horizontal sync signal selected by the data selector (34) and generating a clock signal synchronized with the horizontal sync signal. A phase comparator (36-1) for generating a voltage corresponding to a phase difference between two input signals; A loop filter 36-2 which removes the high frequency components generated by the phase comparator 36-1 and converts them into direct current components; A voltage controlled oscillator 36-3 whose oscillation frequency is changed by a control voltage output from the loop filter 36-2; And an N divider (36-4) which divides the output frequency of the voltage controlled oscillator (36-3) by an integer N and sends it to the phase comparator (36-1). Generating device.