KR0179145B1 - Method of manufacturing semiconductor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for a highly integrated DRAM. The semiconductor device manufacturing method of the present invention for this purpose is to form a field oxide film in the field region of the first conductive substrate defined by the active region and the field region, forming a gate electrode in the active region, both sides of the gate electrode Forming a source / drain region, forming a first insulating layer on the entire surface of the first conductive substrate including the gate electrode, and selectively removing the first insulating layer to expose the drain region to form a first contact hole Forming sidewalls of a second conductive polysilicon sidewall and a second insulating layer on both sides of the first contact hole; forming a bottom electrode in the first contact hole to be connected to the drain region; Forming a dielectric film on the lower electrode, forming a first conductive top electrode on the dielectric film, and including the first conductive top electrode Forming a third contact layer over the first conductive substrate, selectively removing the first and third insulating layers to expose the source region, forming a second contact hole, and a second contact to be connected to the source region And forming a second conductive bit line in the hole.

Therefore, it is possible to reduce the capacitor of the bit line and solve the refresh problem.

Description

Semiconductor device manufacturing method

1 is a cross-sectional view of a conventional semiconductor device manufacturing process.

2 is an equivalent circuit diagram of FIG. (b) is a write operation circuit diagram for (a). (c) is a circuit diagram of a lead-time operation for (a).

3 is a cross-sectional view of a semiconductor device manufacturing process of the present invention.

4 (a) is an equivalent circuit diagram of FIG. (b) is a write operation circuit diagram for (a). (c) is a circuit diagram of a lead-time operation for (a). (d) is an operation circuit diagram for holding data in (a).

* Explanation of symbols for main parts of the drawings

21: n-type substrate 22: field oxide film

23: first insulating film 24: gate electrode

25a: source region 25b: drain region

26 gate sidewall 27 third insulating film

28: first contact hole 29: P-type polysilicon

30: fourth insulating layer 31: storage node

32 dielectric film 33 plate electrode

34: fifth insulating film 35: second contact hole

36: n-type polysilicon

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for a highly integrated DRAM.

Hereinafter, a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a conventional semiconductor device manufacturing process, FIG. 2 (a) is an equivalent circuit diagram of FIG. 1, (b) is a write operation circuit diagram of (a), and (c) is of (a) This is a circuit diagram of the read operation.

As shown in FIG. 1A, a field oxide film 2 is formed in a field region of an n-type substrate 1 defined as a field region and an active region, and the first insulating layer 3 and polysilicon are formed in the active region. The gate electrode 4 is formed by selectively removing the first insulating layer 3 and the polysilicon to expose the n-type substrate 1 by photolithography and etching.

P-type impurity ions are implanted into the entire surface of the n-type substrate 1 on which the gate electrode 4 is formed to form source / drain regions 5a and 5b on both sides of the gate electrode 4, and the n-type substrate 1 A second insulating film is formed on the entire surface, and the second insulating film is removed by an etch back process to form gate sidewalls 6 on both sides of the gate electrode 4.

As shown in FIG. 1B, a third insulating film 7 is formed on the entire surface of the n-type substrate 1, and the third insulating film 7 is exposed to expose the drain region 6b by photolithography and etching. Is selectively removed to form the first contact hole 8.

A storage node 9 is formed in the first contact hole 8 so as to be connected to the drain region 6b, and a dielectric film 10 is formed on the storage node 9. A plate electrode 11 is formed on the dielectric film 10.

As shown in FIG. 1C, a fourth insulating layer 12 is formed on the entire surface of the n-type substrate 1 including the plate electrode 11, and the source region 6a is exposed by photolithography and etching. The fourth insulating layer 12 is removed to form the second contact hole 13 as much as possible.

As shown in FIG. 1D, a P-type polysilicon 14 is formed on the entire surface of the n-type substrate 1, and sidewalls of the P-type polysilicon 14 are formed on both sides of the second contact hole 13 by an etching process. To form.

As shown in FIG. 1E, a fifth insulating layer 15 is formed on the entire surface of the n-type substrate 1, and a sidewall of the fifth insulating layer 15 is formed on the sidewall of the P-type polysilicon 14 by an etching process. Form.

The n-type polysilicon 15, which is a bit line, is formed on the entire n-type substrate 1 including the second contact hole 13.

The operation of the semiconductor device formed as described above is as follows.

As shown in FIG. 2, the n-type polysilicon 16 and the p-type polysilicon 14, which are bit lines, are formed of a diode having a resistance of about 250 kW, and thus a word line at the time of writing. When turned on, current flows from the bit line and is stored in the capacitor through a diode having a resistance of about 250 kV.

During read, when the word line is turned on, a charge in the capacitor forms a current at the base of the npn bipolar transistor, and when the npn bipolar transistor is turned on, a large charge due to Vcc from the sub Charge is delivered to the bit line for reading.

However, such a conventional method of manufacturing a semiconductor device has the following problems.

First, the read operation may be stable by a large current, but because the capacitor itself is small, it causes a refresh problem due to leakage current.

Second, because of the structure of the p-type and n-type junctions of the bit lines and the sidewalls of the n-type polysilicon 16 / sidewall of the n-type polysilicon 16 / contact hole, which is the bitline, The capacitor becomes larger and the operation speed is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and its object is to reduce the capacitor of the bit line and to solve the refresh problem.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a field oxide film in the field region of the first conductive substrate defined by the active region and the field region, forming a gate electrode in the active region, Forming a source / drain region on both sides of the gate electrode, forming a first insulating layer on the entire surface of the first conductive substrate including the gate electrode, and selectively removing the first insulating layer to expose the drain region. Forming a contact hole, forming a second conductive polysilicon sidewall and a second insulating layer sidewall on both sides of the first contact hole, forming a lower electrode in the first contact hole to be connected to the drain region; Forming a dielectric film on the first conductive lower electrode, forming a first conductive top electrode on the dielectric film, and forming a first conductive top electrode Forming a third insulating layer on the entire surface of the first conductive substrate including the upper electrode, selectively removing the first and third insulating layers to expose the source region, and forming a second contact hole, in the source region And forming a second conductive bit line in the second contact hole to be connected.

The semiconductor device manufacturing method of the present invention as described above will be described in more detail with reference to the accompanying drawings.

3 is a cross-sectional view of a semiconductor device manufacturing process of the present invention, FIG. 4 (a) is an equivalent circuit diagram of FIG. 3, (b) is a write-time operation circuit diagram for (a), and (c) is shown in (a). (D) is an operation circuit diagram for holding data for (a).

As shown in FIG. 3A, a field oxide film 22 is formed in a field region of an n-type substrate 21 defined as a field region and an active region, and the first insulating layer 23 and polysilicon are formed in the active region. The gate electrode 24 is formed by selectively removing the first insulating layer 23 and the polysilicon so that the n-type substrate 21 is exposed by photolithography and etching.

P-type impurity ions are implanted into an entire surface of the n-type substrate 21 on which the gate electrode 24 is formed to form source / drain regions 25a and 25b on both sides of the gate electrode 24. A second insulating layer is formed on the entire surface, and the second insulating layer is removed by an etch back process to form gate sidewalls 26 on both sides of the gate electrode 24.

As shown in FIG. 3B, a third insulating layer 27 is formed on the entire surface of the n-type substrate 21, and the third insulating layer 27 is exposed to expose the drain region 25b by photolithography and etching. ) Is selectively removed to form the first contact hole 28.

P-type polysilicon 29 is formed on the entire surface of the n-type substrate 21 including the first contact hole 28 and P-type polysilicon (P-type polysilicon) is formed on both sides of the first contact hole 28 by an etch back process. 29) Form sidewalls.

As shown in FIG. 3 (c), a fourth insulating film 30 is formed on the entire surface of the n-type substrate 21 including the first contact hole 28, and is etched back on the sidewall of the P-type polysilicon 29. Sidewalls of the fourth insulating film 30 are formed.

In addition, a storage node 31 is formed to be connected to the drain region 25b, a dielectric layer 32 is formed on the storage node 31, and a plate is formed on the dielectric layer 32. Plate) An electrode 33 is formed.

As shown in FIG. 3D, a fifth insulating layer 34 is formed on the entire surface of the n-type substrate 21 including the plate electrode 33. The source region 25a is formed by photolithography and etching. The third and fifth insulating layers 27 and 34 are selectively removed to expose the second contact hole 13.

As shown in FIG. 3E, an n-type polysilicon 36 that is a bit line is formed in the second contact hole 35 and on the fifth insulating layer 34.

The operation of the formed semiconductor device as described above is as follows.

As shown in FIG. 4, when the word line is turned on during a write operation, current flows from the bit line and is stored in a capacitor through a PN diode having a resistance of about 250 kV. The charge at the node of the capacitor forms a current at the base of the npn bipolar transistor, a current at the base of the npn bipolar transistor, and a large current from the sub when the npn bipolar transistor is turned on. Is passed to and read from the bitline.

In the case of data retention, the current is formed in the base of the npn bipolar transistor by the charge of the storage node as in the read operation, and the npn bipolar transistor is Continue turning on to charge data in the capacitor.

As explained above, the manufacturing method of the semiconductor element of this invention has the following effects.

First, since data is continuously refreshed even when data is retained, a refresh cycle is not necessary.

Second, since the formation region of the bit line is simplified, the capacitor of the bit line is reduced, so that the operation speed is increased.

Claims (1)

Forming a field oxide film in a field region of a first conductive substrate defined by an active region and a field region, forming a gate electrode in the active region, and forming a source / drain region on both sides of the gate electrode; Forming a first insulating film on the entire surface of the first conductive substrate including a gate electrode, selectively removing the first insulating film to expose the drain region, and forming a first contact hole on both sides of the first contact hole Forming a second conductive polysilicon sidewall and a second insulating layer sidewall, forming a lower electrode in a first contact hole to be connected to the drain region, forming a dielectric layer on the first conductive lower electrode, Forming a first conductive upper electrode on the dielectric film, and forming a third insulating layer on the entire surface of the first conductive substrate including the first conductive upper electrode Forming a second contact hole by selectively removing the first and third insulating layers to expose the source region, and forming a second conductive bit line in the second contact hole to be connected to the source region. Semiconductor device manufacturing method characterized in that it comprises a.