KR0174031B1 - Tft for lcd & the manufacturing method thereof - Google Patents
Tft for lcd & the manufacturing method thereof Download PDFInfo
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- KR0174031B1 KR0174031B1 KR1019940031944A KR19940031944A KR0174031B1 KR 0174031 B1 KR0174031 B1 KR 0174031B1 KR 1019940031944 A KR1019940031944 A KR 1019940031944A KR 19940031944 A KR19940031944 A KR 19940031944A KR 0174031 B1 KR0174031 B1 KR 0174031B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010408 film Substances 0.000 claims abstract description 56
- 239000012535 impurity Substances 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 abstract 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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Abstract
본 발명은 액정표시장치용 박막 트랜지스터 및 그 제조방법에 관한 것으로서, 투명기판상에 반도체층 패턴과 게이트산화막을 순차적으로 형성하고, 상기 게이트산화막상에 제 1 게이트전극과 제 1 필드산화막을 형성한 후, 상기 제 1 게이트전극과 중첩되고 양측이 소정 폭으로 반도체층 패턴과 중첩되는 제 2 게이트전극을 형성하고, 제 2 게이트전극 양측 하부의 반도체층 패턴에 불순물 이온을 주입하여 자기정합적으로 오프셋영역을 갖는 고농도 불순물층을 형성하거나, 제 1 게이트전극 형성 후 저농도로 이온주입하고 제 2 게이트전극 형성 후 고농도로 이온 주입하여 자기정합적으로 LDD 구조를 형성하였으므로, TFT의 온 커런트 감소를 방지하여 소자작동의 신뢰성을 향상시킬 수 있으며, 게이트라인을 제 1 및 제 2 게이트전극의 중첩된 구조로 형성하여 LCD의 신호지연을 방지하여 동화상 표현에 유리하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor for a liquid crystal display device and a method for manufacturing the same, wherein a semiconductor layer pattern and a gate oxide film are sequentially formed on a transparent substrate, and a first gate electrode and a first field oxide film are formed on the gate oxide film. Thereafter, a second gate electrode overlapping the first gate electrode and both sides overlapping the semiconductor layer pattern with a predetermined width is formed, and impurity ions are injected into the semiconductor layer patterns at both lower sides of the second gate electrode to offset the self-alignment. LDD structure was formed by forming a high concentration impurity layer having a region, or ion implantation at a low concentration after the formation of the first gate electrode and ion implantation at a high concentration after the formation of the second gate electrode, thereby preventing on current reduction of the TFT. The reliability of device operation can be improved, and the gate lines are formed in the overlapping structure of the first and second gate electrodes. Prevent a signal delay of over LCD and is advantageous for the moving picture representation.
Description
제1도는 종래 기술에 따른 액정표시장치용 박막 트랜지스터의 단면도.1 is a cross-sectional view of a thin film transistor for a liquid crystal display device according to the prior art.
제2도는 본 발명에 따른 액정표시장치용 박막 트랜지스터의 단면도.2 is a cross-sectional view of a thin film transistor for a liquid crystal display device according to the present invention.
제3도는 본 발명에 따른 액정표시장치용 박막 트랜지스터와 연결되는 게이트라인의 단면도.3 is a cross-sectional view of a gate line connected to a thin film transistor for a liquid crystal display according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 투명기판 2 : 반도체층 패턴1: transparent substrate 2: semiconductor layer pattern
3 : 게이트 산화막 4 : 게이트전극3: gate oxide film 4: gate electrode
5 : 오프셋영역 6 : 고농도 불순물층5: offset region 6: high concentration impurity layer
7 : 필드산화막 8 : 콘택홀7: field oxide film 8: contact hole
9 : 소오스/드레인전극9 source / drain electrodes
본 발명은 액정표시장치(Liquid Crystal Display; 이하 LCD라 칭함)용 박막 트랜지스터(thin film transistor; 이하 TFT라 칭함) 및 그 제조방법에 관한 것으로서, 특히 반도체층 패턴의 채널로 예정되어 있는 부분 상에 제 1 게이트전극을 형성하고, 상기 제 1 게이트전극과 중첩되어 접촉되고 상기 반도체층 패턴과도 소정의 폭으로 중첩되는 제 2 게이트전극을 형성한 후, 자기정합적으로 고농도 불순물층과 오프셋(off-set) 영역이나 저농도 불순물층을 형성하여 TFT의 온커런트 감소 및 신호지연을 방지하여 소자동작의 신뢰성을 향상시킬 수 있는 LCD용 TFT 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor for a liquid crystal display (hereinafter referred to as an LCD) and a method for manufacturing the same, particularly on a portion that is intended as a channel of a semiconductor layer pattern. After forming a first gate electrode, and forming a second gate electrode overlapping and contacting the first gate electrode and overlapping the semiconductor layer pattern with a predetermined width, self-alignment with the high concentration impurity layer is offset (off) The present invention relates to a TFT for LCD and a method of manufacturing the same, which can improve the reliability of device operation by forming a -set) region or a low concentration impurity layer to prevent on current reduction and signal delay of the TFT.
평판표시장치(flat panel display)의 일종인 LCD는 액체의 유동성과 결정의 광학적 성질을 겸비하는 액정에 전계를 가하여 광학적 이방성을 변화시키는 장치로서, 종래 음극선관(Cathode Ray Tube)에 비해 소비전력이 낮고, 부피가 작으며, 대형화 및 고정세화가 가능하여 널리 사용되고 있다.LCD, which is a kind of flat panel display, is a device that changes the optical anisotropy by applying an electric field to a liquid crystal that combines liquidity and optical properties of crystal. Its low volume, small size, large size and high definition make it widely used.
일반적으로 LCD는 화소전극이 형성되어 스위칭 소자와 연결되어 있는 하측 액정기판과 공통전극이 형성되어 있는 상층 액정기판의 사이에 액정이 밀봉되어 있는 형태로 구성된다.In general, LCDs are configured in such a way that liquid crystals are sealed between a lower liquid crystal substrate having pixel electrodes formed therein and connected to a switching element, and an upper liquid crystal substrate having common electrodes formed thereon.
종래 LCD의 제조방법을 살펴보면 다음과 같다.Looking at the manufacturing method of the conventional LCD is as follows.
먼저, 석영재질의 투명기판상에 인듐.틴.옥사이드(indium thin oxide; 이하 ITO라 칭함)로 된 화소전극과 투명전극 패턴을 형성하고, 상기 투명전극 패턴의 단락을 방지하기 위한 보호막과 액정을 배열시키기 위한 배향막을 순차적으로 형성한다.First, a pixel electrode made of indium thin oxide (ITO) and a transparent electrode pattern are formed on a transparent substrate made of quartz, and a protective film and a liquid crystal are formed to prevent a short circuit of the transparent electrode pattern. Alignment films for aligning are formed sequentially.
그다음 상기 배향막에 방향성을 주기 위하여 원통형의 코어에 천이 감겨있는 러빙 롤을 사용하여 러빙을 실시한 후, 보호막과 칼라필터등을 형성하여 하측 액정기판을 완성한다.Then, after rubbing is performed using a rubbing roll wound around a cylindrical core to give the alignment layer a direction, a protective film, a color filter, and the like are formed to complete the lower liquid crystal substrate.
그후, 공통전극을 갖는 상측 액정기판을 형성한 후, 상기 상.하측 액정기판을 일정한 셀겝을 갖도록 스페이서 및 실패턴을 형성하여 봉합시키고, 셀겝에 액정을 주입하고, 밀봉하여 LCD를 완성한다.Thereafter, after forming an upper liquid crystal substrate having a common electrode, the upper and lower liquid crystal substrates are sealed by forming spacers and a failure turn so as to have a constant cell height, and the liquid crystal is injected into the cell cell and sealed to complete the LCD.
또한 통상의 LCD는 사용되는 액정의 종류나 구동 방법 등에 의해 티.엔(Twisted Nematic), 에스.티.엔(Super Twisted Nematic), 강유전성(Ferroelectric) 및 TFT LCD 등으로 구분된다.Conventional LCDs are classified into T. ne (Twisted Nematic), S. T. (Super Twisted Nematic), Ferroelectric, TFT LCD, etc., depending on the type of liquid crystal used and the driving method.
여기서 TFT를 화소 동작의 스위칭 소자로 사용하는 TFT LCD는 다른 종류의 LCD에 비해 응답속도가 빠르고, 넓은 시야각을 가지며, 고정세화 및 고화질화가 가능하여 휴대용 TV나 랩탑 PC 등에 널리 사용되고 있다.TFT LCDs using TFTs as switching elements for pixel operations have a wider response speed than other types of LCDs, have a wide viewing angle, high definition, and high definition, and are widely used in portable TVs and laptop PCs.
이러한 TFT의 종류는 크게 반도체층 패턴인 활성층의 위치에 따른 구조로 구별할 수 있다. 즉 반도체층을 사이에 두고 게이트 전극과 소오스/드레인 전극이 분리되어 있는 스테거드(staggered)형과 반도체층의 일면에 게이트 전극과 소오스/드레인 전극이 형성되어 있는 코플라나(coplanar)형으로 나눈다.The type of TFT can be largely classified into a structure depending on the position of the active layer which is a semiconductor layer pattern. In other words, the semiconductor layer is divided into a staggered type in which the gate electrode and the source / drain electrode are separated, and a coplanar type in which the gate electrode and the source / drain electrode are formed on one surface of the semiconductor layer.
그러나 상기의 TFT LCD는 화소의 일측에 TFT 소자를 형성하여야 하고 소자를 동작시키기 위하여 게이트 버스 및 데이터 버스선을 배치하여야 하므로 화소의 개구율이 떨어지는 문제점이 있다.However, the TFT LCD has a problem in that the aperture ratio of the pixel is lowered because a TFT element must be formed on one side of the pixel and a gate bus and a data bus line must be disposed to operate the element.
제1도는 종래 기술의 일 실시예에 따른 LCD용 TFT의 제조 공정도로서, 오프셋(off set)영역을 갖는 코풀라나형 TFT의 예이다.1 is a manufacturing process chart of an LCD TFT according to an embodiment of the prior art, which is an example of a copulana-type TFT having an offset area.
먼저, 석영재질의 투명기판(1)상에 채널이 되는 반도체층(2) 패턴이 다결정실리콘으로 형성되어 있으며, 상기 구조의 전표면에 게이트산화면(3)이 형성되어 있고, 상기 반도체층(2) 패턴 중앙 부분의 채널로 예정되어 있는 부분 상측의 게이트산화막(3)상에 다결정실리콘으로 된 게이트 전극(4)이 형성되어 있다.First, a pattern of a semiconductor layer 2 serving as a channel is formed of polycrystalline silicon on a transparent substrate 1 of quartz material, and a gate diffusion screen 3 is formed on the entire surface of the structure. 2) A gate electrode 4 made of polycrystalline silicon is formed on the gate oxide film 3 on the upper portion of the portion, which is intended as a channel of the pattern center portion.
또한 상기 게이트전극(4) 하부 양측의 반도체층(2) 패턴에는 게이트전극(4) 하부의 채널영역에 접하는 예정된 폭의 오프셋영역(5)과 N+고농도 불순물층(6)이 연이어 형성되어 있으며, 상기 구조의 전표면에 필드산화막(7)이 도포되어 있다.In addition, an offset region 5 of a predetermined width and N + high concentration impurity layer 6 are formed in the semiconductor layer 2 pattern on both sides of the gate electrode 4 under the gate electrode 4. The field oxide film 7 is applied to the entire surface of the structure.
또한 상기 고농도 불순물층(6)상의 필드산화막(7)과 게이트산화막(3)이 제거되어 상기 고농도 불순물층(6)을 노출시키는 콘택홀(8)들이 형성되어 있으며, 상기 콘택홀(8)을 통하여 상기 고농도 불순물층(6)과 접촉되는 소오스/드레인전극(9)이 금속패턴으로 형성되어 있다.In addition, contact holes 8 are formed to expose the high concentration impurity layer 6 by removing the field oxide layer 7 and the gate oxide layer 3 on the high concentration impurity layer 6. The source / drain electrodes 9 contacting the high concentration impurity layer 6 are formed in a metal pattern.
상기 오프셋영역을 갖는 종래의 TFT는 게이트전극과 드레인전극 말단간에 인가되는 전계를 감소시켜 누설전류를 감소시키기 위한 구조이다.The conventional TFT having the offset region has a structure for reducing leakage current by reducing an electric field applied between the gate electrode and the drain electrode terminal.
상기와 같은 오프셋영역 대신에 엘.디.디(lightly doped drain; 이하 LDD라 칭함) 구조로서 저농도 불순물층을 형성하여도 상기 오프셋영역과 동일한 효과를 얻을 수도 있다.Instead of the offset region described above, even if a low concentration impurity layer is formed as a lightly doped drain (LDD) structure, the same effect as that of the offset region may be obtained.
그러나 상기와 같은 종래의 LCD용 TFT는 누설전류를 감소시키기 위하여 LDD나 오프셋 구조를 갖는데, TFT가 온 상태일 때 LDD나 오프셋 구조가 저항으로 작용하여 온커런트를 감소시켜 소자 동작의 신뢰성을 떨어뜨리고, 신호지연이 발생되며, LCD의 소비 전력을 증가시키는 문제점이 있다.However, the conventional TFT for LCDs has an LDD or offset structure to reduce leakage current. When the TFT is on, the LDD or offset structure acts as a resistance to reduce on current, thereby reducing the reliability of device operation. , Signal delay occurs, and there is a problem of increasing the power consumption of the LCD.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 게이트전극의 상부에 양측단이 반도체층 패턴의 고농도 불순물 영역까지 연장되어 오프셋 또는 LDD의 상측에도 위치하는 별도의 게이트전극을 형성함으로써, TFT의 온커런트의 감소와 신호지연을 방지하여 소자동작의 신뢰성을 향상시키고 LCD의 소자전력을 감소시킬 수 있는 LCD용 TFT를 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a separate gate electrode on both sides of the gate electrode extending up to a high concentration impurity region of the semiconductor layer pattern, which is also located at an offset or above the LDD. Accordingly, the present invention provides a TFT for an LCD that can reduce the on-current of the TFT and prevent signal delay, thereby improving the reliability of device operation and reducing the device power of the LCD.
본 발명의 다른 목적은 반도체층 패턴과 게이트산화막 및 제 1 게이트전극을 형성하고, 제 1 필드산화막을 도포한 후, 상기 제 1 게이드전극과 중첩되고 양단이 소정폭 만큼 연장되어 있는 제 2 게이트전극을 형성하며, 상기 제 2 게이트전극의 양측 하부의 반도체층 패턴에 의해 고농도 불순물층을 자기정합적으로 형성하여 TFT의 온커런트 감소를 방지하여 LCD의 소비 전력을 감소시키고, 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 LCD용 TFT의 제조방법을 제공함에 있다.Another object of the present invention is to form a semiconductor layer pattern, a gate oxide film and a first gate electrode, apply a first field oxide film, and then overlap the first gate electrode and extend the second gate electrode by a predetermined width. And self-aligning a high concentration impurity layer by the semiconductor layer patterns on both lower sides of the second gate electrode to prevent on current reduction of the TFTs, thereby reducing power consumption of the LCD, and reducing process yield and device operation. An object of the present invention is to provide a method of manufacturing a TFT for an LCD that can improve reliability.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 LCD용 TFT의 특징은, 투명기판상에 형성되어 있는 반도체층 패턴과, 상기 구조의 전표면에 형성되어 있는 게이트산화막과, 상기 반도체 패턴에서 채널로 예정되어 있는 부분들 중에서 중앙부분의 상측 게이트산화막상에 형성되어 있는 제 1 게이트전극과, 상기 구조의 전표면에 형성되어 있으며 상기 제 1 게이트전극의 상측을 노출시키는 제 1 필드산화막과, 상기 노출되어 있는 제 1 게이트전극과 접촉되며 상기 제 1 게이트전극 약측의 제 1 필드산화막상에 예정된 폭으로 연장되어 있는 제 2 게이트전극과, 상기 제 2 게이트전극 양측 하부의 반도체층 패턴에 형성되어 있는 고농도 불순물층과, 상기 구조의 전표면에 형성되어 있는 제 2 필드산화막과, 상기 양측의 고농도 불순물층과 접촉되는 소오스/드레인전극을 구비함에 있다.The TFT for LCD according to the present invention for achieving the above object is a semiconductor layer pattern formed on a transparent substrate, a gate oxide film formed on the entire surface of the structure, and from the semiconductor pattern to the channel A first gate electrode formed on an upper gate oxide film in a central portion of the predetermined portions, a first field oxide film formed on an entire surface of the structure and exposing an upper side of the first gate electrode, and the exposure A second gate electrode which is in contact with the first gate electrode and extends in a predetermined width on a first field oxide film on the side of the first gate electrode, and a high concentration formed in a semiconductor layer pattern below both sides of the second gate electrode. Source / de contacted with the impurity layer, the second field oxide film formed on the entire surface of the structure, and the high concentration impurity layers on both sides It is provided as the exhibition pole.
다른 목적을 달성하기 위한 본 발명에 따른 LCD용 TFT 제조방법의 특징은, 투명기판상에 반도체층 패턴을 형성하는 공정과, 상기 구조의 전표면에 게이트산화막을 형성하는 공정과, 상기 반도체층 패턴의 채널로 예정되어있는 부분 상측의 게이트산화막상에 제 1 게이트전극을 형성하는 공정과, 상기 구조의 전표면에 제 1 필드산화막을 형성하는 공정과, 상기 제 1 게이트전극상의 제 1 필드산화막을 제거하여 제 1 게이트전극을 노출시키는 공정과, 상기 제 1 게이트전극과 중첩되어 접촉되며, 상기 제 1 게이트전극 양측의 반도체층 패턴과 예정된 폭으로 중첩되는 제 2 게이트전극을 형성하는 공정과, 상기 제 2 게이트전극 양측 하부의 저농도 불순물층에 불순물 이온을 주입하여 고농도 불순물층을 형성하는 공정과, 상기 구조의 전표면에 제 2 필드산화막을 형성하는 공정과, 상기 고농도 불순물층의 일측 상부의 제 2 및 제 1 필드산화막과 게이트산화막이 순차적으로 제거하여 상기 고농도 불순물층을 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 고농도 불순물층과 접촉되는 소오스/드레인전극을 형성하는 공정을 구비함에 있다.According to another aspect of the present invention, there is provided a method of manufacturing a TFT for an LCD, which includes forming a semiconductor layer pattern on a transparent substrate, forming a gate oxide film on the entire surface of the structure, and forming the semiconductor layer pattern. Forming a first gate electrode on the gate oxide film on the upper portion of the portion scheduled to be a channel of the first channel, forming a first field oxide film on the entire surface of the structure, and forming a first field oxide film on the first gate electrode. Removing and exposing a first gate electrode; forming a second gate electrode overlapping and in contact with the first gate electrode and overlapping a semiconductor layer pattern on both sides of the first gate electrode with a predetermined width; Forming a high concentration impurity layer by injecting impurity ions into the low concentration impurity layers on both lower sides of the second gate electrode, and performing second field oxidation on the entire surface of the structure Forming a contact hole to sequentially remove the second and first field oxide film and the gate oxide film on one side of the high concentration impurity layer to expose the high concentration impurity layer, and through the contact hole. A process of forming a source / drain electrode in contact with a high concentration impurity layer is provided.
본 발명에 따른 LCD용 TFT 제조방법의 다른 특징은, 투명기판상에 반도체층 패턴을 형성하는 공정과, 상기 구조의 전표면에 게이트산화막을 형성하는 공정과, 상기 반도체층 패턴의 채널로 예정되어 있는 부분 상측의 게이트산화막상에 제 1 게이트전극을 형성하는 공정과, 상기 제 1 게이트전극 양측 하부의 반도체층 패턴에 저농도 불순물층을 형성하는 공정과, 상기 구조의 전표면에 제 1 필드산화막을 형성하는 공정과, 사기 제 1 게이트전극상의 제 1 필드산화막을 제거하여 제 1 게이트전극을 노출시키는 공정과, 상기 제 1 게이트전극과 중첩되어 접촉되며, 상기 제 1 게이트전극 양측의 반도체층 패턴과 예정되 폭으로 중첩되는 제 2 게이트전극을 형성하는 공정과, 상기 제 2 게이트전극 양측 하부의 저농도 불순물층에 불순물 이온을 주입하여 고농도 불순물층을 형성하는 공정과, 상기 구조의 전표면에 제 2 필드산화막을 형성하는 공정과, 상기 고농도 불순물층의 일측 상부의 제 2 및 제 1 필드산화막과 게이트산화막이 순차적으로 제거하여 상기 고농도 불순물층을 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 고농도 불순물층과 접촉되는 소오스/드레인전극을 형성하는 공정을 구비함에 있다.Another feature of the TFT manufacturing method for an LCD according to the present invention is a process of forming a semiconductor layer pattern on a transparent substrate, a process of forming a gate oxide film on the entire surface of the structure, and a channel of the semiconductor layer pattern. Forming a first gate electrode on the gate oxide film on the upper portion of the portion, forming a low concentration impurity layer on the semiconductor layer pattern on both lower sides of the first gate electrode, and forming a first field oxide film on the entire surface of the structure. Forming the first gate electrode by removing the first field oxide film on the first gate electrode; and overlapping the first gate electrode to be in contact with the semiconductor layer pattern on both sides of the first gate electrode. Forming a second gate electrode overlapping a predetermined width, and implanting impurity ions into a low concentration impurity layer under both sides of the second gate electrode Forming an impurity layer, forming a second field oxide film on the entire surface of the structure, and sequentially removing the second and first field oxide films and the gate oxide film on one side of the high concentration impurity layer, thereby removing the high concentration impurities. And forming a contact hole exposing the layer, and forming a source / drain electrode in contact with the high concentration impurity layer through the contact hole.
이하, 본 발명에 따른 LCD용 TFT 및 그 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a TFT for an LCD according to the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 LCD용 TFT의 단면도로서, 코플라나형 TFT의 예이며, 장치와 제조방법을 동시에 설명한다.2 is a cross-sectional view of the TFT for LCD according to the present invention, which is an example of a coplanar TFT, and simultaneously describes an apparatus and a manufacturing method.
먼저, 석영이나, 유리 등 투명재질의 투면기판(1)상에 예정된 폭을 갖는 비정질 또는 다결정실리콘으로된 반도체층(2) 패턴을 형성한 후, 상기 구조의 전표면에 게이트산화막(3)을 형성한다.First, a semiconductor layer 2 pattern of amorphous or polysilicon having a predetermined width is formed on a transparent substrate 1 made of quartz, glass or the like, and then a gate oxide film 3 is formed on the entire surface of the structure. Form.
그다음 상기 반도체층(2) 패턴에서 채널로 예정되어 있는 부분의 게이트산화막(3)상에 다결정실리콘층 패턴으로된 제 1 게이트전극(4A)을 형성한 후, 상기 구조의 전표면에 제 1 필드산화막(7A)을 형성하고, 상기 제 1 게이트전극(4A) 상측의 제 1 필드산화막(A)을 제거하여 제 1 게이트전극(4A)의 상부를 노출시키는 콘택홀을 형성한다.Then, a first gate electrode 4A having a polysilicon layer pattern is formed on the gate oxide film 3 in the portion of the semiconductor layer 2 pattern that is supposed to be a channel, and then a first field is formed on the entire surface of the structure. An oxide film 7A is formed, and the first field oxide film A over the first gate electrode 4A is removed to form a contact hole exposing the upper portion of the first gate electrode 4A.
그후, 상기 제 1 게이트전극(4A)의 상부에 제 2 게이트전극(4B)을 형성하되, 상기 제 2 게이트전극(4B)은 상기 제 1 게이트전극(4A)과 접촉되고, 상기 반도체층(2) 패턴과는 오프셋영역으로 예정되어 있는 폭만큼 중첩되는 제 2 게이트전극(4B)을 다결정실리콘이나 금속패턴으로 형성한다.Thereafter, a second gate electrode 4B is formed on the first gate electrode 4A, and the second gate electrode 4B is in contact with the first gate electrode 4A, and the semiconductor layer 2 ) And the second gate electrode 4B overlapping with the predetermined width as the offset region is formed of polycrystalline silicon or a metal pattern.
그다음 상기 제 2 게이트전극(4B) 양측 하부의 반도체층(2) 패턴에 As, P 또는 POCl3등과 같은 N형 또는 P형 불순물을 이온 주입하여 고농도 불순물층(6)을 형성한다. 이때 상기 고농도 불순물층(6)은 제 2 게이트전극(4B)을 마스크로 하여 자기정합적으로 형성되어, 상기 고농도 불순물층(6) 안측의 제 2 게이트전극(4B)과 중첩되는 부분에는 진성 다결정실리콘층의 오프셋영역(5)으로 남게 된다.Next, a high concentration impurity layer 6 is formed by ion implanting N-type or P-type impurities such as As, P, or POCl 3 into the semiconductor layer 2 patterns on both lower sides of the second gate electrode 4B. At this time, the highly doped impurity layer 6 is formed in a self-aligning manner using the second gate electrode 4B as a mask, and an intrinsic polycrystal is formed at a portion overlapping with the second gate electrode 4B on the inner side of the heavily doped impurity layer 6. The offset region 5 of the silicon layer remains.
또한 상기 제 1 게이트전극(4A)을 형성한 후, 상기 반도체층(2) 패턴에 제 1 게이트전극(4A)을 마스크로 저농도 이온주입하여 자기정합적으로 LDD 구조를 형성할 수도 있다.In addition, after the first gate electrode 4A is formed, the LDD structure may be formed in a self-aligned manner by implanting low concentration ions into the semiconductor layer 2 pattern using the first gate electrode 4A as a mask.
그후, 상기 구조의 전표면에 제 2 필드산화막(6)을 형성하고, 상기 고농도 불순물층(6) 일측 상부의 제 2 및 제 1 필드산화막(7B),(7A)을 순차적으로 제거하여 고농도 불순물층(6)의 일측을 노출시키는 콘택홀(8)을 형성하고, 상기 콘택홀(8)을 통하여 고농도 불순물층(6)과 접촉되는 소오스/드레인전극(9)을 Ti, Cr 또는 Al 등의 금속패턴으로 형성한다.Thereafter, the second field oxide film 6 is formed on the entire surface of the structure, and the second and first field oxide films 7B and 7A on one side of the high concentration impurity layer 6 are sequentially removed to remove the high concentration impurity. A contact hole 8 is formed to expose one side of the layer 6, and the source / drain electrode 9 contacting the high concentration impurity layer 6 through the contact hole 8 is formed of Ti, Cr, Al, or the like. It is formed by a metal pattern.
상기와 같은 TFT는 두 개의 중첩되어 있는 게이트전극에 의해 채널과 고농도 불순물층의 사이에 자기정합적으로 오프셋영역이나 LDD 구조가 형성되어 TFT의 온커런트 감소를 방지한다.The TFT is formed by self-aligning an offset region or an LDD structure between the channel and the highly doped impurity layer by two overlapping gate electrodes, thereby preventing the oncurrent reduction of the TFT.
또한 제3도에 도시되어 있는 바와 같이, 게이트전극들이 연결되어 게이트라인을 제 1 및 제 1 게이트전극(4A),(4B)이 중첩되도록 형성하여 게이트라인의 신호 지연을 방지할 수 있다.In addition, as shown in FIG. 3, gate electrodes may be connected to form gate lines to overlap the first and first gate electrodes 4A and 4B, thereby preventing signal delay of the gate lines.
이상에서 설명한 바와 같이, 본 발명에 따른 LCD용 TFT 및 그 제조방법은 투명기판상에 반도체층 패턴과 게이트산화막을 순차적으로 형성하고, 상기 게이트산화막상에 제 1 게이트전극과 제 1 필드산화막을 형성한 후, 상기 제 1 게이트전극과 중첩되고 오프셋영역으로 예정되어 있는 폭 만큼 양측이 반도체층 패턴과 중첩되는 제 2 게이트전극을 형성하고, 제 2 게이트전극 양측 하부의 반도체층 패턴에 불순물 이온을 주입하여 자기정합적으로 오프셋영역을 갖는 고농도 불순물층을 형성하거나, 제 1 게이트전극 형성 후 저농도로 이온주입하고 제 2 게이트전극 형성 후 고농도로 이온주입하여 자기정합적으로 LDD 구조를 형성하였으므로, TFT의 온 커런트 감소를 방지하여 소자동작의 신뢰성을 향상시킬 수 있으며, 게이트라인을 제 1 및 제 2 게이트전극의 중첩된 구조로 형성하여 LCD의 신호지연을 방지하여 동화상 표현에 유리한 이점이 있다.As described above, the LCD TFT and the method of manufacturing the same according to the present invention sequentially form a semiconductor layer pattern and a gate oxide film on a transparent substrate, and form a first gate electrode and a first field oxide film on the gate oxide film. Thereafter, a second gate electrode overlapping the first gate electrode and having a width predetermined as an offset region is formed on both sides of the second gate electrode, and impurity ions are implanted into the semiconductor layer patterns below both sides of the second gate electrode. To form a self-aligned LDD structure by forming a highly doped impurity layer having an offset region by self-alignment or by implanting ions at a low concentration after forming the first gate electrode and by implanting ions at a high concentration after forming the second gate electrode. It is possible to improve the reliability of device operation by preventing on current reduction and to reduce the gate lines of the first and second gate electrodes. To form a nested structure to prevent a signal delay of the LCD has a favorable advantage for the moving picture representation.
Claims (9)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101056229B1 (en) * | 2009-10-12 | 2011-08-11 | 삼성모바일디스플레이주식회사 | An organic light emitting display device comprising a thin film transistor, a method of manufacturing the same, and a thin film transistor |
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1994
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101056229B1 (en) * | 2009-10-12 | 2011-08-11 | 삼성모바일디스플레이주식회사 | An organic light emitting display device comprising a thin film transistor, a method of manufacturing the same, and a thin film transistor |
| US8963214B2 (en) | 2009-10-12 | 2015-02-24 | Samsung Display Co., Ltd. | Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device have the thin film transistor |
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