KR0173964B1 - Method of fabricating a power semiconductor device with latch-up control structure - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a power semiconductor device having a latch-up control structure, comprising using a oxide film pattern (15) as a mask and implanting two impurity ions with different energy. Through this, a latch-up control impurity injection layer 20 and a source junction impurity injection layer 22 having different depths are formed, and an ohmic contact impurity injection layer 26 is formed through the oxide film pattern 15. can do. In particular, the latch-up control impurity implantation layer 20 and the ohmic contact impurity implantation layer 26 may be simultaneously formed by one ion implantation process, thereby reducing the number of ion implantation processes using expensive equipment. Can be.

Description

Manufacturing Method of Power Semiconductor Device with Latch-up Control Structure

1 is a cross-sectional view showing the structure of a conventional power semiconductor device.

2A to 2I are sectional views showing the process steps of manufacturing a power semiconductor device by a conventional manufacturing method.

3A to 3H are cross-sectional views showing the process steps of manufacturing the power semiconductor device shown in FIG. 2 by the method according to the embodiment of the present invention.

4A and 4B show a cross-sectional view showing a partial structure of the power semiconductor device manufactured by FIG. 3 and a curve showing a concentration distribution of dopants of impurity implantation regions in the horizontal direction on the surface of the semiconductor substrate. .

5A and 5B are cross-sectional views showing a partial structure of the power semiconductor device manufactured by FIG. 3 and a curve showing the concentration distribution of dopants of impurity injection regions in the vertical direction from the source region to the epitaxial layer. Figure shown.

6A and 6B are cross-sectional views showing a partial structure of the power semiconductor device manufactured by FIG. 3, and a curve showing the concentration distribution of dopants of impurity injection regions in the vertical direction from the cathode contact region to the epitaxial layer. Figure.

* Explanation of symbols for main parts of the drawings

12 semiconductor substrate 13 buffer layer

14 semiconductor layer (epitaxial layer) 15 gate oxide film

16 gate polysilicon film 19 p ^- type wall region

24 impurity region for latch up control 25 source junction region

27: cathode contact region 28: insulating film

29: metal electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of power semiconductor devices, and more particularly, to a method of manufacturing a power semiconductor device having an impurity implantation structure for controlling latch-up.

As is known, in gated transistors, especially n-channel gated transistors, among power semiconductor devices, latch-up works as a major cause of the limitation of the magnitude of the operable current.

That is, p in the gated transistor having a thyristor ^structure if the upper bottom hole current (hole current) flowing to the formed n ⁺ type source junction regions in the well (well) increases, the ^p-resistance of the well This causes a voltage difference between the well and the source junction region. When the voltage difference is higher than a certain value, the parasitic npnp thyristor operates. When this thyristor is operated, the result is that the pnp transistor is energized, and even if the gate voltage is cut off, the pnp transistor does not turn off, but rather the current flows through the pnp transistor. Will increase. This operation raises the temperature of the gated transistor and eventually destroys it. This series of processes is a latchup phenomenon.

In order to prevent the latch-up phenomenon described above, it is necessary to increase the operable current. In other words, it is essential to make the resistance of the p ⁻ well region under the n ⁺ type source junction region as small as possible to reduce the voltage difference therebetween. There have been various attempts to reduce the resistance, and the most widely used structure is the formation of p ⁺ type wells by ion implantation in the p ^- well region, and a conventional semiconductor device having such a structure is shown in FIG. Is shown.

Referring to FIG. 1, a positive electrode (not shown) formed on the high-concentration p ⁺ -type formed on the semiconductor substrate 12 and the high-concentration n ⁺ -type buffer layer 13 is formed on the n ⁺ -type buffer layer 13, which is installed The low concentration n ⁻ type semiconductor layer 14 is formed by epitaxial growth. The gate polysilicon film 16 is formed on the n ⁻ type semiconductor layer 14 with the gate oxide film 15 interposed therebetween. In addition, the p ⁻ well region 15 is formed on the surface of the n ⁻ type semiconductor layer 14 between the gate polysilicon layer 16 by impurity ion implantation and thermal diffusion, and the latch up does not occur. The high concentration p ⁺ type well region 30 provided for the purpose extends to a portion of the n ⁻ type semiconductor layer 14 while penetrating the central portion of the p ⁻ well region 15 by impurity ion implantation and thermal diffusion. In addition, an n ⁺ type source junction region 25 is formed on the surfaces of the p ⁻ type well region 19 and the p ⁺ type well region 30 using a source forming mask, and the n ⁺ type source. A metal electrode 29 is formed on the part of the junction region 25 and on the surface of the n ⁺ type well region 30 as a cathode. Reference numeral 28 is a PSG film 28 provided for electrical insulation between the metal electrode 29 and the gate polysilicon film 16.

The gated transistor having the above-described structure is formed of the current flowing under the source junction region 25 by the p ⁺ type well region 30 formed through the p ⁻ type well region 19. Since the size can be limited, that is, the resistance becomes small by the p ⁺ well region 30, the voltage difference between the source junction region 25 and the well regions 19 and 30 can be reduced. Latch up can be improved.

However, in the method of manufacturing the gated transistor described above, in order to form the p ⁺ well region 30, a window of about 2-3 mu m or more must be formed on the semiconductor substrate for each cell. There is a problem in that manufacturing is required and thereby the chip size (chip size) becomes large. In addition, there is a problem that the manufacturing process of the gated transistor described above is complicated because additional processes according to the mask fabrication have to be performed.

In order to solve these problems, a power semiconductor device having a new structure and a manufacturing method thereof have been developed by the present inventors and already filed on March 15, 1996 (Patent Application No. 96-6994).

Processes according to the above-described method for manufacturing a power semiconductor device are shown in FIGS. 2A to 2I.

2A to 2I are cross-sectional views illustrating a method of manufacturing the power semiconductor device of FIG. 2 according to an embodiment of the present invention, and the same reference numerals are used for components having the same functions as those shown in FIG. Staging.

Referring to FIG. 2A, on the high concentration p ⁺ type semiconductor substrate 12, phosphorus (P) is used as a dopant, and a high concentration and thin n ⁺ type buffer layer 13 is formed by epitaxial growth. do. Further, on the n ⁺ type buffer layer 13, a low concentration n ⁻ type semiconductor layer 14 having phosphorus (P) as a dopant is formed by epitaxial growth.

Subsequently, an oxide film, a polysilicon film, and a photosensitive film are sequentially formed on the n ⁻ type semiconductor layer 14, and the photoresist film is patterned by a well-known photographic process using a gate forming mask to define a well region. By the etching process using the photoresist pattern 17 formed by patterning the photoresist as a gate forming mask, as shown in FIG. 2B, the polysilicon film and the oxide film are sequentially removed to form the semiconductor layer 14. The gate oxide film 15 and the gerrit polysilicon film 16 are formed on the substrate.

The gate polysilicon film 16 must be conductive in order to function as a gate electrode, which can be formed by in-situ techniques well known in the art, and is also followed by the application of the polysilicon film. It may be formed by impurity injection.

After removal of the photoresist pattern 17, a low concentration of p ⁻ -type impurity ions are implanted using the gate polysilicon layer 16 as a mask for forming a well, and as shown in FIG. 2C, the semiconductor layer ( A p ⁻ type impurity implantation layer 18 formed by implanting impurity ions into 14 is formed. Subsequently, a thermal diffusion process is performed to diffuse the p ⁻ type impurity implantation layer 18 so that a p ⁻ type well 19 is formed as shown in FIG. 2D.

On the other hand, although not shown in the drawing, as shown in FIG. 2B, only the polysilicon film is removed in the etching process to form the patterned gate polysilicon film 16, that is, the lower film of the polysilicon film. After the oxide film is not removed, the impurity implantation layer 18 may be formed by performing an ion implantation process. In this case, the surface of the semiconductor layer 14 is not damaged even if the ion implantation process is performed. Subsequently, the oxide film exposed by the gate polysilicon film 16 may be removed to form the gate oxide film 15.

Referring to FIG. 2E, the source junction forming mask is coated with a nitride film on the surface of the gate polysilicon film 16 and the exposed semiconductor substrate, as shown in FIG. 2F, and then patterned the nitride film. The impurity implantation process is performed using the nitride film pattern 21 and the gate polysilicon film 16 formed at this time as a mask used to form the impurity implantation region for latch-up control. That is, when p-type impurity ions are implanted into the well 19 using the mask, the p-type impurity implantation layer 20 is formed at a predetermined depth in the well 19.

Subsequently, if a high concentration of n ⁺ type impurity ions using the mask as a mask for the source junction formation injection have the proper energy, as illustrated in the 2f also, the n ⁺ doping layer 22 is the p It is formed between the type impurity injection layer 20 and the surface of the semiconductor substrate.

In this embodiment, the n ⁺ type impurity injection layer 22 is formed after the p type impurity injection layer 20 is formed, but the n ⁺ type impurity injection layer 22 is formed first, and then the The same result can be obtained even if the p-type impurity injection layer 20 is formed.

Subsequently, when the nitride film pattern 21 is removed and a thermal diffusion process is performed, impurity ions in the n ⁺ type impurity injection layer 22 and the p type impurity injection layer 20 are diffused to form n ⁺ type source junctions, respectively. A region 25 and a latch-control impurity diffusion region 24 are formed as shown in FIG. 2G. At this time, the impurity diffusion region 24 covers the lower portion of the n ⁺ type source junction region 25 in the p ⁻ type well 19 by appropriately adjusting the thermal diffusion time and temperature. It does not extend to the channel in the lower part of 15).

Since the p-type impurity diffusion region 24 also has a higher impurity concentration than the p ⁻ type well 19, the latch-up phenomenon can be prevented.

Also, a high concentration of p ⁺ -type impurity ions are implanted using the gate polysilicon film 16 as a mask to show a p ⁺ -type impurity implantation layer 26 on the surface of the impurity diffusion region 24 in FIG. 2h. After forming as described above, the impurity ions of the impurity injection layer 26 are diffused by a subsequent heat treatment process to form the cathode ohmic contact region 27. In addition, the cathode ohmic contact region 27 may be formed by a separate heat treatment process as described above, but may be formed simultaneously with the formation of the PSG film in the subsequent application process of the PSG film. It is capable of using the gate polysilicon film 16 as a mask for a cathode ohmic contact is formed to form the region 27 on the surface of the p-type impurity diffusion region 24, the n ⁺ type source junction region (25 This is because the impurity concentration of c) is relatively higher than the impurity concentration of the p ⁺ type cathode ohmic contact region 27.

Subsequently, the PSG film 28 is coated and patterned on the semiconductor substrate including the gate polysilicon film 16 to expose the cathode ohmic contact region 27 and a part of the surface of the source junction region 25. A contact hole is formed, and then a metal electrode 29 is formed on the PSG film 28 as shown in FIG. 2I while filling the contact hole. The PSG film 29 is provided to prevent electrical contact of the gate polysilicon film 16 with the metal electrode 29. After the formation of the PSG film 29, a reflow process is performed to carry out ion implantation through the exposed surface of the semiconductor layer 14 to form the first impurity implantation layer 18. It can compensate for surface damage that occurs when. That is, when the reflow process is performed at a high temperature for about 20-30 minutes, the surface of the semiconductor layer 14 damaged during ion implantation is smooth again.

However, this method uses four expensive ion implanters to form the wells 19, the impurity diffusion region 24 for latch-up control, the source junction region 25 and the cathode ohmic contact region 27. Since not only the ion implantation but also the respective masks are required for the ion implantation, there is a problem in that the production cost is increased and the complicated processes required for the mask fabrication are added.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a power semiconductor device having a simple manufacturing process while improving latch-up as proposed to solve the above-mentioned problems.

Another object of the present invention is to provide a method for manufacturing a power semiconductor device that can improve latchup without using a p ⁺ type well.

According to one aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming a second conductive buffer layer doped with a high concentration of impurities on a first conductive semiconductor substrate doped with a high concentration of impurities; Forming a low-concentration second conductive semiconductor layer by epitaxial growth on the buffer layer; Forming a polysilicon film on the semiconductor layer with an oxide film interposed therebetween; Forming a photoresist pattern on the polysilicon film to define a well region; Selectively removing the polysilicon film using the photosensitive film pattern as a mask to form a gate polysilicon film; Removing the photoresist pattern, and implanting impurity ions into the well region using the gate polysilicon layer as a mask to form a first conductivity type well; Selectively removing an oxide film on the surface of the well defined by the gate polysilicon film to form an oxide film pattern; Implanting a high concentration of impurity ions using the gate polysilicon film and the oxide film pattern as a mask to form a first impurity implantation layer of a second conductivity type in the well region; The impurity ion is implanted using the gate polysilicon film and the oxide film pattern as a mask to form a second impurity injection layer of a first conductivity type formed through a window of the oxide film pattern and a first conductive film formed through the oxide film pattern. Simultaneously forming a third impurity injection layer of a type into said well, said third impurity injection layer being formed below said first impurity injection layer and above said second impurity injection layer; After removing the oxide film pattern, forming a metal electrode on the well by sandwiching an insulating film between the gate polysilicon film so as not to be in electrical contact with the gate polysilicon film; Subsequently, heat treatment is performed to diffuse ions of the first, second, and third impurity implantation layers to form source junction regions, latch diffusion control impurity diffusion regions, and ohmic contact regions.

In this method, the first conductivity type is p type and the second conductivity type is p type.

According to another aspect of the present invention, there is provided a method of manufacturing a power semiconductor device, comprising: forming a buffer layer of a second conductive type doped with a high concentration of impurities on a semiconductor substrate of the first conductive type doped with a high concentration of impurities; Forming a low-concentration second conductive semiconductor layer by epitaxial growth on the buffer layer; Forming a polysilicon film on the semiconductor layer with an oxide film interposed therebetween; Forming a photoresist pattern on the polysilicon film to define a well region; Selectively removing the polysilicon film and the oxide film using the photosensitive film pattern as a mask to form a gate polysilicon film; Removing the photoresist pattern, and implanting impurity ions into the well region using the gate polysilicon layer as a mask to form a first conductivity type well; Forming an oxide film pattern on a surface of the well defined by the gate polysilicon film to define a source junction region; A first conductive type latch up control impurity implantation layer formed through the window of the oxide layer pattern by using the gate polysilicon layer and the oxide layer pattern as a mask and implanting impurity ions, and a first conductive layer formed through the oxide layer pattern Forming an ohmic contact impurity implantation layer of the same type in said well, said ohmic contact impurity implantation layer being formed below said latch-up control impurity implantation layer; Using the gate polysilicon film and the oxide film pattern as a mask and implanting a high concentration of impurity ions to form a second conductive source impurity implantation layer in the well region; After removing the oxide film pattern, forming a metal electrode on the well by sandwiching an insulating film between the gate polysilicon film so as not to be in electrical contact with the gate polysilicon film; Subsequently, heat treatment is performed to diffuse the ions of the impurity injection layers to form a source junction region, an impurity diffusion region for latch-up control, and an ohmic contact region.

Referring to FIG. 3F and FIG. 3G, the method of manufacturing the novel power semiconductor device of the present invention includes using the oxide film pattern 15 as a mask and injecting two impurity ions with different energies. Through the window of the oxide film pattern, a latch-up control impurity injection layer 20 and a source junction impurity injection layer 22 having different depths are formed, and through the oxide film pattern 15, an ohmic contact impurity injection layer ( 26). In particular, the latch-up control impurity implantation layer 20 and the ohmic contact impurity implantation layer 26 may be simultaneously formed by one ion implantation process, thereby reducing the number of ion implantation processes using expensive equipment. have.

3A to 3H are cross-sectional views showing a method of manufacturing a device on a power peninsula having a latch-up control structure according to an embodiment of the present invention, and have the same functions as the components shown in FIGS. 2A to 2I. The same reference numerals are given to the components having the same reference numerals.

Referring first to FIG. 3A, on the high concentration p ⁺ type semiconductor substrate 12, phosphorus (P: phosphorous) is used as a dopant, and the high concentration and thin n ⁺ type buffer layer 13 is formed by epitaxial growth. Is formed. Further, on the n ⁺ type buffer layer 13, a low concentration n ⁻ type semiconductor layer 14 having phosphorus (P) as a dopant is formed by epitaxial growth.

Subsequently, an oxide film 15, a polysilicon film 16, and a photosensitive film 17 are sequentially formed on the n ⁻ type semiconductor layer 14, and the photosensitive film is formed by a well-known photographic process using a mask for forming a gate. The well region is defined by patterning 17). By the etching process using the photoresist pattern 17 formed by patterning the photoresist as a gate forming mask, as shown in FIG. 3B, the polysilicon film is selectively removed to form a gate on the oxide film 15. The polysilicon film 16 is formed.

The gate polysilicon film 16 must be conductive in order to function as a gate electrode, which can be formed by in-situ techniques well known in the art, and is also followed by the application of the polysilicon film. It may be formed by impurity injection.

After removal of the photoresist pattern 17, a low concentration of p ⁻ -type impurity ions are implanted using the gate polysilicon layer 16 as a mask for forming a well, and as shown in FIG. 3C, the semiconductor layer ( A p ⁻ type impurity implantation layer 18 formed by implanting impurity ions into 14 is formed. Subsequently, a thermal diffusion process is performed to diffuse the p ⁻ type impurity implantation layer 18 so that a p ⁻ type well 19 is formed as shown in FIG. 3D.

Referring to FIG. 3E, the oxide film 15 is selectively removed by a selective etching process using a mask for forming impurity regions for source bonding and latch-up control.

Subsequently, as shown in FIG. 3F, an impurity implantation process using the selectively removed oxide film pattern 15 as a mask is performed to form an impurity implantation layer 22 for forming a source junction portion. For example, an impurity implantation layer 22 is formed at a predetermined depth in the well 19 region by implanting a high concentration of n ⁺ -type impurities.

3G, an impurity implantation process using the oxide film pattern 15 as a mask is performed, so that the latch-up control impurity layer 20 and the cathode ohmic contact impurity layer 26 are formed at the same time. That is, the p ⁻ type well 19 is implanted with a high concentration of p type impurity implantation having a higher impurity concentration than the on concentration, so that the latch injection control impurity injection layer 20 and the cathode ohmic contact are disposed at a predetermined depth in the well 19 region. The impurity layer 26 is formed at the same time. Since the impurity implantation process shown in FIG. 3G is performed with higher energy than the impurity implantation process shown in FIG. 3F, the latch-up control impurity implantation layer 20 and the cathode ohmic contact impurity implantation layer 26 are It is formed deeper than the source junction impurity implantation layer 22, and the cathode ohmic contact impurity implantation layer 26 is deeper than the source junction impurity implantation layer 22 and the latchup control impurity implantation layer 26. It is formed at a thinner depth than).

In this embodiment, the p-type impurity implantation layer 20 is formed after the formation of the n ⁺ type impurity implantation layer 22. However, the p-type impurity implantation layer 20 is first formed and then the n-type impurity implantation layer 22 is formed. ^The same result can be obtained also by forming the ⁺ type impurity injection layer 22.

Subsequently, when the thermal diffusion process is performed, the impurity ions in the impurity implantation layers 22, 20, and 26 are simultaneously diffused, so that the n ⁺ type source junction region 25, the latch-control impurity diffusion region 24, and the cathode ohmic contact are respectively. The region 27 is formed as shown in FIG. 3h. At this time, the impurity diffusion region 24 covers the lower portion of the n ⁺ type source junction region 25 in the p ⁻ type well 19 by appropriately adjusting the thermal diffusion time and temperature. It does not extend to the channel in the lower part of 15). This thermal diffusion process can be performed simultaneously with the subsequent formation of the PSG film.

Since the p-type impurity diffusion region 24 also has a higher impurity concentration than the p ⁻ type well 19, the latch-up phenomenon can be prevented.

That is, since the impurity diffusion region 24 for latch-up control is formed under the n ⁺ type source junction region 25, the resistance value under the source junction region 25 becomes small, and the p-type impurity is reduced. The voltage difference between the diffusion region 24 and the n ⁺ type source junction region 25 is reduced to prevent the parasitic npnp thyristors from operating.

Subsequently, the oxide layer 26 exposed by the gate polysilicon layer 16 is removed, and then the PSG layer 28 is coated and patterned on the semiconductor substrate including the gate polysilicon layer 16 to form the cathode. A contact hole exposing not only an ohmic contact region 27 but also a part surface of the source junction region 25 is formed, and then a metal electrode 29 is applied onto the PSG film 28 while filling the contact hole. A power semiconductor device having a structure as shown in FIG. 3h is formed. The PSG film 29 is provided to prevent electrical contact of the gate polysilicon film 16 with the metal electrode 29. In addition, after the PSG film 29 is formed, a reflow process is performed to carry out ion implantation through the exposed surface of the semiconductor layer 14 to form the impurity implantation layers 22 and 20. It can compensate for surface damage that occurs when. That is, when the reflow process is performed at a high temperature for about 20-30 minutes, the surface of the semiconductor layer 14 damaged during ion implantation is smooth again.

4A is a cross-sectional view taken along the channel layer of the power semiconductor device manufactured by the above-described method, and FIG. 4B shows the concentration of the dopant in the impurity injection regions in the horizontal direction (arrow direction) on the surface of the power semiconductor substrate. It is a figure which shows a curve. Referring to FIG. 4B, it is shown that the p-type impurity concentration is not increased on the surface of the channel layer. That is, it is shown that the p-type impurity diffusion region 24 for latch-up control is not formed along the boundary of the source junction region 25 to the channel layer.

FIG. 5A is a cross-sectional view taken vertically from the surface of the source junction region 25 of the power semiconductor device, and FIG. 5B shows a region in which a p-type dopant is diffused directly below the source junction region 25. The curve is shown. As shown in FIG. 4B, a p-type dopant having a concentration higher than that of the p ⁻ type well 19 is diffused under the source junction region 25, so that the hole current flowing through the region can be reduced. Shows the structure.

FIG. 6A is a cross-sectional view taken vertically from the surface of the cathode ohmic contact region 27 of the power semiconductor device. FIG. 6B is a high concentration of ohmic contact with the metal electrode 29 on the cathode contact surface. P ⁺ dopants are spreading.

According to the above-described method, the cathode ohmic contact portion and the latch-up control impurity diffusion layer can be simultaneously formed by one ion implantation using one mask, and the source junction region can also be formed by using the same mask. The process is simplified. In particular, the production cost of the semiconductor device can be lowered by reducing the number of ion implantation processes that require the use of expensive equipment.

In addition, according to the method of the present invention described above, it is not necessary to form the p ⁺ type well through the p ⁻ type well to the semiconductor layer in order to control the latch up, so that the latch up is generated without forming the p ⁺ type well. Can be prevented.

Moreover, since the method of the present invention does not use the p ⁺ well implantation required to form a p ⁺ type well, it is necessary to open an ion implantation window having a width of about 2-3 µm for each cell. There is no need to fabricate the ion implantation window forming mask. As a result, the manufacturing process can be simplified and the chip size can be reduced.

Claims (5)

A fixing for forming a second conductive buffer layer 13 doped with a high concentration of impurities on the first conductive semiconductor substrate 12 doped with a high concentration of impurities; Forming a low-concentration second conductive semiconductor layer (14) by epitaxial growth on the buffer layer (13); Forming a polysilicon film on the semiconductor layer (14) with an oxide film therebetween; Forming a photoresist pattern (17) on the polysilicon film to define a well region; Forming a gate polysilicon film (16) by selectively removing the polysilicon film using the photosensitive film pattern (17) as a mask; Removing the photoresist pattern (17) and implanting impurity ions into the well region using the gate polysilicon layer (16) as a mask to form a first conductivity type well (19); Selectively removing an oxide film (15) on the surface of the well (19) defined by the gate polysilicon film (16) to form an oxide film pattern; By using the gate polysilicon layer 16 and the oxide layer pattern 15 as a mask to implant a high concentration of impurity ions to form a first impurity injection layer 22 of the second conductivity type in the well 19 region Process; The second impurity injection layer 20 of the first conductive type is formed through the window of the oxide pattern 15 by implanting impurity ions using the gate polysilicon layer 16 and the oxide pattern 15 as a mask. ) And a third impurity injection layer 26 of the first conductivity type formed through the oxide film pattern 15 are simultaneously formed in the well 19, and the third impurity injection layer 26 is formed of the first impurity. Forming below the injection layer (22) and above the second impurity injection layer (20); After removing the oxide layer pattern 15, a process of forming a metal electrode 29 on the well 19 by sandwiching an insulating layer 28 between the gate polysilicon layer 16 so as not to be in electrical contact with the gate polysilicon layer 16. And; Subsequently, heat treatment is performed to diffuse the ions of the first, second, and third impurity injection layers 22, 20, and 26 so that the source junction region 25, the impurity diffusion region 24 for latch-up control 24, and the ohmic contact region 27 are diffused. A method of manufacturing a power semiconductor device comprising the step of forming. The method of manufacturing a power semiconductor device according to claim 1, wherein the first conductive type is p type and the second conductive type is p type. Forming a second conductive buffer layer 13 doped with a high concentration of impurities on the first conductive semiconductor substrate 12 doped with a high concentration of impurities; Forming a low-concentration second conductive semiconductor layer (14) by epitaxial growth on the buffer layer (13); Forming a polysilicon film on the semiconductor layer (14) with an oxide film therebetween; Forming a photoresist pattern (17) on the polysilicon film to define a well region; Forming a gate polysilicon film (16) by selectively removing the polysilicon film and the oxide film using the photosensitive film pattern (17) as a mask; Removing the photoresist pattern (17) and implanting impurity ions into the well region using the gate polysilicon layer (16) as a mask to form a first conductivity type well (19); Forming a source junction region by forming an oxide film pattern on the surface of the well (19) defined by the gate polysilicon film (16); The impurity implantation layer 20 of the first conductive type latch-up control formed through the window of the oxide layer pattern 15 by using the gate polysilicon layer 16 and the oxide layer pattern 15 as a mask and implanting impurity ions. And the first conductive type ohmic contact impurity injection layer 26 formed through the oxide film pattern 15 are simultaneously formed in the well 19, and the ohmic contact impurity injection layer 26 is formed on the latch. A step formed below the impurity injection layer 20 for up control; The gate polysilicon layer 16 and the oxide layer pattern 15 are used as a mask, and a high concentration of impurity ions are implanted to form a second conductive impurity implantation layer 22 in the well 19 region. Forming step; After removing the oxide layer pattern 15, a process of forming a metal electrode 29 on the well 19 by sandwiching an insulating layer 28 between the gate polysilicon layer 16 so as not to be in electrical contact with the gate polysilicon layer 16. And; And then heat-treating to form ions in the impurity implantation layers 22, 20, and 26 to form a source junction region 25, a latch diffusion control impurity diffusion region 24, and an ohmic contact region 27. Method for manufacturing a power semiconductor device. In the method for manufacturing a power semiconductor device, in which a buffer layer 13 and a semiconductor layer 14 are sequentially formed on a semiconductor substrate 12, a polysilicon is formed on the semiconductor layer 14 with an oxide film interposed therebetween. Forming a film; Patterning the polysilicon film to form a gate polysilicon film (16); Implanting impurity ions into the well region using the gate polysilicon film 16 as a mask to form a first conductivity type well 19; Selectively removing an oxide film (15) on the surface of the well (19) defined by the gate polysilicon film (16) to form an oxide film pattern; By using the gate polysilicon layer 16 and the oxide layer pattern 15 as a mask to implant a high concentration of impurity ions to form a first impurity injection layer 22 of the second conductivity type in the well 19 region Process; The second impurity injection layer 20 of the first conductive type is formed through the window of the oxide pattern 15 by implanting impurity ions using the gate polysilicon layer 16 and the oxide pattern 15 as a mask. ) And a third impurity injection layer 26 of the first conductivity type formed through the oxide film pattern 15 are simultaneously formed in the well 19, and the third impurity injection layer 26 is formed of the first impurity. Forming below the injection layer (22) and above the second impurity injection layer (20); Subsequently, heat treatment is performed to diffuse the ions of the first, second, and third impurity injection layers 22, 20, and 26 so that the source junction region 25, the impurity diffusion region 24 for latch-up control 24, and the ohmic contact region 27 are diffused. A method of manufacturing a power semiconductor device comprising the step of forming. In the method for manufacturing a power semiconductor device, in which a buffer layer 13 and a semiconductor layer 14 are sequentially formed on a semiconductor substrate 12, a polysilicon is formed on the semiconductor layer 14 with an oxide film interposed therebetween. Forming a film; Patterning the polysilicon film to form a gate polysilicon film (16); Implanting impurity ions into the well region using the gate polysilicon film 16 as a mask to form a first conductivity type well 19; Selectively removing an oxide film (15) on the surface of the well (19) defined by the gate polysilicon film (16) to form an oxide film pattern; The impurity implantation layer 20 of the first conductive type latch-up control formed through the window of the oxide layer pattern 15 by using the gate polysilicon layer 16 and the oxide layer pattern 15 as a mask and implanting impurity ions. And the first conductive type ohmic contact impurity injection layer 26 formed through the oxide film pattern 15 are simultaneously formed in the well 19, and the ohmic contact impurity injection layer 26 is formed on the latch. A step formed below the impurity injection layer 20 for up control; The gate polysilicon layer 16 and the oxide layer pattern 15 are used as a mask, and a high concentration of impurity ions are implanted to form a second conductive impurity implantation layer 22 in the well 19 region. Forming step; And then heat-treating to form ions in the impurity implantation layers 22, 20, and 26 to form a source junction region 25, a latch diffusion control impurity diffusion region 24, and an ohmic contact region 27. Method for manufacturing a power semiconductor device.