KR0170665B1 - Ram for 3-dimensional graphics - Google Patents

Abstract

The present invention relates to a RAM for three-dimensional graphics that accelerates the processing of three-dimensional graphics by rapidly updating a Z buffer essential to three-dimensional graphics.

The RAM for 3D graphics according to the present invention is a DRAM for storing an existing pixel value: first and second data registers for storing new pixel values transmitted from a raster engine and operating alternately with each other, and a read of the DRAM. First and second latch registers which store existing pixel values read from the DRAM during operation or provide the pixel values latched during the write operation of the DRAM to the DRAM in a read operation of the DRAM, and alternately operate with each other; Compares the existing Z values latched in the first or second data register with the new Z values latched in the first or second latch register, and converts the new pixel values according to the result. Comparator overwrites latch register 2, internal bus for data transfer between DRAM and first and second latch registers, generated in raster engine To an address from the latch and latches the address generating a plurality of addresses specifying the pixel of the next access address latch estimated buffer provided to the DRAM; And a controller configured to provide the addresses generated in the address latch buffer during read and write of the DRAM according to an address generated by a raster engine and a function signal, and to control an interaction between the data register and the latch register. do.

The RAM for 3D graphics according to the present invention has an effect of writing new pixel values faster by comparing and updating existing pixel values with new pixel values in a pipeline form.

Description

RAM for 3D Graphics

1 is a block diagram showing the configuration of a conventional three-dimensional graphics system.

2 is a block diagram showing the configuration of a conventional three-dimensional graphics RAM.

3 is a block diagram showing the configuration of a three-dimensional graphics RAM according to the present invention.

4 is a timing diagram showing the operation of the apparatus shown in FIG.

The present invention relates to a three-dimensional graphics RAM having a color buffer and a Z-buffer, and more particularly, to update three-dimensional graphics by quickly updating the Z buffer essential to the three-dimensional graphics processing. It relates to a three-dimensional graphics RAM to accelerate the processing of.

The first hardware based on the Z-buffer algorithm was based on the traditional DRAM architecture, introduced in the 1970s, and in the 1980s, VRAM was added to add additional input and output ports to the DRAM. The processing speed of graphics was increased by VRAM, but this was an improvement in the speed of access to memory, but not the speed of rendering.

FBRAM, developed by Mitsubish Electric Corporation, uses a cache technique, which not only requires cache memory (using SRAM) but also stores tags and line state necessary to determine the hit and miss of the cache memory. There is an additional need for a tag RAM and a cash controller to control them. As a result, FBRAMs are expensive and have complex interfaces.

Accordingly, an object of the present invention is to provide a RAM for 3D graphics that performs a Z buffer algorithm with a simple structure.

A 3D graphics RAM according to the present invention which achieves the above object is a buffer for storing pixel values in a 3D graphics RAM which periodically reads stored pixel values (color value and Z value) and outputs them as an image signal. Memory, first and second data registers which alternately store new pixel values transmitted from the raster engine, and store existing pixel values read from the buffer memory during read operation of the buffer memory or the buffer The pixel values latched during the write operation of the buffer memory are supplied to the buffer memory during a read operation of the memory, and latched in the first and second latch registers and the first or second data registers that operate alternately. Compare existing Z values with new Z values latched in the first or second latch registers A comparator that overwrites small values to the first or second latch register, an internal bus for data transfer between the buffer memory and the first and second latch registers, and latches an address generated in the raster engine An address latch buffer for generating a plurality of addresses that specify a pixel for which next access is expected from the latched address and providing the buffer memory to the buffer memory, an address generated by the raster engine, and an address generated by the address latch buffer according to a function signal. And a control unit for reading and writing the buffer memory, and controlling an alternating operation of the data register and the latch register. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a conventional three-dimensional graphics system. The apparatus shown in FIG. 1 consists of a geometry engine 10, a raster engine 12, a RAM for three-dimensional graphics 14, a digital to analog converter 16, and a cathode ray tube (CRT) 18. do.

In 3D graphics, an object represented by primitives such as triangles and lines forms a frame screen through the geometry engine 10 and the raster engine 12. The formed frame screen is stored in the RAM 14 for 3D graphics.

The geometry engine 10 is implemented using a floating point processor or a digital signal processor (DSP) because floating point operations such as modeling transformation, clipping, lighting, and projection are performed. do.

The raster engine 12 performs color value calculation by a shading model, Z value calculation by a Z-buffer algorithm for masking, etc., for each pixel of the basic element. In the raster engine 12, since a relatively simple and repetitive operation is performed, a unique VLSI chip is designed and used.

The pixels stored in the frame buffer memory 14 are read out periodically.

The digital / analog converter 16 converts digital image data read periodically from the frame buffer memory 14 into analog image data. The CRT 18 provides an analog video signal output from the digital / analog converter 16 as a video output.

In general, a complex scene consists of a collection of objects. If two opaque objects are projected at the same point on the screen, only the object closer to the eye is visible. Therefore, in order to accurately draw complex scenes, objects closest to the eyes should appear on the screen, and objects behind them should not appear on the screen.

In animation, a complex scene is constructed by creating models that draw a plurality of basic elements and then overlapping them. In this case, the Z buffer algorithm can be used to construct a continuous scene.

The basic element is composed of a large number of pixels. Graphics systems that use the Z-buffer algorithm determine whether the element is visible at every pixel in the frame. The Z value is read from the frame buffer memory 14 for all the pixels in the basic element and compared with the new Z value generated in the raster engine 20. If the pixel is visible, the new Z value and color value are written to the frame buffer memory 14.

That is, each time a new pixel value is generated, a READ MODIFY cycle of reading, updating, and writing data recorded in the frame buffer memory 14 must be performed.

In order to change a screen or a fast scene with precision, RAM for 3D graphics with very fast access speed is required, but such RAM for 3D graphics is expensive and has a complicated interface.

2 is a block diagram showing a conventional three-dimensional graphics RAM showing the FBRAM structure developed by Mitsubish Electric Corporation. The apparatus shown in FIG. 2 includes a cache memory 22 composed of a DRAM 20 including a page buffer, an SRAM storing data read from the DRAM 20 in units of pages, and a Z read from the cache memory 22. A comparison device 24 for comparing the value with the new Z value generated from the rasterizer and updating the cache memory 22 according to the result, and the cache memory 22 according to the address generated in the raster engine 12. It includes a cache control unit 26 for controlling.

Since the RAM for 3D graphics shown in FIG. 2 uses a cache technique, not only cache memory is required, but also a tag for storing a tag and a line state necessary to determine the hit and miss of the cache memory. There is a further need for RAM and a cash controller to control them.

3 is a block diagram showing the configuration of a three-dimensional graphics RAM according to the present invention. The apparatus shown in FIG. 3 reads from the buffer memory 30, two data registers 31 and 32, which store new pixel values (color and Z values) transmitted from the raster engine (12 in FIG. 1). Two latch registers 33 and 34 that store the existing Z value, and compare the existing Z value with the new Z value and update the new pixel value to the latch registers 33 and 34 according to the result. The comparator 35, the internal bus 36 for data transfer between the DRAM 30 and the latch registers 33 and 34, the address latch buffer 39 for latching and storing the address, and the internal according to the address and control information. It is comprised as the control part 38 which controls an operation.

In general, since the addresses of interpolated (interpolated) pixel values generated in the raster engine 12 increase sequentially, the next access address can be predicted by decoding the initial address. By using this address prediction method, the existing Z values expected to be accessed are read from the buffer memory 30 in advance and compared with the Z values generated in the raster engine 12, thereby reducing the time required for the READ MODIFY cycle. Can be.

The address and control signal generated by the raster engine 12 are input to the address buffer latch 39 and the control unit 38 of the 3D graphics RAM according to the present invention, respectively. On the other hand, the pixel values (color value and Z value) are stored in the data registers 31 and 32.

The address buffer latch 30 generates the latched initial address and addresses from which it is expected to be accessed next. The generated addresses are provided to the buffer memory 30, and the pixel values read out from the buffer memory 30 are transferred to the latch register 0 33 through the internal bus 36.

Existing Z values sent to latch register 0 (33) are compared with new Z values stored in data registers (31, 32) by comparator (35).

The new pixel values stored in the data registers 31 and 32 are newly written or discarded in the latch register 0 33 according to the comparison result in the comparator 35.

When all existing pixel values latched in the latch register 0 (33) are updated through the above process, they are immediately transferred to the DRAM (30). Since these operations are performed alternately by two latch registers 33 and 34 and data registers 31 and 32, they can be executed continuously without waiting time until the comparison operation of the comparator is completed. A more compact and faster Z buffer algorithm can be implemented. In FIG. 3, reference numerals 40 and 41 are serial registers for periodically reading pixel values stored in the RAM 30, and 42, 43, and 44 are multiplexers.

4 is a timing diagram showing an operation cycle of the apparatus shown in FIG. Pixel data is 64 bits (R, G, B, alpha is 8 bits, Z value is 24 bits), Data register is 64 bits, Latch register is 256 bits (4 pixel size), Internal bus is 256 Assume the case consists of bits.

When the raster engine 12 writes 64-bit data (one pixel data) to the 3D graphics RAM according to the present invention at the address X00000000, the addresses A31-A0 are transmitted to the address buffer 39, and a function signal. (function signal) (0, 1, 2, 3), WE, BE, RAS, CAS are transmitted to the control unit 38, and the pixel value is transmitted to the data register 0 (31).

When the value of the latched function signal is X0 and WE, RAS, and CAS are active, the control unit 38 decodes them and assigns four existing pixel values at once and 32-bit of 64-bit. The control signal is sent to the address buffer latch 39 and the comparator 35 so that only the bits are compared. The storage location of the DRAM 30 is selected by the address of RAS and CAS generated from the address buffer latch 39, and the four existing pixel values stored therein are stored through the latch register 0 (256 bits through the internal bus 36). 33) is read out.

The above operation is executed in the first cycle SO and at the same time, a new pixel value obtained from the raster engine 12 is stored in the data register 0 (31).

In the second cycle S1, the comparator 35 compares bit 32-bit 55, which is the Z value portion of the existing pixel latched at the first address of the latch register 0 33, with the Z value stored in the data register 0 31. According to the comparison result, the new pixel value is overwritten or discarded at the first address of the latch register 0 (33). In parallel with the above operation, the raster engine 12 stores the new pixel value at X00000008 as the data register 1 (32). At this time, the address X00000008 of the corresponding pixel value is used to select the second address of the latch register 0 33 without being transferred to the DRAM 30.

The existing pixel value of the selected second address is transferred to the comparator 35 in the third cycle S2, where it is compared with the new pixel value stored in the data register 1 32 and updated accordingly. This operation proceeds the same in the fourth cycle S3 and continues until all four existing pixel values stored in the latch register 0 33 are compared.

In the fifth cycle S4 (page hit state), the raster engine 12 generates a new pixel value, a function signal X0 together with X00000020, and the control unit 38 and the address buffer latch 39 provide a related signal. Decode and read transfer are performed so that four existing pixel values are latched from the DRAM 30 to the latch register 1 (34).

In the sixth cycle S5, an operation for recording and transferring the pixel value of the already completed latch register 0 33 to the DRAM 30 is performed. This designates the storage location of the DRAM 30 as the address (latched in the first cycle) that was latched in the address buffer latch 39 when the value of the function signal is X1, and all update pixels of the latch register 0 33 therein. This is done by loading the value through the internal write transfer cycle.

While the above series of operations continue, the raster engine 12 can continuously write new pixel values without requiring a read cycle, a mod cycle, or a standby cycle, thereby improving performance of the Z buffer algorithm.

As described above, the RAM for 3D graphics according to the present invention has an effect of writing new pixel values faster by comparing and updating the existing pixel values with the new pixel values in a pipeline form.

In addition, the raster engine can continuously write new pixel values because it can decode the addresses generated by the raster engine and prefetch four existing pixel values from the DRAM and at the same time receive new pixel values from the raster engine. .

In addition, the RAM for three-dimensional graphics according to the present invention has the advantage that the design is simpler and cheaper than when using the conventional cache technique.

Claims (1)

3. A 3D graphics RAM which periodically reads stored pixel values (color value and Z value) and outputs them as an image signal, comprising: a buffer memory for storing pixel values and new pixel values transmitted from a raster engine First and second data registers operating in a favorable manner, and store existing pixel values read from the buffer memory during a read operation of the buffer memory, or latched pixel values during a write operation of the buffer memory during a read operation of the buffer memory. To first and second latch registers, and to existing Z values latched to the first or second data registers and to the first or second latch registers. Compares the latched new Z values and overwrites the new pixel values to the first or second latch register according to the result. Intersect, an internal bus for data transfer between the buffer memory and the first and second latch registers, a plurality of latches of addresses generated in the raster engine and designating pixels to be expected next access from the latched addresses. An address latch buffer for generating and providing addresses to the buffer memory, an address generated from the address latch buffer according to an address and a function signal generated from a raster engine, and at the time of reading and writing the buffer memory, and providing the data register And a control unit for controlling an alternating operation of the latch register.