KR0170515B1 - A semiconductor device with a gold structure and a method of fabricating the same - Google Patents
A semiconductor device with a gold structure and a method of fabricating the same Download PDFInfo
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- KR0170515B1 KR0170515B1 KR1019950033418A KR19950033418A KR0170515B1 KR 0170515 B1 KR0170515 B1 KR 0170515B1 KR 1019950033418 A KR1019950033418 A KR 1019950033418A KR 19950033418 A KR19950033418 A KR 19950033418A KR 0170515 B1 KR0170515 B1 KR 0170515B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 125
- 229920005591 polysilicon Polymers 0.000 claims abstract description 125
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 32
- 239000010410 layer Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Abstract
본 발명은 GOLD 구조를 갖는 반도체장치 및 그의 제조방법에 관한 것으로서, 그 구성은 활성영역과 필드영역이 정의되어 있고 그리고 상기 활성영역에 LDD 영역(43a)과 고농도의 확산영역(43b)으로 형성된 소오스/드레인영역이 형성되어 있는 반도체기판(30)과; 상기 반도체기판(30)상에 필드영역에 형성된 소자격리용 산화막(32)과; 상기 활성영역상에 형성된 게이트 산화막(34)과; 상기 게이트산화막(34)상에 형성되어 있고 그리고 사이에 소정두께를 갖는 산화막(38)이 끼워져 있는 제1 및 제2폴리실리콘막(36,40)과; 상기 제1폴리실리콘막(36)상에서 상기 제2폴리실리콘막(40)과 상기 산화막(38)의 측벽에 형성되고 그리고 상기 제1 및 제2폴리실리콘막(36,40)을 전기적으로 접속하는 측벽폴리실리콘막(44)과; 상기 게이트산화막(34)상에서 상기 측벽폴리실리콘막(44)과 상기 제1폴리실리콘막(36)의 측벽에 형성된 측벽산화막(46)과; 상기 소오스/드레인영역과 상기 제2폴리실리콘막의 표면에 형성된 콘택부(48)를 포함한다. 상기 GOLD 구조에 의해, 측벽폴리실리콘막(46)의 폭에 의해서 게이트와 드레인의 중첩길이가 결정되기 때문에, 그 게이트-드레인 중첩길이의 조절이 용이하고, 그리고 게이트전극으로 사용되는 상기 상하부의 폴리실리콘막(36)(40)의 사이에 소정두께를 갖는 산화막(38)이 형성되어 있기 때문에, 양호한 수직구조를 갖는 폴리실리콘막(40)이 비등방성식각에 의해 용이하게 형성될 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a GOLD structure and a method of manufacturing the same, the configuration of which is defined as an active region and a field region, and a source formed of an LDD region 43a and a high concentration diffusion region 43b in the active region. A semiconductor substrate 30 having a / drain region formed thereon; An element isolation oxide film 32 formed in the field region on the semiconductor substrate 30; A gate oxide film 34 formed on the active region; First and second polysilicon films 36 and 40 formed on the gate oxide film 34 and sandwiching an oxide film 38 having a predetermined thickness therebetween; It is formed on the sidewalls of the second polysilicon film 40 and the oxide film 38 on the first polysilicon film 36 and electrically connects the first and second polysilicon films 36 and 40. A sidewall polysilicon film 44; Sidewall oxide films 46 formed on sidewalls of the sidewall polysilicon film 44 and the first polysilicon film 36 on the gate oxide film 34; And a contact portion 48 formed on the surface of the source / drain region and the second polysilicon layer. Since the overlap length of the gate and the drain is determined by the width of the sidewall polysilicon film 46 by the GOLD structure, the gate-drain overlap length can be easily adjusted, and the upper and lower polys used as the gate electrode Since the oxide film 38 having a predetermined thickness is formed between the silicon films 36 and 40, the polysilicon film 40 having a good vertical structure can be easily formed by anisotropic etching.
Description
제1도는 종래의 반도체장치의 구조를 보인 단면도.1 is a cross-sectional view showing the structure of a conventional semiconductor device.
제2a도 내지 제2d도는 종래의 제조방법에 따라 제1도의 반도체장치를 제조하는 공정들을 보인 순차적인 공정도.2A to 2D are sequential process diagrams showing processes for manufacturing the semiconductor device of FIG. 1 according to a conventional manufacturing method.
제3도는 본 발명의 반도체장치의 구조를 보인 단면도.3 is a cross-sectional view showing the structure of a semiconductor device of the present invention.
제4a도 내지 제4d도는 본 발명의 제조방법에 따라 제3도의 반도체장치를 제조하는 공정들을 보인 순차적인 공정도.4A through 4D are sequential process diagrams showing processes for manufacturing the semiconductor device of FIG. 3 according to the manufacturing method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
30 : 반도체기판 32 : 소자분리용 산화막30: semiconductor substrate 32: oxide film for device isolation
34 : 게이트산화막 36 : 제1폴리실리콘막34: gate oxide film 36: first polysilicon film
38 : 층간산화막 40 : 제2폴리실리콘막38: interlayer oxide film 40: second polysilicon film
42 : 상부산화막 44 : 측벽폴리실리콘막42: upper oxide film 44: sidewall polysilicon film
46 : 측벽산화막 48 : 실리사이드막46 sidewall oxide film 48 silicide film
본 발명은 반도체장치의 제조에 관한 것으로서, 구체적으로는 GOLD(gate-drain overlapped LDD)구조를 갖는 반도체장치와 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a semiconductor device having a gate-drain overlapped LDD (GOLD) structure and a manufacturing method thereof.
일반적으로, 반도체장치에 있어서 집적도와 속도특성은 매우 중요한 요소이다. 이러한 집적도와 속도특성을 고려하여 MOS(metal oxide semiconductor) 소자는 개발되어 왔고, 또한 고내압 및 신뢰성의 향상을 위한 소자의 구조에 대한 연구도 활발히 진행되어 왔다.In general, integration and speed characteristics are very important factors in semiconductor devices. In consideration of such integration and speed characteristics, metal oxide semiconductor (MOS) devices have been developed, and researches on the structure of devices for improving the breakdown voltage and reliability have been actively conducted.
특히, 속도특성과 신뢰성의 향상을 위해서 제안된 GOLD 구조는 횡적 영역을 감소시켜서 짧은 채널효과(short channel effect)에 의한 드레숄드전압의 감소를 방지할 수 있을 뿐만 아니라 소오스-드레인사이의 펀치스루(punchthrough)의 저하를 방지할 수 있고, 또한 핫 캐리어(a hot carrier) 효과에 의한 소자의 특성열화를 방지할 수 있는 구조로 사용되어 왔다.In particular, the proposed GOLD structure for improving the speed characteristics and reliability can reduce the lateral area to prevent the reduction of the threshold voltage due to the short channel effect, as well as the punch-through between the source and the drain. It has been used as a structure that can prevent the punchthrough from being lowered and also prevent the deterioration of characteristics of the device due to a hot carrier effect.
그러나, 상술한 GOLD 구조를 갖는 반도체장치의 제조공정은 복잡할 뿐만 아니라, 제조가 어려운 문제가 있었다.However, the manufacturing process of the semiconductor device having the GOLD structure described above is not only complicated, but also difficult to manufacture.
이러한 GOLD 구조를 갖는 반도체장치가 제1도에 도시되어 있다.A semiconductor device having such a GOLD structure is shown in FIG.
제1도를 참고하면, 반도체기판(10)상에 활성영역과 필드영역이 정의되어 있고 그리고 상기 활성영역에 LDD(lightly doped drain) 영역(22)과 고농도의 확산영역(28)으로 형성된 소오스/드레인영역이 형성되어 있다. 게이트산화막(12)상에 자연산화막(natural oxide:16)을 사이에 끼우고 제1 및 제2폴리실리콘막(14,18)이 형성되어 있고, 상기 제2폴리실리콘막(18)상에 CVD(chemical vapor deposition) 산화막(20)이 형성되어 있고, 그리고 상기 자연산화막(16)상에서 상기 CVD 산화막(20)과 상기 제2폴리실리콘막(18)의 측벽에 측벽폴리실리콘막(24)이 형성되어 있다. 또한, 상기 제1폴리실리콘막(14)의 양단에는 SELOCS(selective oxide coating of silicon-gate)법에 의해서 저온습식산화되어서 SELOCS 산화막(26)이 형성되어 있다.Referring to FIG. 1, an active region and a field region are defined on a semiconductor substrate 10, and a source / field formed of a lightly doped drain (LDD) region 22 and a high concentration diffusion region 28 is formed in the active region. A drain region is formed. First and second polysilicon films 14 and 18 are formed on the gate oxide film 12 with a natural oxide layer 16 interposed therebetween, and CVD is performed on the second polysilicon film 18. (chemical vapor deposition) An oxide film 20 is formed, and a sidewall polysilicon film 24 is formed on sidewalls of the CVD oxide film 20 and the second polysilicon film 18 on the natural oxide film 16. It is. In addition, SELOCS oxide films 26 are formed on both ends of the first polysilicon film 14 by low temperature wet oxidation by a selective oxide coating of silicon-gate (SELOCS) method.
이러한 GOLD 구조에 있어서는, 상기 SELOCS 산화막(26)의 폭에 의해서 게이트-드레인 중첩길이가 결정되기 때문에, 그 길이를 조절하기 어려울 뿐 아니라 공정의 재현성에도 문제가 있었다.In such a GOLD structure, since the gate-drain overlap length is determined by the width of the SELOCS oxide film 26, it is difficult to control the length and there is a problem in the reproducibility of the process.
또한, 게이트폴리실리콘막으로서 형성된 제1폴리실리콘막(14)과 제2폴리실리콘막(18)이 자연산화막(16)에 의해 구분되기 때문에, 상기 제2폴리실리콘막(18)이 등방성식각법에 의해 식각된다. 그 결과, 제2폴리실리콘막(18)의 수직적구조가 양호하지 못하게 되는 문제가 있었다.In addition, since the first polysilicon film 14 and the second polysilicon film 18 formed as the gate polysilicon film are separated by the natural oxide film 16, the second polysilicon film 18 isotropically etched. Etched by As a result, there was a problem that the vertical structure of the second polysilicon film 18 was not good.
다음은 상술한 GOLD 구조를 갖는 반도체장치의 제조방법을 제2a도 내지 제2d도에 의거하여 설명한다.Next, a method of manufacturing a semiconductor device having the above-described GOLD structure will be described with reference to FIGS. 2A to 2D.
제2a도에 도시된 바와 같이, 반도체기판(10)상에, 게이트산화막(12)과 제1폴리실리콘막(14) 및 자연산화막(16)을 차례로 형성하고, 상기 자연산화막(16)상에는 제2폴리실리콘막(18)이 형성되며, 그리고 상기 제2폴리실리콘막(16)상에는 소정패턴의 CVD 산화막(20)이 형성된다.As shown in FIG. 2A, the gate oxide film 12, the first polysilicon film 14, and the natural oxide film 16 are sequentially formed on the semiconductor substrate 10, and the first oxide film 16 is formed on the natural oxide film 16. A bipolysilicon film 18 is formed, and a CVD oxide film 20 of a predetermined pattern is formed on the second polysilicon film 16.
이어, 상기 CVD 산화막(20)의 패턴을 마스크로 사용하여서 상기 자연산화막(16)이 노출될 때까지 등방성 식각을 실행하면, 제2b도에 도시된 바와 같이 상기 제2폴리실리콘막(18)의 상측이 과식각된다. 또한 이온주입공정을 실행하여서 반도체기판(10)에 LDD 영역(22)이 형성된다.Subsequently, when isotropic etching is performed using the pattern of the CVD oxide film 20 as a mask until the natural oxide film 16 is exposed, as shown in FIG. 2B, the second polysilicon film 18 The upper side is overetched. In addition, an LDD region 22 is formed in the semiconductor substrate 10 by performing an ion implantation process.
계속해서, 상기 CVD 산화막(20)과 상기 제2폴리실리콘막(18)의 측벽에, 제2c도에 도시된 바와 같이, 측벽폴리실리콘막(24)이 형성된다.Subsequently, sidewall polysilicon films 24 are formed on sidewalls of the CVD oxide film 20 and the second polysilicon film 18, as shown in FIG. 2C.
또한, 이온주입공정을 실행하여서 고농도의 확산층(28)이 형성된 다음, SELOCS 법에 의해서 상기 제1폴리실리콘막(14)의 양단에 산화막(26)이 형성된다. 이와같이, 제1도와 같은 GOLD 구조를 갖는 종래의 반도체장치의 제조가 완료된다.Further, a high concentration diffusion layer 28 is formed by performing an ion implantation process, and then an oxide film 26 is formed on both ends of the first polysilicon film 14 by SELOCS method. Thus, the manufacture of the conventional semiconductor device having the GOLD structure as shown in FIG. 1 is completed.
이러한 종래의 방법에 의하면, 상기 SELOCS 산화막(26)의 폭에 의해서 게이트-드레인 중첩길이가 결정되고, 그리고 게이트폴리실리콘막으로서 형성된 제1폴리실리콘막(14)과 제2폴리실리콘막(18)이 자연산화막(16)에 의해 구분되기 때문에, 상술한 문제점들이 야기된다.According to this conventional method, the gate-drain overlap length is determined by the width of the SELOCS oxide film 26, and the first polysilicon film 14 and the second polysilicon film 18 formed as the gate polysilicon film are Since it is distinguished by this natural oxide film 16, the above-mentioned problems are caused.
따라서, 본 발명의 목적은 게이트측벽에 형성되는 측벽폴리실리콘막에 폭에 의해서 게이트와 드레인의 중첩길이가 조절될 수 있는 GOLD 구조를 갖는 반도체장치 및 그의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a semiconductor device having a GOLD structure in which the overlap length of the gate and the drain can be adjusted by the width of the sidewall polysilicon film formed on the gate side wall, and a manufacturing method thereof.
본 발명의 다른 목적은 게이트전극으로 사용되는 상기 상하부의 폴리실리콘막의 사이에 소정두께를 갖는 산화막에 의거하여 비등방성 식각에 의해 양호한 수직구조를 갖는 상부폴리실리콘막이 형성되는 GOLD 구조를 갖는 반도체장치 및 그의 제조방법을 제공하는데 있다.Another object of the present invention is a semiconductor device having a GOLD structure in which an upper polysilicon film having a good vertical structure is formed by anisotropic etching based on an oxide film having a predetermined thickness between the upper and lower polysilicon films used as gate electrodes; It is to provide a method for producing the same.
상술한 목적을 달성하기 위한 본 발명의 일특징에 의하면, GOLD 구조를 갖는 반도체장치는, 활성영역과 필드영역이 정의되어 있고 그리고 상기 활성영역에 LDD 영역과 고농도의 확산영역으로 형성된 소오스/드레인영역이 형성되어 있는 반도체기판과; 상기 반도체기판상에 필드영역에 형성된 소자격리용 산화막과; 상기 활성영역상에 형성된 게이트산화막과; 상기 게이트산화막상에 형성되어 있고 그리고 사이에 소정두께를 갖는 산화막이 끼워져 있는 제1 및 제2폴리실리콘막과; 상기 제1폴리실리콘막상에서 상기 제2폴리실리콘막과 상기 산화막의 측벽에 형성되고 그리고 상기 제1 및 제2폴리실리콘막을 전기적으로 접속하는 측벽폴리실리콘막과; 상기 게이트산화막상에서 상기 측벽폴리실리콘막과 상기 제1폴리실리콘막의 측벽에 형성된 측벽산화막과; 상기 소오스/드레인영역과 상기 제2폴리실리콘막의 표면에 형성된 콘택부를 포함한다.According to one aspect of the present invention for achieving the above object, in a semiconductor device having a GOLD structure, an active region and a field region are defined and a source / drain region formed of an LDD region and a high concentration diffusion region in the active region. A semiconductor substrate formed thereon; An isolation film for isolation of an element formed in the field region on the semiconductor substrate; A gate oxide film formed on the active region; First and second polysilicon films formed on the gate oxide film and sandwiched with an oxide film having a predetermined thickness therebetween; A sidewall polysilicon film formed on the first polysilicon film and formed on sidewalls of the second polysilicon film and the oxide film and electrically connecting the first and second polysilicon films; A sidewall oxide film formed on the sidewalls of the sidewall polysilicon film and the first polysilicon film on the gate oxide film; And a contact portion formed on the surface of the source / drain region and the second polysilicon layer.
이 장치에 있어서, 상기 콘택부는 실리사이드막이다.In this apparatus, the contact portion is a silicide film.
본 발명의 다른 특징에 의하면, GOLD 구조를 갖는 반도체장치의 제조방법은, 반도체기판상에 활성영역과 필드영역을 정의한 다음, 상기 필드영역에 소자격리용 산화막을 형성하는 공정과; 상기 소자격리용 산화막사이의 활성영역상에 게이트산화막을 형성하는 공정과; 상기 게이트산화막과 상기 소자격리용 산화막상에 도전형의 제1폴리실리콘막과 층간산화막을 차례로 형성하는 공정과; 상기 산화막상에 도전형 제2폴리실리콘막과 상부산화막을 차례로 형성하는 공정과; 소정 패턴의 마스크를 사용하여 상기 상부산화막과 상기 제2폴리실리콘막 및 상기 층간산화막을 선택적으로 제거하여 게이트구조물을 형성하는 공정과; 상기 게이트구조물을 마스크로 사용하는 불순물주입을 실행하여 상기 반도체기판에 LDD 영역을 형성하는 공정과; 상기 게이트구조물의 측벽에 도전형의 측벽폴리실리콘막을 형성하는공정과; 상기 측벽폴리실리콘막이 형성된 상기 게이트 구조물을 마스크로 사용하는 불순물주입을 실행하여 고농도의 소오스/드레인 확산영역을 형성하는 공정과; 상기 측벽폴리실리콘막과 상기 노출된 폴리실리콘막의 측벽에 측벽산화막을 형성하는 공정을 포함한다.According to another aspect of the present invention, a method of manufacturing a semiconductor device having a GOLD structure includes: defining an active region and a field region on a semiconductor substrate, and then forming an element isolation oxide film in the field region; Forming a gate oxide film on an active region between the device isolation oxide films; Forming a conductive first polysilicon film and an interlayer oxide film sequentially on the gate oxide film and the device isolation oxide film; Sequentially forming a conductive second polysilicon film and an upper oxide film on the oxide film; Selectively removing the upper oxide film, the second polysilicon film, and the interlayer oxide film using a mask having a predetermined pattern to form a gate structure; Forming an LDD region in the semiconductor substrate by performing impurity implantation using the gate structure as a mask; Forming a conductive sidewall polysilicon film on the sidewalls of the gate structure; Performing impurity implantation using the gate structure on which the sidewall polysilicon film is formed as a mask to form a high concentration source / drain diffusion region; Forming a sidewall oxide film on sidewalls of the sidewall polysilicon film and the exposed polysilicon film.
이 방법에 있어서, 상기 제2폴리실리콘막의 제거공정은 건식식각에 의해 실행된다.In this method, the step of removing the second polysilicon film is performed by dry etching.
이 방법에 있어서, 상기 층간산화막은 건식 또는 습식식각에 의해 실행된다.In this method, the interlayer oxide film is performed by dry or wet etching.
이 방법에 있어서, 상기 측벽폴리실리콘막의 형성공정은 폴리실리콘막을 퇴적하는 공정과 이 퇴적된 폴리실리콘막에 불순물이온을 주입하는 공정 및 비등방성 식각을 실행하여 상기 측벽폴리실리콘막을 형성하는 공정을 포함한다.In this method, the step of forming the sidewall polysilicon film includes depositing a polysilicon film, implanting impurity ions into the deposited polysilicon film, and performing anisotropic etching to form the sidewall polysilicon film. do.
이 방법에 있어서, 상기 비등방성 식각을 실행하는 공정이 실행되는 과정에 상기 측벽폴리실리콘막이 형성된 게이트구조물이외의 상기 제1폴리실리콘막이 선택적으로 동시에 제거된다.In this method, the first polysilicon film other than the gate structure on which the sidewall polysilicon film is formed is selectively removed simultaneously in the process of performing the anisotropic etching.
이 방법에 있어서, 상기 측벽산화막의 형성공정을 실행하는 과정에 상기 제2폴리실리콘막상에 있는 상기 산화막과, 상기 구조물과 상기 소자격리용 산화막사이의 게이트산화막이 선택적으로 동시에 제거되는 것을 포함한다.In this method, the oxide film on the second polysilicon film and the gate oxide film between the structure and the device isolation oxide film are selectively removed simultaneously in the process of forming the sidewall oxide film.
이 방법에 있어서, 상기 측벽산화막의 형성공정후에 소오스/드레인 영역과 게이트영역상에 콘택용 실리사이드막을 형성하는 공정을 포함한다.The method includes a step of forming a contact silicide film on the source / drain region and the gate region after the step of forming the sidewall oxide film.
상기 GOLD 구조에 의해, 측벽폴리실리콘막의 폭에 의해서 게이트와 드레인의 중첩길이가 결정되기 때문에, 그 게이트-드레인 중첩길이의 조절이 용이하고, 그리고 게이트전극으로 사용되는 상기 상하부의 폴리실리콘막의 사이에 소정두께를 갖는 산화막이 형성되어 있기 때문에, 양호한 수직구조를 갖는 폴리실리콘막이 비등방성식각에 의해 용이하게 형성될 수 있다.The overlapping length of the gate and the drain is determined by the width of the sidewall polysilicon film by the GOLD structure, so that the gate-drain overlapping length can be easily adjusted, and between the upper and lower polysilicon films used as the gate electrode. Since an oxide film having a predetermined thickness is formed, a polysilicon film having a good vertical structure can be easily formed by anisotropic etching.
이하, 본 발명의 실시예를 첨부도면 제3도와 제4도에 의거하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 and 4 of the accompanying drawings.
제3도를 참고하면, 본 발명의 신규한 GOLD 구조를 갖는 반도체장치는, 활성영역과 필드영역이 정의되어 있고 그리고 상기 활성영역에 LDD(lightly doped drain) 영역(43a)과 고농도의 확산영역(43b)으로 형성된 소오스/드레인영역이 형성되어 있는 반도체기판(30)과; 상기 반도체기판(30)상에 필드영역에 형성된 소자격리용 산화막(32)과, 상기 활성영역상에 형성된 게이트산화막(34)과; 상기 게이트산화막(34)상에 형성되어 있고 그리고 사이에 소정두께를 갖는 산화막(38)이 끼워져 있는 제1 및 제2폴리실리콘막(36,40)과; 상기 제1폴리실리콘막(36)상에서 상기 제2폴리실리콘막(40)과 상기 산화막(38)의 측벽에 형성되고 그리고 상기 제1 및 제2폴리실리콘막(38,40)을 전기적으로 접속하는 측벽폴리실리콘막(44)과; 상기 게이트산화막(34)상에서 상기 측벽폴리실리콘막(44)과 상기 제1폴리실리콘막(36)의 측벽에 형성된 측벽산화막(46)과; 상기 소오스/드레인영역과 상기 제2폴리실리콘막의 표면에 형성된 콘택용 실리사이드막(48)을 포함하는 구성을 갖는다.Referring to FIG. 3, in the semiconductor device having the novel GOLD structure of the present invention, an active region and a field region are defined, and the lightly doped drain (LDD) region 43a and the high concentration diffusion region (LDD) are defined in the active region. A semiconductor substrate 30 having source / drain regions formed of 43b) formed thereon; An isolation layer oxide film 32 formed in the field region on the semiconductor substrate 30, and a gate oxide layer 34 formed on the active region; First and second polysilicon films 36 and 40 formed on the gate oxide film 34 and sandwiching an oxide film 38 having a predetermined thickness therebetween; The second polysilicon film 40 is formed on the sidewalls of the oxide film 38 on the first polysilicon film 36 and electrically connects the first and second polysilicon films 38 and 40. A sidewall polysilicon film 44; Sidewall oxide films 46 formed on sidewalls of the sidewall polysilicon film 44 and the first polysilicon film 36 on the gate oxide film 34; And a contact silicide film 48 formed on the surface of the source / drain region and the second polysilicon film.
상기 GOLD 구조에 있어서, 측벽폴리실리콘막(44)의 폭에 의해서 게이트와 드레인의 중첩길이가 결정되기 때문에, 그 게이트-드레인 중첩길이의 조절이 용이하고, 그리고 게이트전극으로 사용되는 상기 상하부의 폴리실리콘막(36)(40)의 사이에 소정두께를 갖는 산화막(38)이 형성되어 있기 때문에, 양호한 수직구조를 갖는 폴리실리콘막(40)이 비등방성식각에 의해 용이하게 형성될 수 있다.In the GOLD structure, since the overlap length of the gate and the drain is determined by the width of the sidewall polysilicon film 44, the gate-drain overlap length can be easily adjusted, and the upper and lower polys used as the gate electrode Since the oxide film 38 having a predetermined thickness is formed between the silicon films 36 and 40, the polysilicon film 40 having a good vertical structure can be easily formed by anisotropic etching.
다음은 제4a도 내지 제4d도를 참고하여 본 발명에 따른 반도체장치의 제조방법에 대해서 설명한다.Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 4A to 4D.
제4a도에 의하면, 반도체기판(30)상에 활성영역(an active region)과 필드영역(a field region)을 정의한 다음, 상기 필드영역에 소자격리용 산화막(32)이 형성되어 있고, 이 소자격리용 산화막(32)사이의 활성영역상에는 게이트산화막(34)이 형성되어 있으며, 그리고 상기 산화막(32,34)들상에 불순물이온이 도핑된 폴리실리콘막(36)과 산화막(38)이 순차로 형성되어 있다. 상기 폴리실리콘막(36)이 도전성을 갖기 위한 다른 실시예로서, 상기 산화막(32,34)상에 도핑되지 않은 폴리실리콘막(36)을 차례로 형성한 다음, 불순물주입공정에 의해서 상기 폴리실리콘막(36)에 불순물이온이 주입되어서 상술한 도전성을 갖는 폴리실리콘막이 형성된다.Referring to FIG. 4A, an active region and a field region are defined on the semiconductor substrate 30, and then an element isolation oxide film 32 is formed in the field region. A gate oxide film 34 is formed on the active region between the qualified oxide films 32, and the polysilicon film 36 and the oxide film 38 doped with impurity ions on the oxide films 32 and 34 are sequentially formed. Formed. As another embodiment for the polysilicon film 36 to have conductivity, an undoped polysilicon film 36 is sequentially formed on the oxide films 32 and 34, and then the polysilicon film is formed by an impurity implantation process. Impurity ions are implanted into the 36 to form the polysilicon film having the above-described conductivity.
이어, 제4b도에 도시된 바와 같이, 상기 산화막(38)상에 도전성을 갖는 폴리실리콘막(40)과 산화막(42)을 차례로 형성한 다음, 소정패턴의 감광막 패턴(미도시됨)을 상기 산화막(42)상에 형성하고, 이 감광막패턴을 마스크로 사용하여 건식식각을 행하여 상기 산화막(42)과 도핑된 폴리실리콘막(40)을 차례로 제거한다. 또한, 노출된 상기 산화막(38)은 건식 또는 습식식각법에 의해서 선택적으로 제거된 다음, LDD(lightly doped drain)영역을 형성하기 위하여 상기 패턴화된 산화막(42)과 폴리실리콘막(40) 및 산화막(38)의 적층구조물을 마스크로 사용하여 불순물주입공정이 실행되면, 제4b도와 같이 상기 반도체기판(30)의 표면에 LDD 영역(43a)을 갖는 구조가 형성된다. 이 경우 상기 폴리실리콘막(40) 식각시, 상기 산화막(38)이 식각정지층으로 작용하여 폴리실리콘막(36)이 식각되는 것이 방지된다. 이로 인해 상기 폴리실리콘막(36)에 덮여진 게이트 산화막(34)은 상기 식각공정으로 인한 손상으로부터 안전하게 된다. 이 식각공정으로 상기 폴리실리콘막(36)이 상기 폴리실리콘막(40)과 동일한 길이로 식각될 경우, 상기 게이트산화막(34)은 상부표면 일부가 식각되는 식각손상을 입게 되고, 이 식각손상은 기생 커패시턴스의 증가를 발생시켜 트랜지스터의 동작속도를 느리게 하고, 필드 전계에 영향을 주어 트랜지스터 동작에 악영향을 미치게 된다. 물론 상기 식각공정은 폴리실리콘막 식각공정 및 산화막 식각공정으로 구성된다. 계속해서, 제4c도에 도시된 바와 같이, 얇은 두께를 갖는 도핑된 폴리실리콘막을 형성한 다음 비등방성 식각을 행하면, 상기 폴리실리콘막(40)과 상기 산화막(38)의 측벽에 측벽폴리실리콘막(44)이 형성된다. 이때, 상기 측벽폴리실리콘막(44)이 형성하기 위한 비등방성 식각이 실행되는 과정에 상기 폴리실리콘막(36)이 동시에 선택적으로 제거된다. 이로서 폴리실리콘막(40)과 다른 길이를 갖는 게이트 전극의 폴리실리콘막(36)이 형성된다. 또한, 상기 측벽폴리실리콘막(44)이 형성된 상기 패턴화된 적층구조물을 마스크로 사용하여서 불순물주입공정을 실행하면, 제4c도와 같은 고농도의 소오스/드레인 확산영역(43b)이 형성된다.Subsequently, as shown in FIG. 4B, the conductive polysilicon film 40 and the oxide film 42 are sequentially formed on the oxide film 38, and then a photosensitive film pattern (not shown) having a predetermined pattern is formed. It is formed on the oxide film 42, and dry etching is performed using this photosensitive film pattern as a mask to sequentially remove the oxide film 42 and the doped polysilicon film 40. In addition, the exposed oxide layer 38 is selectively removed by a dry or wet etching method, and then the patterned oxide layer 42 and the polysilicon layer 40 and the silicon oxide layer 40 are formed to form a lightly doped drain (LDD) region. When the impurity implantation process is performed using the stacked structure of the oxide film 38 as a mask, a structure having the LDD region 43a is formed on the surface of the semiconductor substrate 30 as shown in FIG. 4B. In this case, when the polysilicon film 40 is etched, the oxide film 38 serves as an etch stop layer, thereby preventing the polysilicon film 36 from being etched. As a result, the gate oxide layer 34 covered with the polysilicon layer 36 is secured from damage due to the etching process. When the polysilicon layer 36 is etched to the same length as the polysilicon layer 40 by the etching process, the gate oxide layer 34 is etched to etch a portion of the upper surface, and the etch damage An increase in parasitic capacitance causes the transistor to slow down, affects the field electric field, and adversely affects transistor operation. Of course, the etching process includes a polysilicon film etching process and an oxide film etching process. Subsequently, as shown in FIG. 4C, when a doped polysilicon film having a thin thickness is formed and then anisotropically etched, a sidewall polysilicon film is formed on the sidewalls of the polysilicon film 40 and the oxide film 38. 44 is formed. At this time, the polysilicon layer 36 is selectively removed at the same time during the anisotropic etching for forming the sidewall polysilicon layer 44 is performed. As a result, a polysilicon film 36 of a gate electrode having a length different from that of the polysilicon film 40 is formed. Further, when the impurity implantation process is performed using the patterned laminated structure on which the sidewall polysilicon film 44 is formed as a mask, a high concentration source / drain diffusion region 43b as shown in FIG. 4C is formed.
마지막으로, 제4d도에 도시된 바와 같이, 제4c도의 구조물위에 산화막을 형성한 다음 비등방성 식각을 실행하면, 상기 측벽폴리실리콘막(44)과 상기 노출된 폴리실리콘막(36)의 측벽에 측벽산화막(46)이 형성된다. 이때, 상기 비등방성 식각이 실행되는 과정에, 이 측벽산화막(46)이 형성됨과 동시에, 상기 산화막(42)과 상기 패턴화된 적층구조물을 마스크로 사용하여 식각공정을 실행하면, 표면이 노출되어 있는 상기 게이트산화막(34)이 선택적으로 제거된다. 상기 산화막(42)의 제거에 의해서 노출된 상기 폴리실리콘막(40)의 표면과 상기 게이트산화막(34)의 선택적 제거에 의해서 노출된 상기 LDD 영역(43a)의 표면상에만 콘택용 실리사이드막(a silicide film:48)이 형성된다.Finally, as shown in FIG. 4D, when an oxide film is formed on the structure of FIG. 4C, and then anisotropic etching is performed, the sidewalls of the sidewall polysilicon film 44 and the exposed polysilicon film 36 are formed. A sidewall oxide film 46 is formed. At this time, when the anisotropic etching is performed, the sidewall oxide layer 46 is formed, and the etching process using the oxide layer 42 and the patterned stacked structure as a mask is performed to expose the surface. The gate oxide film 34 is selectively removed. The contact silicide film a only on the surface of the polysilicon film 40 exposed by the removal of the oxide film 42 and on the surface of the LDD region 43a exposed by the selective removal of the gate oxide film 34. silicide film 48 is formed.
상술한 반도체장치의 제조방법에 의하면, 상기 폴리실리콘막(44)에 의해 상기 폴리실리콘막(36)과 폴리실리콘막(40)이 전기적으로 연결되어서 게이트전극을 형성하기 때문에, 상기 LDD 영역(43a)과 상기 측벽폴리실리콘막(46)이 중첩되는 GOLD 구조가 형성될 수 있다.According to the above-described method of manufacturing a semiconductor device, since the polysilicon film 44 and the polysilicon film 36 are electrically connected to each other to form a gate electrode, the LDD region 43a ) And the sidewall polysilicon layer 46 may be overlapped with each other.
또한, 본 발명의 제조방법에 의해 형성된 상기 GOLD 구조에 있어서, 측벽폴리실리콘막(46)에 폭에 의해서 게이트와 드레인의 중첩길이가 조절될 수 있기 때문에, 그 게이트-드레인 중첩길이의 조절이 용이하다.Further, in the GOLD structure formed by the manufacturing method of the present invention, since the overlap length of the gate and the drain can be adjusted by the width of the sidewall polysilicon film 46, the gate-drain overlap length can be easily adjusted. Do.
게다가, 본 발명에 의한 GOLD 구조에 있어서, 게이트전극으로 사용되는 상기 상하부의 폴리실리콘막(36)(40)의 사이에 소정두께를 갖는 산화막(38)이 형성되어 있기 때문에, 양호한 수직구조를 갖는 폴리실리콘막(40)이 비등방성식각에 의해 용이하게 형성될 수 있다.Furthermore, in the GOLD structure according to the present invention, since the oxide film 38 having a predetermined thickness is formed between the upper and lower polysilicon films 36 and 40 used as the gate electrode, it has a good vertical structure. The polysilicon film 40 can be easily formed by anisotropic etching.
Claims (9)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950033418A KR0170515B1 (en) | 1995-09-30 | 1995-09-30 | A semiconductor device with a gold structure and a method of fabricating the same |
| JP8170063A JPH09116150A (en) | 1995-09-30 | 1996-06-28 | Semiconductor device with gold structure and its manufacture |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950033418A KR0170515B1 (en) | 1995-09-30 | 1995-09-30 | A semiconductor device with a gold structure and a method of fabricating the same |
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| KR970018685A KR970018685A (en) | 1997-04-30 |
| KR0170515B1 true KR0170515B1 (en) | 1999-02-01 |
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| KR1019950033418A KR0170515B1 (en) | 1995-09-30 | 1995-09-30 | A semiconductor device with a gold structure and a method of fabricating the same |
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| KR (1) | KR0170515B1 (en) |
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|---|---|---|---|---|
| KR100567047B1 (en) * | 1999-06-28 | 2006-04-04 | 주식회사 하이닉스반도체 | Menufacturing method for mos transistor |
| US7307332B2 (en) | 2004-02-27 | 2007-12-11 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104037084B (en) * | 2013-03-05 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104103505B (en) * | 2013-04-10 | 2017-03-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of grid |
| CN104183473B (en) * | 2013-05-21 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method and semiconductor devices of metal gate transistor |
-
1995
- 1995-09-30 KR KR1019950033418A patent/KR0170515B1/en not_active IP Right Cessation
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- 1996-06-28 JP JP8170063A patent/JPH09116150A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567047B1 (en) * | 1999-06-28 | 2006-04-04 | 주식회사 하이닉스반도체 | Menufacturing method for mos transistor |
| US7307332B2 (en) | 2004-02-27 | 2007-12-11 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
| US7560329B2 (en) | 2004-02-27 | 2009-07-14 | Fujitsu Microelectronics Limited | Semiconductor device and method for fabricating the same |
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| Publication number | Publication date |
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| KR970018685A (en) | 1997-04-30 |
| JPH09116150A (en) | 1997-05-02 |
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