KR0161813B1 - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- KR0161813B1 KR0161813B1 KR1019950043116A KR19950043116A KR0161813B1 KR 0161813 B1 KR0161813 B1 KR 0161813B1 KR 1019950043116 A KR1019950043116 A KR 1019950043116A KR 19950043116 A KR19950043116 A KR 19950043116A KR 0161813 B1 KR0161813 B1 KR 0161813B1
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- South Korea
- Prior art keywords
- lead
- horizontal portion
- semiconductor package
- semiconductor chip
- lead frame
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명에 의한 반도체 패키지는 반도체칩이 안착되는 리이드프레임패드와, 리이드프레임패드의 가장자리에 다수 형성되되, 반도체칩의 상면과 평행한 면상에 형성되는 수평부와, 수평부가 아랫방향으로 연장되어 형성되는 수직부로 구분되어 형성되는 리이드와, 반도체칩과 리이드를 전기적으로 연결시키는 다수의 본딩와이어와, 반도체칩과 리이드를 애워싸면 형성되되, 리이드에서 수평부의 일단면 및 저면과 수직부의 바깥면이 노출되도록 형성되는 몰딩체를 포함하여 이루어진다.The semiconductor package according to the present invention includes a lead frame pad on which a semiconductor chip is seated, a plurality of horizontal frames formed on an edge of the lead frame pad, a horizontal portion formed on a surface parallel to the upper surface of the semiconductor chip, and a horizontal portion extending downward. Leads are formed by dividing the vertical portion, and a plurality of bonding wires electrically connecting the semiconductor chip and the lead, and formed by enclosing the semiconductor chip and the lead, where one end surface and the bottom surface of the horizontal portion and the outer surface of the vertical portion are exposed. It includes a molding formed to be.
Description
제1도는 종래의 반도체 패키지의 실시예를 도시한 사시도.1 is a perspective view showing an embodiment of a conventional semiconductor package.
제2도는 본 발명에 의한 반도체 패키지의 일실시예를 도시한 사시도 및 단면도.2 is a perspective view and a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10,10',24 : 몰딩체 11,11' : 외부리이드10,10 ', 24: Molding body 11,11': Outer lead
20 : 반도체칩 21 : 리이드프레임패드20: semiconductor chip 21: lead frame pad
22 : 리이드 22-1 : 수평부22: lead 22-1: horizontal portion
22-2 : 수직부 23 : 본딩와이어22-2: vertical portion 23: bonding wire
본 발명은 반도체 패키지(package)에 관한 것으로, 특히 셋트(set) 실장시에 범용적으로 실장시킬 수 있으면서 최소의 실장면적을 갖도록 하는 것에 적당하도록 한 반도에 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a package on a peninsula, which is suitable for having a minimum mounting area while being universally mountable at the time of set mounting.
제1도는 종래의 반도체 패키지의 실시예를 도시한 사시도로서, 제1도의 (a)는 종래의 반도체 패키지에서 홀(hole)삽입용 패키지로서 디아이피(DIP; Dual Inline Package)형을 도시한 사시도이고, 제1도의 (b)는 종래의 반도체 패키지에서 표면 실장용 패키지로서 에스오피(SOP; Small outline package)형을 도시한 사시도이다. 이하 첨부된 도면을 참고로 종래의 반도체 패키지의구조를 설명하면 다음과 같다.FIG. 1 is a perspective view showing an embodiment of a conventional semiconductor package, and FIG. 1 (a) is a perspective view showing a dual inline package (DIP) type as a package for inserting holes in a conventional semiconductor package. FIG. 1B is a perspective view showing a small outline package (SOP) type as a surface mounting package in a conventional semiconductor package. Hereinafter, a structure of a conventional semiconductor package will be described with reference to the accompanying drawings.
종래의 반도체 패키지의 실시예에서 디아이피형의 반도체 패키지는 제1도의 (a)에 도시된 바와 같이, 직육면체 형태로 된 몰딩체(molding body)(10)와, 몰딩체의 양측에서 수직적으로 형성된 다수의 외부리이드(out lead)(11)로 이루어지며, 인쇄회로기판(PCB; Printed Circuit Board) 등과 같은 기판에서 홀 삽입형 기판에 셋트 실장시에는 외부리이드의 하단이 기판의 홀에 삽입되는 방법으로 실장된다.In an embodiment of the conventional semiconductor package, the DIP semiconductor package is formed with a molding body 10 in the form of a rectangular parallelepiped and vertically formed at both sides of the molding body, as shown in FIG. It consists of a plurality of external leads (out lead) 11, the lower end of the outer lead is inserted into the hole of the substrate when mounting the hole-insertable substrate in a substrate such as a printed circuit board (PCB) It is mounted.
그리고 종래의 반도체 패키지의 다른 실시예에서 에스오피형의 반도체 패키지는 제1도의 (b)에 도시된 바와 같이, 직육면체 형태로 된 몰딩체(10')와, 몰딩체의 양측에 형성되되 하단이 몰딩체의 바깥쪽으로 휘어지면서 형성된 다수의 외부리이드(11')로 이루어지며, 표면 실장형 기판에 실장된다.In another embodiment of the conventional semiconductor package, an SOP-type semiconductor package is formed on a molded body 10 'having a rectangular parallelepiped shape and on both sides of the molded body, as shown in FIG. It consists of a plurality of outer leads (11 ') formed while bending to the outside of the molding body, it is mounted on a surface-mount substrate.
이때, 몰딩체의 내부에는 리이드프레임패드(lead frame pad)에 안착된 반도체 칩(chip)과, 외부리이드가 연장된 내부리이드(inner lead)와, 반도체 칩과 내부리이드를 연결시키는 본딩와이어(bonding wire) 등이 형성되어 있다.(도면에 도시되지 않음)At this time, the inside of the molding body is a semiconductor chip seated on a lead frame pad, an inner lead with an outer lead extending, and a bonding wire connecting the semiconductor chip with the inner lead. wires, etc. (not shown).
그러나 종래의 반도체 패키지에 있어서는, 패키지의 셋팅 업체에서 인쇄회로 기판 등의 전환이 용이하지 않았으며, 또한 외부리이드가 몰딩체의 가장자리에서 바깥쪽으로 돌출되어 있으므로 기판에 실장시에 차지하는 면적이 증가되어 최종 셋트의 크기가 증가되었고, 이러한 요소는 표면적이 한정된 기판 상에 효율적인 셋트실장을 제한시키는 요인으로 대두되고 있다.However, in the conventional semiconductor package, it is not easy to switch the printed circuit board and the like in the package setting company, and since the outer lead protrudes outward from the edge of the molding body, the area occupied when mounting on the substrate increases. The size of the sets has increased, and these factors have emerged as a limiting factor for efficient set mounting on substrates with limited surface area.
본 발명은 이러한 문제를 해결하기 위해 안출된 것으로, 기판에 최소 실장면적을 갖도록 하면서, 선택적인 실장이 가능하도록 한 반도체 패키지를 제공하고자 하는 것이 그 목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a semiconductor package capable of selectively mounting while having a minimum mounting area on a substrate.
본 발명에 의한 반도체 패키지는 반도체칩이 안착되는 리이드프레임패드와, 리이드프레임패드의 가장자리에 다수 형성되되, 반도체칩의 상면과 평행한 면상에 형성되는 수평부와, 수평부가 아랫방향으로 연장되어 형성되는 수직부로 구분되어 형성되는 리이드와, 반도체칩과 리이드를 전기적으로 연결시키는 다수의 본딩와이어와, 반도체칩과 리이드를 애워싸면 형성되되, 리이드에서 수평부의 일단면 및 저면과 수직부의 바깥면이 노출되도록 형성되는 몰딩체를 포함하여 이루어진다.The semiconductor package according to the present invention includes a lead frame pad on which a semiconductor chip is seated, a plurality of horizontal frames formed on an edge of the lead frame pad, a horizontal portion formed on a surface parallel to the upper surface of the semiconductor chip, and a horizontal portion extending downward. Leads are formed by dividing the vertical portion, and a plurality of bonding wires electrically connecting the semiconductor chip and the lead, and formed by enclosing the semiconductor chip and the lead, where one end surface and the bottom surface of the horizontal portion and the outer surface of the vertical portion are exposed. It includes a molding formed to be.
제2도는 본 발명에 의한 반도체 패키지를 도시한 사시도 및 단면도로서, 제2도의 (a)는 사시도이며, 제2도의 (b)는 본 발명에 의한 반도체 패키지의 실시예를 도시한 단면도이고, 제2도의 (c)는 본 발명에 의한 반도체 패키지의 다른 실시예를 도시한 단면도이다. 이하 본 발명에 의한 반도체 패키지의 구조를 설명하면 다음과 같다.2 is a perspective view and a cross-sectional view showing a semiconductor package according to the present invention, Figure 2 (a) is a perspective view, Figure 2 (b) is a cross-sectional view showing an embodiment of the semiconductor package according to the present invention, 2C is a cross-sectional view showing another embodiment of the semiconductor package according to the present invention. Hereinafter, the structure of the semiconductor package according to the present invention will be described.
본 발명에 의한 반도체 패키지는 제2도의 (a)와 (b)와 같이, 반도체칩(20)이 안착되는 리이드프레임패드(21)와, 리이드프레임패드의 가장자리에 수평부(22-1)와 수직부(22-2)로 구분되는 T자의 형태로 다수 형성되되, 수직부는 수평부에서 리이드프레임패드와 가까운 쪽으로 치우쳐서 형성되는 리이드(22)와, 반도체칩과 각각의 리이드를 전기적으로 연결시키기 위하여 수평부의 일단 상면과 연결되는 다수의 본딩와이어(23)와, 반도체칩과 리이드를 애워싸면서 형성되되, ㄱ자의 형태의 리이드에서 수평부의 일단면 및 저면과 수직부의 바깥면이 노출되도록 형성되는 몰딩체(24)를 포함하여 이루어진다.According to the semiconductor package according to the present invention, as shown in FIGS. 2A and 2B, the lead frame pad 21 on which the semiconductor chip 20 is seated, the horizontal portion 22-1 and the edge of the lead frame pad, It is formed in a plurality of T-shape divided into the vertical portion 22-2, the vertical portion in the horizontal portion is formed to be biased toward the lead frame pad close to the semiconductor chip and each of the leads to electrically connect A plurality of bonding wires 23 connected to the upper surface of one end of the horizontal part, and formed while enclosing the semiconductor chip and the lead, wherein the molding is formed to expose one end surface of the horizontal part and the outer surface of the bottom part and the vertical part in the L-shaped lead. And a sieve 24.
또한 본 발명에 의해 반도체 패키지의 다른 실시예로서는 제2도의 (c)와 같이, 리이드(22)를 T자의 형태로 형성하되, 수직부(22-2)는 수평부(22-1)에서 리이드프레임패드(21)과 가까운 단에 형성되고, 수평부(22-1)는 일단 상면에는 본딩와이어(23)를 연결시킨다.According to another exemplary embodiment of the present invention, as shown in FIG. 2 (c), the lead 22 is formed in the shape of a T, but the vertical portion 22-2 is the horizontal frame 22-1 in the lead frame. It is formed at a stage close to the pad 21, and the horizontal portion 22-1 connects the bonding wire 23 to the upper surface thereof.
즉, 본 발명에 의한 반도체 패키지는 몰딩체를 리이드에서 수평부의 일단면 및 저면과 수직부의 바깥면이 노출되도록 형성하여, 리이드가 몰딩체의 가장자리에서 바깥쪽으로 노출되지 않게 형성되어 셋트실장시에 패키지의 실장면적을 최소화 시킬 수 있어서 최종 셋트의 크기를 감소시키며, 따라서 표면적이 한정된 기판 상에서 효율적으로 셋트실장을 할 수 있다.That is, in the semiconductor package according to the present invention, the molded body is formed such that one end surface and the bottom surface of the horizontal portion and the outer surface of the vertical portion are exposed in the lead, so that the lead is not exposed outward from the edge of the molding body so that the package is packaged at the time of mounting. It is possible to minimize the mounting area of the substrate, thereby reducing the size of the final set, and thus it is possible to efficiently set mount on a substrate having a limited surface area.
그리고 본 발명에 의한 반도체 패키지의 실장시에서는 패키지의 셋팅 업체에서 리이드의 노출된 수평부의 일단면 및 저면 또는 수직부의 측면을 이용하여 선택적으로 기판에 셋트실장을 시킬 수 있다.In the case of mounting the semiconductor package according to the present invention, the package setting company may selectively set the substrate on the substrate using one end surface and the bottom surface or the vertical side surface of the exposed horizontal portion of the lead.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043116A KR0161813B1 (en) | 1995-11-23 | 1995-11-23 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950043116A KR0161813B1 (en) | 1995-11-23 | 1995-11-23 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970030693A KR970030693A (en) | 1997-06-26 |
| KR0161813B1 true KR0161813B1 (en) | 1998-12-01 |
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ID=19435316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950043116A KR0161813B1 (en) | 1995-11-23 | 1995-11-23 | Semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR0161813B1 (en) |
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1995
- 1995-11-23 KR KR1019950043116A patent/KR0161813B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970030693A (en) | 1997-06-26 |
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