KR0157474B1 - Gold Alloys for Semiconductor Devices - Google Patents
Gold Alloys for Semiconductor Devices Download PDFInfo
- Publication number
- KR0157474B1 KR0157474B1 KR1019940005746A KR19940005746A KR0157474B1 KR 0157474 B1 KR0157474 B1 KR 0157474B1 KR 1019940005746 A KR1019940005746 A KR 1019940005746A KR 19940005746 A KR19940005746 A KR 19940005746A KR 0157474 B1 KR0157474 B1 KR 0157474B1
- Authority
- KR
- South Korea
- Prior art keywords
- gold
- yttrium
- beryllium
- ppm
- calcium
- Prior art date
Links
- 229910001020 Au alloy Inorganic materials 0.000 title claims abstract description 22
- 239000003353 gold alloy Substances 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052727 yttrium Inorganic materials 0.000 claims abstract description 27
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims abstract description 27
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052790 beryllium Inorganic materials 0.000 claims abstract description 20
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052791 calcium Inorganic materials 0.000 claims abstract description 19
- 239000011575 calcium Substances 0.000 claims abstract description 19
- 239000010931 gold Substances 0.000 claims abstract description 15
- 229910052737 gold Inorganic materials 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 238000002156 mixing Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000013329 compounding Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C5/00—Alloys based on noble metals
- C22C5/02—Alloys based on gold
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/012—Semiconductor purity grades
- H01L2924/01204—4N purity grades, i.e. 99.99%
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 반도체 소자용 금합금, 더 자세히는 주로 예컨대 반도체 소자상의 전극과 외부리드를 접합하기 위하여 사용하는 내열성이 뛰어난 본딩용 금선등에 사용되기에 유리한 반도체 소자용 금합금에 관한 것이다.BACKGROUND OF THE INVENTION The present invention relates to gold alloys for semiconductor devices, and more particularly, to gold alloys for semiconductor devices which are advantageously used for bonding gold wires having excellent heat resistance, for example, for bonding electrodes and external leads on semiconductor devices.
본 발명은 이트륨, 칼슘, 베릴륨, 납의 각 원소를 함유하여 이루어진 금합금에 있어서, 각각의 원소의 비율이 이트륨:칼슘:베릴륨:납=1:0.5~2.0:0.1~1.0:0.1~1.0의 범위내에 있고, 또한 이트륨의 최소량이 5중량ppm이상이고, 각각의 원소의 총량이 80중량ppm이하이고, 잔부가 불가피한 불순물과 금인 것을 특징으로 하는 반도체 소자용 금합금과 이트륨, 칼슘, 베릴륨, 납의 각 원소를 함유하여 이루어진 금합금에 있어서, 각각의 원소의 비율이 이트륨:칼슘:베릴륨:납=1:0.7~1.5:0.2~0.6:0.1~0.5의 범위내에 있고, 또한 이트륨이 10~30중량ppm이고, 각각의 원소의 총량이 20~60중량ppm이고, 잔부가 불가피한 불순물과 금인 것을 특징으로 하는 반도체 소자용 금합금을 제공한다.The present invention relates to a gold alloy containing yttrium, calcium, beryllium and lead, wherein the ratio of each element is within the range of yttrium: calcium: beryllium: lead = 1: 0.5 to 2.0: 0.1 to 1.0: 0.1 to 1.0 In addition, the minimum amount of yttrium is 5 ppm by weight or more, the total amount of each element is 80 ppm by weight or less, and the remainder is an inevitable impurity and gold alloy element, yttrium, calcium, beryllium, lead each element In the gold alloy containing, the ratio of each element is in the range of yttrium: calcium: beryllium: lead = 1: 0.7 to 1.5: 0.2 to 0.6: 0.1 to 0.5, and the yttrium is 10 to 30 ppm by weight, respectively. Provided is a gold alloy for a semiconductor device, characterized in that the total amount of elements is 20 to 60 ppm by weight, and the balance is inevitable impurities and gold.
Description
[발명의 명칭][Name of invention]
반도체 소자용 금합금Gold Alloys for Semiconductor Devices
[발명의 상세한 설명]Detailed description of the invention
[산업상의 이용분야][Industrial use]
본 발명은 반도체 소자용 금합금, 더 자세히는 주로 예컨대 반도체 소자상의 전극과 외부리드를 접합하기 위하여 사용하는 내열성이 뛰어난 본딩용금선 등에 사용되기에 유리한 반도체 소자용 금합금에 관한 것이다.BACKGROUND OF THE INVENTION The present invention relates to gold alloys for semiconductor devices, and more particularly, to gold alloys for semiconductor devices which are advantageously used for bonding wires having excellent heat resistance, for example, for bonding electrodes and external leads on semiconductor devices.
[종래의 기술][Prior art]
종래 예컨대 규소반도체 소자상의 전극과 외부리드와의 사이를 접속하는 본딩선으로서는 금세선(金細線)이 사용되어 왔다. 이와같이 금세선이 많이 사용되어온 것은 금볼의 형상이 진원구상으로 되어, 형성되는 금볼의 경도가 적절하여 접합시의 압력에 의하여 규소반도체 소자를 손상시키지 않고, 확실한 접속을 할수 있어서 그 신뢰성이 매우 높기 때문이었다. 그리고, 이러한 본딩용 금세선에 관해서는 이제까지도 많은 제안이 이루어져 있다.For example, a gold wire has been used as a bonding line for connecting between an electrode on a silicon semiconductor element and an external lead. The reason why gold wire has been used a lot is because the shape of the gold ball is a round sphere, the hardness of the formed gold ball is appropriate, and the reliability of the connection is very high without damaging the silicon semiconductor element due to the pressure at the time of bonding. It was. And many proposals are made | formed so far regarding such a bonding gold wire.
[발명이 해결하려고 하는 과제][Problems that the invention tries to solve]
그러나, 이들 많은 제안을 실용에 제공한 경우, 금세선을 자동본더에 걸어 금세선의 선단을 용융하여 금볼을 형성시켜서 접합을 행하면, 금세선을 재결정화 온도가 낮아 내열성이 결여되기 때문에, 금볼 형성의 직상부에서 인장강도가 부족하여 절단되거나, 절단되지 않고 접합되어도 접합후의 금세선은 수지봉지에 의하여 단선되거나, 또 반도체소자를 봉지용 수지로 보호한 경우, 와이어 플로우를 나타내어 단락을 일으키는 문제점이 있다.However, when many of these proposals are put into practical use, when the gold wire is connected to the automatic bonder and the tip of the gold wire is melted to form a gold ball for joining, the gold wire is low in recrystallization temperature and thus lacks heat resistance. Even if the upper part is cut due to lack of tensile strength or is bonded without being cut, the gold wire after the bonding is disconnected by the resin encapsulation or when the semiconductor element is protected by the encapsulating resin, there is a problem of causing a short circuit due to the wire flow. .
상기의 문제점을 해결하기 위하여 종래부터 접속시에 형성되는 금볼의 형상 및 경도를 손상시키지 않을 정도로 고순도금중에 미량의 첨가원소를 가하여 파단강도와 내열성을 향상시킨 여러가지의 본딩용 금세선이 공표되어 있는 것은 주지의 사실이다.In order to solve the above problems, various bonding gold wires have been published in which a small amount of additive elements are added to high-purity plating so as not to damage the shape and hardness of the gold balls formed at the time of connection, thereby improving breaking strength and heat resistance. It is a well known fact.
본 발명자들은 이들 제안된 여러가지 금세선들이 구체적으로 실용에 제공할 수 있는 것인가 아닌가에 대하여 검토하여 보았던바, 이들 종래의 여러가지 제안은 어느 것이나 최근 급속히 보급되고 있는 박형 패키지용 디바이스에 대응시키기에는 접합된 루프의 높이가 적절하지 않기 때문에 불충분하다는 문제점이 있는 것을 알아냈다.The present inventors have examined whether or not these proposed various gold wires can be practically provided for practical use, and these various conventional proposals have been bonded to correspond to the devices for thin package which are rapidly spreading recently. We found that the problem is that the loop is not adequate because the height is not appropriate.
이러한 검토의 결과를 근거로하여 본 발명자들은 예의 검토를 거듭한 결과, 이트륨, 칼슘, 베릴륨, 납의 각 원소를 함유하여 이루어진 금합금에 있어서, 각각의 원소의 비율이 이트륨:칼슘:베릴륨:납=1:0.5~2.0:0.1~1.0:0.1~1.0범위내에 있고, 또한 이트륨의 최소량이 5중량ppm 이상이고, 각각의 원소의 총량이 80중량 ppm이하로 함으로써, 접합의 루프높이를 현저히 낮게할 수 있는 것을 알아내어 본발명을 하기에 이르렀다.Based on the results of these studies, the present inventors earnestly studied, and in the gold alloy containing the elements of yttrium, calcium, beryllium, and lead, the ratio of each element was yttrium: calcium: beryllium: lead = 1. The loop height of the junction can be significantly lowered by being in the range of: 0.5 to 2.0: 0.1 to 1.0: 0.1 to 1.0, and the minimum amount of yttrium is 5 ppm by weight or more, and the total amount of each element is 80 ppm by weight or less. I found out that the present invention.
따라서, 본발명의 제1의 목적은 접합의 루프높이를 낮게할 수 있어서, 박형 패키지용 디바이스의 본딩선으로서 채용하는 경우, 이에 충분히 대응할 수 있는 반도체 소자용 금합금을 제공하는데 있다.Accordingly, a first object of the present invention is to provide a gold alloy for a semiconductor element that can reduce the loop height of a junction and can sufficiently cope with this when employed as a bonding line of a thin package device.
또, 제2의 목적은 접합의 루프높이를 현저히 낮게할 수 있어서 박형 패키지용 디바이스의 본딩선으로서 채용하는 경우, 실용상 이에 충분히 대응할 수 있는 반도체 소자용 금합금을 제공하는데 있다.A second object of the present invention is to provide a gold alloy for a semiconductor element that can significantly reduce the loop height of a junction and can be sufficiently used in practice when employed as a bonding wire of a thin package device.
[과제를 해결하기 위한 수단][Means for solving the problem]
상기의 목적을 달성하기 위하여 본발명은 두가지 수단을 채용하고 있다.In order to achieve the above object, the present invention employs two means.
제1의 수단은 이트륨, 칼슘, 베릴륨, 납의 각원소를 함유하여 이루어진 금합금에 있어서, 각각의 원소의 비율이 이트륨:칼슘:베릴륨:납=1:0.5~2.0:0.1~1.0:0.1~1.0의 범위내에 있고, 또한 이트륨의 최소량이 5중량ppm 이상이고, 각각의 원소의 총량이 80중량 ppm이하이고, 잔부가 불가피한 불순물과 금인 것을 특징으로 하는 것이다.The first means is a gold alloy containing yttrium, calcium, beryllium and lead elements, wherein the ratio of each element is yttrium: calcium: beryllium: lead = 1: 0.5 to 2.0: 0.1 to 1.0: 0.1 to 1.0. It is in the range, and the minimum amount of yttrium is 5 ppm by weight or more, the total amount of each element is 80 ppm by weight or less, and the balance is unavoidable impurities and gold.
또, 제2의 수단은 이트륨, 칼슘, 베릴륨, 납의 각원소를 함유하여 이루어진 금합금에 있어서, 각각의 원소의 비율이 이트륨:칼슘:베릴륨:납=1:0.7~1.5:0.2~0.6:0.1~0.5의 범위내에 있고, 또한 이트륨이 10~30중량ppm 이고, 각각의 원소의 총량이 20~60중량 ppm이고, 잔부가 불가피한 불순물과 금인 것을 특징으로 하는 것이다.The second means is a gold alloy containing yttrium, calcium, beryllium and lead elements, wherein the ratio of each element is yttrium: calcium: beryllium: lead = 1: 0.7 to 1.5: 0.2 to 0.6: 0.1 to It is in the range of 0.5, yttrium is 10-30 ppm by weight, the total amount of each element is 20-60 ppm by weight, and the balance is unavoidable impurities and gold.
이트륨의 첨가량이 5중량ppm이하일 때에는 내열성이 향상되지 않고, 봉지수지의 영향을 받아 와이어 플로우를 나타내며, 또한 루프높이에 불균일이 생겨 불안정한 접합으로 되므로, 최소량은 5중량ppm이상으로 정하였다. 그리고, 바람직하기는 10~30중량ppm이다.When the addition amount of yttrium was 5 ppm by weight or less, the heat resistance was not improved, and the wire flow was shown under the influence of the encapsulating resin, and the unevenness occurred at the loop height, resulting in an unstable joint, so the minimum amount was set to 5 ppm by weight or more. And preferably, it is 10-30 weight ppm.
이트륨에 대한 칼슘의 첨가배합비율이 0.5미만일 때에는 이트륨과 베릴륨과의 상승작용이 결여되어, 내열성이 불안정하게 되고, 루프높이에 불균일이 생겨 약간의 와이어 플로우를 나타낸다. 반대로, 2.0을 넘으면 볼표면에 산화피막이 형성되어, 볼형상에 왜곡이 생기며, 또한 칼슘이 금의 결정입계에 석출되어 취성이 생겨, 신성가공에 지장이 생긴다. 따라서 첨가배합비율의 범위는 0.5~2.0으로 정하였다.When the addition ratio of calcium to yttrium is less than 0.5, the synergy between yttrium and beryllium is lacking, the heat resistance becomes unstable, and unevenness occurs in the loop height, thereby showing a slight wire flow. On the contrary, if it exceeds 2.0, an oxide film is formed on the surface of the ball, distortion occurs in the shape of the ball, and calcium precipitates at the grain boundaries of gold, causing brittleness, which causes trouble in the sacred processing. Therefore, the range of addition ratio was set at 0.5 to 2.0.
그리고, 바람직한 범위는 0.8~1.5이다And the preferable range is 0.8-1.5
베릴륨의 이트륨이나 칼슘에 대한 첨가배합비율이 0.1미만일 때에는 상온의 기계적 강도를 더 향상시킬 수 없다. 반대로 1.0을 넘으면 볼표면에 산화피막이 형성되어, 볼형상에 왜곡이 생기며, 또한 베릴륨이 금의 결정입계에 석출되어 취성이 생겨서 신선가공에 지장이 생긴다. 따라서, 첨가배합비율의 범위는 0.1~1.0으로 정하였다.When the addition ratio of beryllium to yttrium or calcium is less than 0.1, the mechanical strength at room temperature cannot be further improved. On the contrary, if it exceeds 1.0, an oxide film is formed on the surface of the ball, distortion occurs in the shape of the ball, and beryllium precipitates at the grain boundaries of gold, causing brittleness, which causes problems in fresh processing. Therefore, the range of addition compounding ratio was set to 0.1-1.0.
그리고, 바람직한 범위는 0.2~0.6이다.And a preferable range is 0.2-0.6.
납의 이트륨이나 칼슘 그리고 베릴륨에 대한 배합비율이 0.1미만일 때에는 효과가 생기지 않는다. 반대로 배합비율이 높아질수록 상온강도, 고온강도가 모두 높아지나, 1.0을 넘으면 볼형상에 왜곡이 생겨, 진구도가 나빠지므로 1.0이하로 하고, 첨가배합 비율의 범위는 0.1~1.0으로 정하였다. 그리고, 바람직한 범위는 0.1~0.5이다. 그리고, 각각의 원소의 총량은 80중량ppm이하이다. 80중량ppm을 넘으면, 볼표면에 형성된 첨가물 원소의 산화피막이 볼형상에 영향(캐비티의 발생)을 주어, 진구가 되지 않게 된다. 그리고, 바람직한 범위는 20~60중량ppm이다.It does not work when the blending ratio of lead to yttrium, calcium and beryllium is less than 0.1. On the contrary, the higher the blending ratio, the higher the room temperature strength and the high temperature strength. However, when the mixing ratio is higher than 1.0, distortion occurs in the shape of the ball and the sphericity becomes worse. Therefore, the mixing ratio is set to 1.0 or less. And a preferable range is 0.1-0.5. The total amount of each element is 80 ppm by weight or less. If it exceeds 80 ppm by weight, the oxide film of the additive element formed on the surface of the ball affects the shape of the ball (occurrence of the cavity), and becomes no true bulb. And a preferable range is 20-60 ppm by weight.
[실시예]EXAMPLE
이하, 실시예에 대하여 설명한다.Hereinafter, an Example is described.
금순도가 99.99중량%이상인 전해금을 사용하여 표1에 표시한 화학성분의 금합금을 고주파 진공용해로에 용해주조하여, 그 주괴를 압연한 후, 상온에서 신성가공을 행하여 최종선 직경을 25㎛ø의 금합금 세선으로 하고, 소둔하여 신장치가 4%로 되도록 조질한다.Gold alloys of the chemical composition shown in Table 1 were melted and cast in a high frequency vacuum melting furnace using an electrolytic gold with a purity of 99.99% by weight or more, and the ingot was rolled, and then subjected to a new processing at room temperature to obtain a final wire diameter of 25 μmø. It is made of fine alloy alloy and annealed so that the new equipment is 4%.
[표 1]TABLE 1
얻어진 금합금 세선에 대하여 상온인장강도, 고온인장강도(250°, 20초 유지), 접합한 루프높이, 모울드시의 와이어풀로우 및 볼형상을 조사한 결과를 표 2에 표시하였다.Table 2 shows the results obtained by examining the tensile strength at room temperature, the tensile strength at high temperature (250 °, maintained for 20 seconds), the bonded loop height, the wire pull and mold shape at the mold.
[표 2]TABLE 2
접합의 루프높이는 고속자동 본더를 사용하여 반도체 소자상의 전극과 외부리드와의 사이를 접합한 후, 형성되는 루프정상부의 높이와 칩의 전극면을 광학현미경으로 관찰하여 그 높이를 측정한다.The loop height of the junction is a junction between the electrode on the semiconductor element and the external lead using a high-speed automatic bonder, and then the height of the loop top formed and the electrode surface of the chip are observed by an optical microscope to measure the height.
와이어플로우는 고속자동 본더로 반도체 소자상의 전극과 외부리드를 접합하여, 박형모울드의 금형내에 세트하여 봉지용수지를 주입한 후, 얻어진 패키지를 X선을 관찰하여, 봉지용 수지에 의한 본딩선의 왜곡, 즉, 직선접합으로 부터의 최대 만곡거리(h)와 접합스판 거리(l)를 측정하여, 왜곡치(h/l×100)로 부터 와이어플로우의 양호불량을 평가하였다.Wireflow is a high-speed automatic bonder, which joins electrodes on semiconductor elements and external leads, sets them in a mold of a thin mold, injects encapsulating resin, and observes X-rays of the resulting package. That is, the maximum bending distance (h) and the bonding span distance (l) from the linear joint were measured, and the poor quality of the wire flow was evaluated from the distortion value (h / l × 100).
○표 : 왜곡치 3%미만(박형 패키지에 적합하다)○ Table: Less than 3% distortion (suitable for thin packages)
△표 : 왜곡치 3~10%△ Table: Distortion value 3 ~ 10%
×표 : 왜곡치 11%이상× Table: 11% distortion
볼형상은 고속자동본더를 사용하여, 전기토치 방전에 의하여 얻어지는 금합금볼을 주사전자현미경으로 관찰하여, 그 외관, 진구도, 캐비티의 세가지 관점에서 평가하였다. 먼저, 외관에 대하여는 볼표면에 산화물이 생기는 상태에 의하여 양호불량의 판단을 하였다.The ball shape was evaluated by using a high-speed automatic bonder, the gold alloy ball obtained by the electric torch discharge by scanning electron microscope, and the three aspects of appearance, sphericity, and cavity. First, regarding the appearance, good or bad was judged by the state in which oxides were formed on the ball surface.
○표 : 볼표면이 매끄럽다.○ Table: Ball surface is smooth.
△표 : 볼표면에 약간 산화물이 인정된다.(Triangle | delta) table | surface: Oxide is recognized by the ball surface slightly.
×표 : 볼표면에 명백히 산화물이 인정된다.X Table: An oxide is clearly recognized on the ball surface.
다음에 진구도에 대하여는 선직경의 약 3배 (75㎛ø)의 볼을 제작하였을 때의 긴직경(㎛)과 짧은 직경(㎛)과의 차에 의하여 양호불량의 판단을 하였다.Next, about the sphericity, the defect was judged by the difference between the long diameter (micrometer) and the short diameter (micrometer) at the time of making the ball about three times (75 micrometer (phi)) of the linear diameter.
○표 : 3㎛ 이하○ Table: 3㎛ or less
△표 : 3~6㎛△ Table: 3 ~ 6㎛
×표 : 6㎛ 이상Table: 6 µm or more
끝으로, 캐비티에 대해서는 볼바닥부에 캐비티의 발생 상황에 의하여 양호불량의 판단을 하였다.Finally, the cavity was judged to be inferior due to the occurrence of the cavity at the bottom of the ball.
○표 : 전혀 인정되지 않는다.○ Table: Not accepted at all.
△표 : 약간 인정된다.(Triangle | delta): It is recognized slightly.
×표 : 뚜렷이 인정된다.X mark: Appeared clearly.
결과로 부터 이해되는 바와같이, 본발명의 실시예 4~10은 이트륨, 칼슘, 베릴륨, 납의 각 원소의 배합비율 및 각 원소의 총량, 그리고 불가피한 불순물의 첨가량이 이상적이기 때문에, 내열성이 양호하고, 상온 및 고온강도가 높아, 접합 루프높이를 낮게 형성할 수 있어서, 봉지수지에 의한 와이어 플로우의 영향도 무시할 수 있고, 또한 볼형상도 양호하기 때문에 신뢰성이 있는 접합이 가능하게 되었다. 또, 실시예1은 원소의 총량이 바람직한 범위를 약간 하회하고 있어서, 루프높이가 상기 실시예4~10에 비하여 약간 높게되어 왜곡치가 3~10%로 되었으나, 실용상 특별한 불편은 없었다. 또, 실시예 2,3 및 11은 원소의 총량이 바람직한 범위를 약간 상회하고 있어서, 긴 직경과 짧은 직경의 차가 3~6㎛이 되고, 또 캐비티는 약간 인정되었으나, 실용상 특별한 불편은 없었다. 이 결과로 부터 표1에 표시된 실시예 1~11의 범위내이면 실용상 특별한 불편은 없다고 판단된다. 다만, 바람직하기는 실시예 4~10의 범위내인 경우에는 본 발명의 소기의 목적이 이상적으로 달성된다.As can be understood from the results, Examples 4 to 10 of the present invention have good heat resistance since the compounding ratio of yttrium, calcium, beryllium and lead, the total amount of each element, and the amount of addition of unavoidable impurities are ideal. Since the room temperature and the high temperature strength are high, the joining loop height can be formed low, the influence of the wire flow due to the encapsulating resin can be ignored, and the ball shape is also good, so that reliable joining can be achieved. In Example 1, the total amount of elements was slightly below the preferred range, and the loop height was slightly higher than that of Examples 4 to 10, resulting in a distortion value of 3 to 10%, but there was no particular inconvenience in practical use. In Examples 2, 3 and 11, the total amount of elements slightly exceeded the preferred range, and the difference between the long and short diameters was 3 to 6 µm, and the cavity was slightly recognized, but there was no particular inconvenience in practical use. From this result, it is judged that there is no particular inconvenience in practical use if it is in the range of Examples 1-11 shown in Table 1. However, preferably in the case of the range of Examples 4-10, the desired objective of this invention is ideally achieved.
이상의 본 발명에 대하여 비교예1은 원소의 총량이 5.1이므로 극단으로 적고, 루프높이가 훨씬 높아지고 와이어플로우가 생겨 실용에 제공할 수 없었다.With respect to the present invention described above, Comparative Example 1 is extremely low because the total amount of elements is 5.1, the loop height is much higher, and wire flow occurs, and thus it cannot be used for practical use.
또, 비교예2~3은 모두 원소의 총량이 허용한도를 초과하고, 또 비교예3은 더욱이 베릴륨과 납의 배합비율이 허용한도를 크게 일탈하고 있기 때문에, 어느 것도 볼형상이 좋지 않아 실용에 제공할 수 없었다.In Comparative Examples 2 to 3, the total amount of the elements exceeded the allowable limit, and in Comparative Example 3, since the compounding ratio of beryllium and lead was greatly deviated from the allowable limit, none of them had a poor ball shape, so they were practically provided. I could not.
[발명의 효과][Effects of the Invention]
이상 설명한 바와같이, 본 제1발명의 반도체 소자용 금합금은 상온 및 고온 인장강도가 모두 뛰어나, 접합의 루프높이를 낮게 형성할 수 있고, 봉지수지에 의한 와이어 플로우도 작고, 고속자동 본더에 충분히 대응할 수 있음과 동시에 형성되는 볼형상도 거의 만족할 수 있는 진구이므로, 특히 박형 패키지용 디바이스의 본딩선으로서 채용하는 경우에는 신뢰성이 높아 실용에 충분히 제공할 수 있어서, 산업이용상 다대한 가치를 갖고 있다.As described above, the gold alloy for semiconductor device of the present invention is excellent in both the normal temperature and the high temperature tensile strength, and can form a low loop height of the junction, and the wire flow by the encapsulation resin is small, and it is sufficient to cope with the high speed automatic bonder. Since the ball shape can be almost satisfied with the ball shape, it is highly reliable and can be provided sufficiently for practical use, especially when it is used as a bonding wire of a device for thin packages, and has great value for industrial use.
또, 본 제2발명에 관한 반도체 소자용 금합금은 상온 및 고온 인장강도가 모두 훨씬 뛰어나서, 접합루프높이를 현저히 낮게 형성할 수 있고, 봉지수지에 의한 와이어 플로우도 없고, 고속자동 본더에 충분히 대응할 수 있음과 동시에 형성되는 볼형상도 만족할 수 있는 진구이므로, 특히 박형 패키지용 디바이스의 본딩선으로서 채용하는 경우에는 신뢰성이 높고, 실용에 충분히 제공할 수 있어서, 산업이용상 다대한 가치를 갖고 있다.In addition, the gold alloy for semiconductor element according to the second invention is much superior in both the normal temperature and the high temperature tensile strength, so that the junction loop height can be formed significantly lower, there is no wire flow by the encapsulating resin, and it can cope with the high speed automatic bonder sufficiently. Since the ball shape, which is formed at the same time, can also be satisfied, it is highly reliable when used as a bonding wire of a device for a thin package, and can be sufficiently provided for practical use, which has great value for industrial use.
Claims (2)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP93-98882 | 1993-03-31 | ||
JP9888293 | 1993-03-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940022687A KR940022687A (en) | 1994-10-21 |
KR0157474B1 true KR0157474B1 (en) | 1998-12-01 |
Family
ID=14231528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940005746A KR0157474B1 (en) | 1993-03-31 | 1994-03-22 | Gold Alloys for Semiconductor Devices |
Country Status (4)
Country | Link |
---|---|
KR (1) | KR0157474B1 (en) |
GB (1) | GB2276632B (en) |
SG (1) | SG44578A1 (en) |
TW (1) | TW284791B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5945065A (en) * | 1996-07-31 | 1999-08-31 | Tanaka Denshi Kogyo | Method for wedge bonding using a gold alloy wire |
-
1994
- 1994-03-18 TW TW083102381A patent/TW284791B/zh active
- 1994-03-22 KR KR1019940005746A patent/KR0157474B1/en not_active IP Right Cessation
- 1994-03-24 SG SG1996003005A patent/SG44578A1/en unknown
- 1994-03-24 GB GB9405839A patent/GB2276632B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2276632A (en) | 1994-10-05 |
SG44578A1 (en) | 1997-12-19 |
TW284791B (en) | 1996-09-01 |
KR940022687A (en) | 1994-10-21 |
GB2276632B (en) | 1996-02-28 |
GB9405839D0 (en) | 1994-05-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6210637B1 (en) | Gold alloy thin wire for semiconductor devices | |
JPS62127438A (en) | Bonding wire for semiconductor device | |
KR0157474B1 (en) | Gold Alloys for Semiconductor Devices | |
JP3579493B2 (en) | Gold alloy wires for semiconductor devices | |
JPS63211731A (en) | Bonding wire | |
JP3811600B2 (en) | Semiconductor element gold alloy wire | |
JP3779817B2 (en) | Gold alloy wire for semiconductor elements | |
JP3028458B2 (en) | Gold alloy wires for semiconductor devices | |
JP3346871B2 (en) | Gold alloy for semiconductor devices | |
JPH07335686A (en) | Gold alloy fine wire for bonding | |
CN101601126B (en) | Gold alloy wire for ball bonding | |
JP3012466B2 (en) | Gold alloy wires for semiconductor devices | |
JPH02219249A (en) | Gold alloy thin wire for bonding | |
JPH1167812A (en) | Gold and silver alloy wires for semiconductor devices | |
KR0145549B1 (en) | Gold alloy wire for bonding semiconductor device | |
JP3426397B2 (en) | Gold alloy fine wire for semiconductor devices | |
JPH02205641A (en) | Gold alloy thin wire for bonding | |
JP3426399B2 (en) | Gold alloy fine wire for semiconductor devices | |
JP3535657B2 (en) | Gold alloy wire for semiconductor elements | |
JP3120940B2 (en) | Spherical bump for semiconductor device | |
JP3586909B2 (en) | Bonding wire | |
JPH02250934A (en) | Au alloy extra fine wire for bonding semiconductor device | |
JPH0719788B2 (en) | Gold alloy fine wire for bonding | |
JPH0530892B2 (en) | ||
JPS62127437A (en) | Bonding wire for semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19940322 |
|
PG1501 | Laying open of application | ||
A201 | Request for examination | ||
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19950830 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19940322 Comment text: Patent Application |
|
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19980430 |
|
GRNT | Written decision to grant | ||
PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19980730 Patent event code: PR07011E01D |
|
PR1002 | Payment of registration fee |
Payment date: 19980730 End annual number: 3 Start annual number: 1 |
|
PG1601 | Publication of registration | ||
PR1001 | Payment of annual fee |
Payment date: 20010725 Start annual number: 4 End annual number: 4 |
|
PR1001 | Payment of annual fee |
Payment date: 20020722 Start annual number: 5 End annual number: 5 |
|
FPAY | Annual fee payment |
Payment date: 20030722 Year of fee payment: 6 |
|
PR1001 | Payment of annual fee |
Payment date: 20030722 Start annual number: 6 End annual number: 6 |
|
LAPS | Lapse due to unpaid annual fee | ||
PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20050409 |