KR0155529B1 - Parallel optical logic operator - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel optical logic processing system that minimizes the path of light by densely arranging surface emitting lasers, optical logic elements, and microlens arrays vertically. The purpose of the present invention is to provide a parallel optical logic processing system that improves the integration efficiency by eliminating the components that change the path by providing an optical path through which the light can pass and operate linearly. have.

Description

Parallel optical logic processing system

1 is a cross-sectional view of the entire structure of a parallel optical logic processing system according to the present invention.

2 is a cross-sectional view of a detailed structure in a unit chip according to the present invention.

3 is a plan view of the laser two-dimensional array according to the present invention.

4 is an explanatory diagram of signal processing for a logic function in the present invention.

* Explanation of symbols for main parts of the drawings

1: Surface-emitting laser array for initial data input

2: surface emitting laser array with light through hole

3: microlens array 4: photological element array

5: Unit chip 6: Minimum unit of logic execution in unit chip

7: surface emitting laser element 8: microlens

9: window of light management circuit 10: junction

11: laser light 12: light through hole

a, b: pair of optical signals for arithmetic processing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical logic processing system, and to a parallel optical logic processing system that minimizes the path of light while vertically arranging surface emitting lasers, optical logic elements, and microlens arrays.

Parallel optical logic processing systems such as optical computers require efficient integration of light sources that emit light, optical logic devices that operate on light, and passive optical components that control light paths.

Here, the parts that control the path of light are so large that the space is larger than that of other devices, which places the greatest limitation on the integration of the whole system.

Parallel optical logic processing systems designed up to now use optical path control or optical splitter that separates light into two vertical paths.

However, these optical fibers and optical splitters take up a lot of space, and the size of the entire system becomes so large that it is not practical as an optical computer.

Accordingly, the present invention provides a path through which light can pass linearly through a substrate having a light source and an optical logic element, and also changes the path of light by using an optical logic element that can be operated while the light proceeds linearly. The purpose of the present invention is to provide a parallel optical logic processing system with high integration efficiency by eliminating components.

In order to achieve the above object, the present invention is a laser array comprising a plurality of lasers for emitting light of intensity corresponding to the information to be processed; A micro lens array positioned next to the reiser, the micro lens array comprising a plurality of micro lenses for converting light emitted from the laser into parallel light; And between the micro lens array and the laser array of the next stage, and performs information on the light corresponding to the laser light propagated through the micro lens using optical bistable by an all-optical effect. A unit chip composed of an optical logic element array for absorbing or passing the parallel light into and inputting data of 1 or 0 is vertically stacked so that light proceeds linearly in each logic execution step and is located next to the laser. And a light through hole for allowing the light emitted from the laser to reach the optical logic device via the micro lens.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of the entire structure of a parallel optical logic processing system according to the present invention, FIG. 2 is a cross-sectional view of a detailed structure in a unit chip according to the present invention, and FIG. 3 is a plan view of a laser two-dimensional array according to the present invention.

1, 2 and 3, 1 is a surface emitting laser array for initial data history, 2 is a surface emitting laser array with light through holes, 3 is a microrend array, 4 is an optical logic device array, and Is the unit chip, 6 is the minimum unit of logic performance within the unit chip, 7 is the surface emitting laser element, 8 is the microlens, 9 is the window of the optical logic circuit, 10 is the junction, 11 is the laser light, 12 is the light through hole, a b denotes a pair of optical signals for arithmetic processing, respectively.

The structure of the present invention will be described with reference to FIG. 1 and FIG.

In the structure of the present invention, a vertical cavity surface-emitting laser (VCSEL) array is used as the light source.

The optical logic device uses a SEED (Self Electrooptic Effect Device) array that performs logic functions using optical bistable stability due to all-optical effects.

The SEED can be divided into a reflection type and a transmission type according to the path of the light. In the present invention, the transmission type SEED is used to maintain the progress of light in one direction.

In addition, microlens arrays are used to reduce the divergence of light propagation.

Here, an array means a laser array, a photological element, or a lens arrange | positioned regularly on a two-dimensional plane substrate.

The arrangement of each array component is described in FIG.

The basic arrangement is in order of the surface emitting laser array 2 having the light through hole, the microlens array 3, and the light transmissive logic element error 4, like the hatched portion 5 of FIG.

The three arrays are combined to form a unit chip 5 that performs a specific logic function, and arithmetic processing for various logic functions is performed by repeatedly stacking this unit chip.

The change in logic function in each unit chip is utilized by changing the internal circuit of the optical logic element array 4.

However, only the initial data input laser array 1 is arranged in front of the first unit chip as shown in FIG.

The detailed structure of the array components in the unit chip 5 is shown in FIG.

Representatively selecting only the logic performing minimum unit 6 using a pair of micro lasers (a, b) of the two-dimensional array is as follows.

The unit chip 5 to which the logic performing minimum unit 6 of FIG. 2 belongs is referred to as N-th unit chip for convenience.

In order to allow the laser light 11 oscillated from the (N-1) unit chip to pass through to the laser array substrate 2 in the Nth unit chip, each laser unit element 7 as shown in the plan view of FIG. Next, the light through hole 12 is made.

The microlens array 3 or single microlens 8 is made by etching concentric grooves on the glass substrate using the principle of Fresnel lens.

The laser array substrate 2, the microlens substrate 3, and the optical non-array substrate 4 are fixed to each other by the bonding portion 10 as shown in FIG.

The focus of the microlens is such that the light from the lasers (a, b) of the Nth unit chip 5 passes through the microlens 8 to be parallel light, and the window 9 of the optical logic element in the Nth unit chip 5 The light enters the window 9 of the optical logic circuit in the (N + 1) th unit chip.

Each logic circuit is constructed using a conventional AND, OR, NOR, and NAND circuit using a SEED element.

4 is an explanatory diagram of signal processing for a logic function in the present invention.

With reference to FIG. 4, the operation principle of the present invention will be described below.

First, the optical signal system will be described.

A binary or zero optical signal is used using a pair of laser lights a and b.

For example, as shown in FIG. 4A, a state in which the intensity of a is large among the pair of laser lights a and b may be set to 1.

Here, the two light intensities are each within a range that can be converted into a light bistable state where light is absorbed or passed through the SEED optical logic circuit.

Next, the optical signal input will be described.

The first optical signal input oscillates the light having the signal of FIG. 4 (a) from a pair of lasers in the initial laser array 1, and inputs data into the window 9 of the optical logic circuit in the next unit chip. do.

The optical signal input thereafter inputs the optical signal from the window of the (N-1) th optical logic circuit through the through hole in the Nth laser array and into the window of the Nth optical logic circuit.

This light passing through the window of the Nth optical logic circuit is extinguished as the (N + 1) th array array substrate enters the back side and is absorbed in the substrate.

Next, the logic performance will be described.

The optical signal from the (N-1) th optical logic circuit is input to perform the logic operation in the Nth optical logic circuit, and the data resulting from the logic performance causes the Nth optical logic circuit to absorb or pass light through the window. Save as.

Here, the state which absorbs light is defined as OFF, and the state which passes is defined as ON.

Next, the optical signal output will be described.

In a pair of lasers within the Nth unit chip, as shown in FIG. 4B, both oscillate light having high intensity and read the stored data while passing through the window of the Nth optical logic circuit.

When the window of the Nth optical logic circuit is in an ON state, the light intensity is maintained after passing through the window, and is output as an optical signal corresponding to a high intensity in FIG.

When passing through the window in the OFF state, most of the light is absorbed and output as an optical signal having a low intensity in (a) of FIG.

The optical signal output here is input to the (N + 1) th optical logic circuit again.

At this time, since the data is stored in the SEED optical logic circuit is limited to silver time of the nano (10 ^-9 ) seconds, the corresponding time difference is required for the input and output of the data.

That is, if data of the ON or OFF state is stored in the window after performing logic operation in the Nth optical logic circuit as the (N-1) th laser input, light is emitted from the Nth laser with a time difference within the time when this data disappears. Read the stored data.

According to the present invention described above, the following effects can be obtained.

First, by making a light through the laser array substrate, it is possible to solve the problem of the loss of light and the progress of light by the substrate.

In particular, when using a wavelength at which laser light is absorbed by the substrate, the light through hole becomes an effective structure for providing an optical path.

Second, since the light proceeds linearly in each logic execution step, there is no need for a part that changes the path of the light.

Third, it is possible to maximize the integration efficiency by densely stacking the planar array components vertically, and to configure a large capacity parallel signal processing system.

Claims (4)

A laser array consisting of a plurality of lasers emitting light of intensity corresponding to information to be logic processed; A micro lens array positioned next to the laser, the micro lens array comprising a plurality of micro lenses for converting light emitted from the laser into parallel light; And between the microlens array and the laser array of the next stage, and performing a logic function by using optical bistable by an all-optical effect on information corresponding to the light of the laser which has been advanced through the microlens. A unit chip composed of an optical logic element array for absorbing or passing the parallel light into and inputting data of 1 or 0 is vertically stacked so that light travels linearly in each logic execution step and is located next to the laser. And a light through hole for allowing the light emitted by the laser to reach the optical logic device via the micro lens. According to claim 1, wherein the light source uses a vertical resonance type surface emitting laser array, and parallel optical logic, characterized in that the optical through-holes are formed next to each laser element so that the light from the previous stage chip passes through the laser substrate. Processing system. The parallel optical logic processing system according to claim 1, wherein an input laser array for inputting initial data is added in front of the first unit chip. 2. The parallel optical logic processing system according to claim 1, wherein each micro lens constituting the micro lens array is made by etching concentric grooves on a glass substrate using the principle of Fresnel lens.