KR0147667B1 - Manufacturing Method of Semiconductor Device Using Different Spacer Length - Google Patents

Abstract

A method for manufacturing a semiconductor device using different spacer lengths is described.

The present invention provides a method of manufacturing a semiconductor device using different spacer lengths in NMOS and PMOS regions of a cell array portion and a peripheral circuit portion, respectively, by forming spacers by etching and source / drain ion implantation after masking the respective regions. A first embodiment of forming a transistor and a second embodiment of forming a spacer and a poly pad of a cell array region first, followed by a spacer of an NMOS and PMOS region to complete a transistor. Therefore, not only can each transistor have suitable electrical characteristics by spacers of different lengths, but also spacer formation and source / drain ion implantation are consistently performed, thus eliminating the need for a separate mask and simplifying the process.

Description

Manufacturing Method of Semiconductor Device Using Different Spacer Length

1A to 1E are process charts for forming a semiconductor device according to the prior art.

2A through 8C are process diagrams for forming a semiconductor device according to the first embodiment of the present invention.

9A to 14C are process charts for forming a semiconductor device according to the second embodiment of the present generation.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using different spacer lengths.

The first requirement in realizing VLSI is to reduce the size of the device. However, reducing the size of the device poses a problem of short-channel effects, including variations in device characteristics due to hot carrier injection.

As a countermeasure for this, the LDD (Lightly Doped Drain) structure may be mentioned. The structure is realized by low concentration ion implantation into the portion self-aligned by a common gate electrode and high concentration ion implantation into the portion self-aligned by a spacer.

On the other hand, as the degree of integration of circuits becomes more advanced, the thickness and width of word lines are gradually reduced, and their lengths are gradually increased, resulting in more line resistance. Therefore, the increase in the propagation delay time (τ = RC) of the problem has been a problem, so the need for a word line material having a low resistivity for the reduction thereof has emerged strongly. This necessity led to the use of tungsten polysides (WSix) as materials with low resistivity.

In the fabrication of transistors using a conventional poly gate that blankets N-ion implants for the NMOS LDD structure, even if the thickness of the oxide for forming spacers is the same for both NMOS and PMOS, there is no problem in the transistor's electrical characteristics. In transistor manufacturing using tungsten polyside gate, a non-overlap of the gate and the source / drain does not overlap in the source / drain region of the PMOS transistor, thereby controlling the electrical characteristics (threshold voltage) of the PMOS transistor. There was a problem that was difficult to do.

Therefore, in order to solve this problem, a method of fabricating a transistor of a semiconductor device has been proposed in which spacers having different lengths between NMOS and PMOS are formed to have suitable electrical characteristics for each transistor.

Here, the prior art will be described in the method for manufacturing a semiconductor device using different spacer lengths.

1A to 1E are diagrams illustrating a semiconductor device forming step according to the prior art.

FIG. 1A is a view showing a step before forming a gate electrode. After forming the field oxide film 2 and the gate oxide film 3 on the semiconductor substrate 1, the polysilicon film 4 and the silicide layer 5 having a uniform thickness are formed. ) Is shown in the first step of forming the NMOS and PMOS regions.

FIG. 1B is a view illustrating a step in which a low concentration ion implantation is performed to form an LDD structure after forming a gate electrode. The polysilicon film 4 and the silicide layer 5 are formed in a predetermined size after the first step. By patterning, the same gate electrodes 6 and 7 are formed in the NMOS and PMOS regions, and an N- / P-LDD ion implantation region is implanted by implanting a desired amount of impurities using an N + mask in the NMOS region and a P + mask in the PMOS region. It consists of a second step of forming (8,9).

FIG. 1C is a view showing the step of forming the spacer oxide film 10 and the step forming photosensitive film 11. The oxide film 10 is deposited on the resultant material after the second step, and the PMOS region is formed by using an N + mask. It consists of a third step of shielding with (11).

FIG. 1D illustrates a step of etching the spacer oxide film 10. A portion of the oxide film 10 exposed by the photoresist film 11 formed on the PMOS region after the third step is etched to form a PMOS region. The fourth step is to form the oxide film 10 lower than the PMOS region.

FIG. 1E illustrates a step of forming spacers having different lengths. After the fourth step, the oxide film 10 having the step difference is etched to form two sidewall spacers 12A and 12B having different lengths in the NMOS and PMOS regions, respectively. The fifth step is to form.

As described above, the conventional device fabrication method requires a separate mask operation to form a step in the oxide film 10 of the NMOS region and the PMOS region.

Accordingly, it is an object of the present invention to provide an efficient manufacturing method that simplifies the mask process as well as having suitable electrical characteristics for each transistor by using spacers having different lengths in forming transistors of a semiconductor device.

The present invention to achieve the above object,

A method of manufacturing a semiconductor device having different spacers in a cell array, an NMOS, and a PMOS region, the method comprising: a first step of sequentially depositing a gate oxide film, a low resistance conductive layer for a gate electrode, and an oxide film having an appropriate thickness on a semiconductor substrate; A second step of patterning a gate electrode to a predetermined size after the first step, and then performing N-ion implantation on the entire surface of the NMOS, PMOS, or cell array to form an LDD structure; A third step of forming an NMOS spacer by depositing a first oxide film for forming a spacer after the second step and etching by using an N + source / drain mask; A fourth step of forming an NMOS transistor by performing N + source / drain ion implantation after the third step; A fifth step of wet etching the first oxide layer to a predetermined thickness in order to completely overlap the gate electrode and the source / drain in the source / drain of the PMOS transistor after the fourth step; A sixth step of forming a PMOS spacer by etching the first oxide film wet after the fifth step using a P + source / drain mask; A seventh step of forming a PMOS transistor using P + source / drain ion implantation after the sixth step; And an eighth step of forming a cell array spacer by etching the second oxide layer after the seventh step by etching the cell open mask.

In order to achieve the above object, the present invention also provides

A method of manufacturing a semiconductor device having different spacers in a cell array, an NMOS, and a PMOS region, the method comprising: a first step of sequentially depositing a gate oxide film, a low resistance conductive layer for a gate electrode, and an oxide film having an appropriate thickness on a semiconductor substrate; After the first step, after patterning the gate electrode to a predetermined size, a second step of performing N-ion implantation for forming an LDD structure on the entire surface of the NMOS, PMOS, and cell arrays, and a third step for forming spacers after the second step Depositing an oxide film; A fourth step of forming a cell array spacer by etching by using a cell open mask after the third step; Depositing and etching polysilicon after the fourth step to form a poly pad in the capacitor contact portion and the bit line contact region; A sixth step of forming an NMOS transistor by etching the N + source / drain mask using the N + source / drain mask after the fifth step and then performing N + source / drain ion implantation; Performing a seventh step of wet etching the third oxide layer to a predetermined thickness in order to completely overlap the gate electrode and the source / drain in the source / drain of the PMOS transistor after the sixth step; An eighth step of etching the third oxide film wet-etched after the seventh step using a P + source / drain mask to form a PMOS spacer; And a ninth step of forming a PMOS transistor by performing P + source / drain ion implantation after the eighth step.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 8C are process diagrams for forming a semiconductor device according to the first embodiment of the present invention.

Each a figure shows an NMOS region, each b figure shows a PMOS region, and each c figure shows a cell array region.

2A to 2C illustrate the steps of forming the gate electrodes 40 and 50 and the first oxide film 80. The low-resistance conductivity for the gate oxide film 30 and the gate electrode on the semiconductor substrate 20 is shown. A first step of sequentially depositing a layer and an oxide film having an appropriate thickness; A second step of forming the gate electrodes 40 and 50 and the oxide film pattern 60 by patterning the low resistance conductive layer and the oxide film to a predetermined size after the first step; A third step of performing N-ion implantation on the entire surface of the NMOS, PMOS, and cell array to form an LDD structure on the resultant product on which the gate electrodes 40 and 50 are formed; And a fourth step of forming a first oxide film 80 on the resultant subjected to N-ion implantation.

The low resistance conductive layer is preferably formed of the polysilicon film 40 and the silicide film 50 having a predetermined thickness, and the silicide film is preferably tungsten silicide, for example. In addition, the first oxide film 80 is for forming a spacer, the thickness is preferably formed to 1500 ~ 2000 ~.

3A to 3C show a step of forming an NMOS transistor, which is formed by applying a photoresist on the resultant on which the first oxide film 80 is formed and then patterning it using an N + source / drain mask. 1st process of forming 1 photoresist pattern PR1; A second process of forming an NMOS spacer SP1 by etching using the first photoresist pattern PR1; An NMOS transistor (not shown) is formed by performing N + source / drain ion implantation on the resultant using the first photoresist pattern PR1 and the NMOS spacer SP1 as an ion implantation mask; It consists of four steps.

The N + source / drain ion implantation forms the NMOS spacer SP1 after etching the first oxide layer 80 in a HF-containing solution at about 200 to 250 microns before the first process, and forms the first photoresist pattern PR1. You can also proceed after removing. In this case, since the N + source / drain ion implantation is performed on the entire surface of the oxide film, the amount of the oxide film to be etched is increased by about twice as compared to the case where the process is performed without removing the photosensitive film in the subsequent oxide film etching process.

4A to 4C illustrate a step of forming a PMOS transistor, the first process of removing the first photoresist pattern PR1; A second process of wet etching the first oxide layer 80 to a predetermined thickness for complete overlap between the gate electrode and the source / drain in the source / drain of the PMOS transistor after the first process; A third process of forming a second photoresist pattern PR2 by applying a photoresist on the first oxide film 80 wet-etched after the second process and patterning the same by using a P + source / drain mask; A fourth step of forming a PMOS spacer SP2 by etching the first oxide film 80 using the first photoresist pattern PR2; After the fourth step, a P + source / drain ion implantation is performed to form a PMOS transistor (the impurity region is not shown). In this case, since the PMOS spacer SP2 is formed thinner than the NMOS spacer SP1 by the second process, the gate electrodes 40 and 50 and the P + source / drain may overlap in the PMOS region.

5A to 5C show a step of forming a second oxide film 90, the first process of removing the second photoresist pattern PR2; The second step is to form an insulator, eg, an oxide, on the resultant of the first step, thereby forming the second oxide film 90. In this case, the second oxide film 90 serves to prevent etch damage caused by etching of the NMOS and PMOS regions from a poly pad etching process to be performed later in the cell array region. The thickness of the second oxide layer 90 is 1000 to 1500 Å. It is preferable to form.

6A to 6C illustrate a step of forming a third photoresist pattern PR3. The photoresist is applied on a resultant product on which the second oxide film 90 is formed, and then patterned by using a cell open mask. It consists of a 1st process which makes three photoresist patterns PR3.

7A to 7C illustrate a step of forming a cell array spacer SP3. The second oxide film 90 and the first oxide film 80 are etched through the third photoresist pattern PR3. The first step is to form spacers SP3 in the cell array portion.

8A to 8C illustrate a step of completing a transistor of a cell array unit, and includes a first process of removing the third photoresist pattern PR3 by the cell open mask. This completes the fabrication of the transistor of the semiconductor device using different spacer lengths. In the post process, low-resistance polysilicon is deposited and patterned into a predetermined pattern to manufacture a semiconductor device.

As described above, according to the first embodiment of the present invention, since different spacer lengths can be formed in the NMOS, PMOS, and cell array portions, the gate electrode and the source / drain can be overlapped by shortening the PMOS spacer length. The mask operation can be simplified by forming different spacer lengths with each mask and simultaneously performing source / drain ion implantation.

9A through 14C are process diagrams for forming a semiconductor device in accordance with a second embodiment of the present invention. Here, the same reference numerals as in FIGS. 2A through 8C denote the same materials except for the PR pattern and the spacer, each a is an NMOS region, each b is a PMOS region, and each c is a cell array region. Each is shown.

9A to 9C illustrate the steps of forming the gate electrodes 40 and 50 and the third oxide film 70. The gate oxide film, the low resistance conductive layer for the gate electrode, and the titration on the semiconductor substrate 20 are shown. A first step of sequentially depositing an oxide film having a thickness; A second step of forming gate electrodes 40 and 50 by patterning the low resistance conductive layer and the oxide film to a predetermined size after the first step; A third step of performing N-ion implantation on the entire surface of the NMOS, PMOS, and cell array to form an LDD structure on the resultant product on which the gate electrodes 40 and 50 are formed; And a fourth process of forming a third oxide film 70 on the resultant subjected to N-ion implantation.

The third oxide film 70 is preferably formed to 2000 to 2500Å, and in the embodiment of the present invention, a poly pad is first formed in the cell array, so that the third oxide film 70 may be prevented from being damaged by etching of NMOS and PMOS during poly etching. Since the oxide film is unnecessary, it is sufficient to deposit the third oxide film 70 only once.

10A to 10C illustrate a step of forming a spacer of a cell array region, in which a photoresist is applied on the resultant on which the third oxide layer 70 is formed, and then patterned using a cell open mask. The first process of forming the photoresist pattern PR1 and the second process of forming the spacer SP1 of the cell array region by etching the first photoresist pattern PR1 with a mask.

11A to 11C illustrate a step of forming the poly pad 100 in the cell array region. The first process of removing the first photoresist pattern PR1 and depositing polysilicon on the resultant are shown. 2nd process, the 3rd process of forming the poly pad 100 in a capacitor contact part and a bit line contact area by etching using a pad poly mask, and the process of removing the photoresist pad | donut (not shown) by a pad poly mask. It consists of four steps.

12A to 12C illustrate a step of forming an NMOS transistor, in which a second layer is formed by applying photoresist to the resultant having the poly pad 100 formed in the cell array region, and then patterning the same by using an N + source / drain mask. A first step of forming a photoresist pattern PR2 and a second step of forming an NMOS spacer SP2 by etching using the second photoresist pattern PR2; An N + source / drain ion implantation on the resultant using the second photoresist pattern PR2 and the NMOS spacer SP2 as an ion implantation mask to form an NMOS transistor (not shown in the impurity region) It consists of four steps.

The N + source / drain ion implantation forms the NMOS spacer SP2 after etching the third oxide layer 70 in a HF-containing solution at about 200 to 250 microns before the first process, and then forms the second photoresist pattern PR2. You can also proceed after removing. In this case, since N + source / drain ions are implanted on the entire surface of the oxide film except for the cell array region, the amount of oxide film etched is about twice as large as that in the subsequent oxide etching process without performing the photosensitive film removal process. Increases.

13A to 13C illustrate a step of forming a PMOS transistor, the first process of removing the second photoresist pattern PR2; A second process of wet etching the source / drain of the PMOS transistor after the first process so that the third oxide film 70 has a predetermined thickness for complete overlap between the gate electrode and the source / drain; A third process of forming a third photoresist pattern PR3 by applying a photoresist on the third oxide film 70 wet-etched after the second process and patterning the same by using a P + source / drain mask; A fourth step of forming a PMOS spacer SP3 by etching the third oxide film 70 using the third photoresist pattern PR3; After the fourth step, a P + source / drain ion implantation is performed to form a PMOS transistor (the impurity region is not shown). In this case, since the PMOS spacer SP3 is formed thinner than the NMOS spacer SP2 by the second process, the gate electrodes 40 and 50 and the P + source / drain may overlap in the PMOS region.

14A to 14C are diagrams illustrating stages in which transistors of a semiconductor device having different lengths of spacers are completed, and the first process is performed to remove the third photoresist pattern PR3.

The second embodiment of the present invention is a process of first forming a poly pad in a cell array, and the process can be simplified by only one oxide deposition as described above, and the process can be simplified. It is possible to have suitable electrical characteristics for the transistor of.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (11)

A method of manufacturing a semiconductor device using different spacer lengths, comprising: a first step of sequentially depositing a gate oxide film, a low resistance conductive layer for a gate electrode, and an oxide film having an appropriate thickness on a semiconductor substrate; A second step of forming a gate electrode by patterning the gate oxide layer, the low resistance conductive layer, and the second electrode; A third step of performing N-ion implantation for forming an LDD structure on the resultant gate electrode on the entire surface of the NMOS, PMOS, and cell array regions; A fourth step of forming an NMOS spacer through an etching process using a N + source / drain mask after depositing a first oxide film for spacer formation on the resultant N-ion implantation; A fifth step of forming an NMOS transistor by performing N + source / drain ion implantation on the resultant NMOS spacer formed thereon; A sixth step of wet etching the first oxide layer to a predetermined thickness for complete overlap between the gate electrode and the source / drain in a source / drain of a PMOS transistor; Forming a PMOS spacer by wet etching the first oxide layer using a P + source / drain mask and etching the first oxide layer; An eighth step of forming a PMOS transistor by performing P + source / drain ion implantation on the resultant PMOS spacer; And a ninth step of forming a cell array spacer through an etching process and a photo using a cell open mask after depositing a second oxide film on the resultant. 2. The method of claim 1, wherein the low resistance conductive layer of the first step is formed of a polysilicon film and a silicide film having a predetermined thickness. 3. The method of claim 2, wherein the silicide film having a predetermined thickness is formed of a tungsten silicide film. 2. The method of claim 1, wherein the first oxide film in the fourth step is formed at 1500 to 2000 microns. The method of claim 1, wherein the N + source / drain ion implantation of the fifth step is performed by etching the first oxide layer in an HF-containing solution at about 200 to 250 Å in the fourth step to form the NMOS spacer, and then removing the photoresist layer. A method of manufacturing a semiconductor device using different spacer lengths, characterized in that it proceeds. The method of claim 1, wherein the second oxide film of the ninth step is formed to have a thickness of 1000 to 1500 1. A method of manufacturing a semiconductor device using different spacer lengths, comprising: a first step of sequentially depositing a gate oxide film, a low resistance conductive side for a gate electrode, and an oxide film having an appropriate thickness on a semiconductor substrate; A second step of patterning a gate electrode to a predetermined size after the first step, and then performing N-ion implantation on the entire surface of the NMOS, PMOS, or cell array to form an LDD structure; A third step of depositing a third oxide film for forming a spacer after the second step; A fourth step of forming a spacer in the cell array region by etching using the cell open mask after the third step; Depositing and etching polysilicon after the fourth step to form a poly pad on the bit line contact area on the capacitor contact area; A sixth step of forming an NMOS transistor by forming an NMOS spacer through a photolithography and an etching process using an N + source / drain mask after the fifth step and performing N + source / drain ion implantation; Performing a seventh step of wet etching the PMOS transistor so that the third oxide film has a predetermined thickness in order to completely overlap the gate electrode and the source / drain in the source / drain after the sixth step; An eighth step of etching the third oxide film wet-etched after the seventh step using a P + source / drain mask to form a PMOS spacer; And a ninth step of forming a PMOS transistor by performing P + source / drain ion implantation after the eighth step. The method of claim 7, wherein the low resistance conductive layer of the first step is a polysilicon film and a silicide film having a predetermined thickness. 10. The method of claim 8, wherein the silicide film having a predetermined thickness is formed of a tungsten silicide film. 8. The method of claim 7, wherein the third oxide film of the third step is formed at 2000 to 2500 microns. The method of claim 7, wherein the N + source / drain ion implantation of the sixth step is performed by etching the third oxide layer in an HF-containing solution at about 200˜250 μm, forming the NMOS spacer, and removing the photoresist layer. A semiconductor device manufacturing method using different spacer lengths.