KR0147504B1 - An improved time switch for a trunk - Google Patents

Abstract

The present invention provides a first time slot interchange apparatus 1-1 which can accommodate a 960 trunk; A first data link device (2-1) for interfacing the first timeslot interchange device (1-1) on a 1K link; A second timeslot interchange device 1-2 capable of accommodating a 960 trunk; A second data link device (2-2) for interfacing the second timeslot interchange device (1-2) on a 1K link; And receiving a clock from the first data link device 2-1 and the second data link device 2-2, and receiving data from the first and second timeslot interchange devices 1-1 and 1-2. And a control memory and maintenance device (10) for receiving and providing a control memory function for exchanging voice memory timeslots in the first and second timeslot interchange devices (1-1, 1-2). This improves trunk capacity and reduces manufacturing costs by reducing configuration requirements.

Description

Time switch device with improved trunk capacity

1 is a block diagram showing a conventional time switch device for accommodating 960 trunks,

2 is a block diagram showing a conventional time switch device for accommodating a 1920 trunk;

3 is a block diagram showing a time switch device for accommodating 1920 trunks according to the present invention;

FIG. 4 is a block diagram showing the control memory and the maintenance apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

1-1,1-2: Time Slot Interchange Device 2-1,2-2: Data Link Device

3-1,3-2,10: Control memory and maintenance device 33-1,33-2,33-3: Control memory

22-1,22-2,22-3: Control data output device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time switch device of a digital all-electronic exchange, and in particular, to a connection with a digital trunk interface (DT1) and a digital CEPT interface (DC1) in a line and trunk access subsystem (LTAS). The present invention relates to a time switch device having improved trunk capacity in a digital switch device.

In general, the digital electronic switchboard provides a communication path through which subscribers transmit PCM-modulated voice and data at 64 kbps to a specific counterpart, performing time switching (T) with a time slot set through a call processing process. It has a complicated switching structure that is time-switched again through space division switching (S), and has a trunk interface function for connecting the switching stations to connect subscribers in one switching station to subscribers of another switching station. have.

As shown in FIG. 1, a conventional time switch device used to accommodate a trunk as described above is provided with 960 trunks in one time slot interchange device and connected to a 1K link through a data link device. The time switch device includes a timeslot interchange device (1-1); Data linkage apparatus 1-2; And a control memory and maintenance device 3-1 to connect the 960 trunk on a 1K link.

On the other hand, as shown in FIG. 2, in order to accommodate 1920 trunk which is doubled of 960, a first timeslot interchange apparatus (TSIA: 1-1) in which the first group accommodates 960 trunks; A first data link device (TLIA: 2-1) for connecting the timeslot interchange device 1-1 on a 1K link; A first control memory for receiving a clock from the data link device 2-1 and providing a control memory and control data to a time slot interchange device according to control of a time switch processor (not shown) and testing the time switch device; A second timeslot interface device (1-2) configured as a maintenance device (CMMA) 3-1, independent of the same configuration as the first group, and the second group accommodating 960 trunks; A second data link device (2-2) for connecting the timeslot interchange device (1-2) on a 1K link; And a second control memory for receiving a clock from the data link device 2-2, providing a control memory and control data to the time slot interchange device under control of a time switch processor (not shown), and testing the time switch device. It consists of the maintenance apparatus 3-2.

By the way, in the time switch configuration connected to the 2K link as described above, it is preferable that only one of the control memory maintenance devices 3-1 and 3-2 is duplicated and mounted therein. There is a problem in that the two are mounted for unnecessary manufacturing costs unnecessarily.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and improves the trunk demand capacity and reduces the manufacturing cost by reducing the number of control memory and maintenance devices required to reduce the manufacturing cost The purpose is to provide.

In order to achieve the above object, an apparatus of the present invention includes a first timeslot interchange apparatus capable of accommodating 960 trunks; A first data link device for interfacing the first timeslot interchange device on a 1K link; A second timeslot interchange device capable of receiving a 960 trunk; A second data link device for interfacing the second timeslot interchange device on a 1K link; And receiving a clock from the first data link device and the second data link device, receiving data from the second timeslot interchange device, and performing timeslot exchange of voice memories in the first and second timeslot interchange devices. It is characterized by consisting of a control memory and a maintenance device that provides a control memory function for.

In addition, the control memory and the maintenance apparatus according to the present invention for the configuration as described above is provided with one more control memory, so as to perform the functions of other conventional control memory and maintenance apparatus, one control memory and maintenance apparatus This can improve trunk capacity.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

As shown in FIG. 3, the time switch device according to the present invention comprises: a first timeslot interchange device 1-1 capable of accommodating 960 trunks; A first data link device (2-1) for interfacing the first timeslot interchange device (1-1) on a 1K link; A second timeslot interchange device 1-2 capable of accommodating a 960 trunk; A second data link device (2-2) for interfacing the second timeslot interchange device (1-2) on a 1K link; And receiving a clock from the first data link device 2-1 and the second data link device 2-2, and receiving data from the first and second timeslot interchange devices 1-1 and 1-2. And a control memory and a maintenance device (10) for receiving and providing a control memory function for exchanging voice memory timeslots in the first and second timeslot interchange devices (1-1, 1-2). have.

In addition, the control memory and the maintenance apparatus 10 according to the present invention, as shown in Figure 4, from the two TLIA CP3, CP3D. A clock selection and distribution unit 16-1 for receiving the FP3 clock and selecting and distributing a clock input of one TLIA according to a valid signal; A clock driver 16-2 receiving the output of the clock selection and distribution unit 16-1 and outputting one set of MCLK (4,096 kHz) and FS (8 kHz) clocks per four sets of subhighways; A differential receiver 11-1 which receives subhighway differential serial data having a transmission rate of 2048 kbps from the service unit and outputs it as single ended serial data; In response to the clock of the clock selector and divider 16-1, the differential receiver 11-1 converts the serial data output to parallel and converts the looped-in sub-way serial data to parallel. A serial-to-parallel conversion and multiplexing unit 14 for generating and outputting one-bit parity for data in units of bytes after multiplexing by a number 1/32 decoder; The outputs of the serial-to-parallel converter and the multiplexer 14 are sequentially recorded along the outputs of the clock selector and divider 16-1, and the outputs of the serial-to-parallel convertor and the multiplexer 14 are sequentially recorded. A voice memory 31 for recording and rearranging the order of time slots by sequentially reading along the output of the clock selector 16-1; An output latch (19) for latching the output of said voice memory (31) to output to TSIA; An input latch and selector 21 for receiving parallel data of 10 bits from the first TSIA group and the second TSIA group and selecting one input according to a valid bit; Μ-A, A-μ converter 32 for converting μ-A or A-μ according to UA, TC bits; After checking the parity in the parallel outputs of the μ-A and A-μ converters 32 and converting them in series, some of them loop back to the serial-to-parallel conversion and multiplexer 14 for intra jitter, and others A parallel-to-serial conversion and demultiplexer 15 outputted to the differential transmitter 11-2; A differential transmitter (11-2) which receives serial data of a single output from the parallel-to-serial conversion and demultiplexer (15) and drives a differential signal to output it as a service unit; A parity checker 20 which receives parity-related information from the serial-to-parallel conversion and multiplexing unit 14 and the parallel-to-parallel conversion and demultiplexing unit 15 and outputs the parity-related information to the state information receiving unit 18-1; Through the processor matching unit 13-1, an address for reading data stored in the voice memory of the time slot interchange device 1 (TSIA) from the time switch processor TSP to the data link device 1 side is randomly received and stored. A first control memory 33-1 reading sequentially according to the clock of the clock selection and distribution unit 16-1; A second control memory 33-2 storing an address for reading data stored in the voice memory of the timeslot interchange apparatus 1 (TSIA) to the data link device 2 through the processor matching unit 13-1; A third control memory 33-3 storing an address for reading data stored in the voice memory of the timeslot interchange apparatus to the CMMA side through the processor matching unit 13-1; A first control data output latch 22-1 for the first control memory 33-1 to latch an output and output the TSIA to the TSIA; A second control data output latch 22-2 for latching the output of the second control memory 33-2 to output to TSIA; A third control data output latch 22-3 for latching an output of the third control memory 33-3 to output to the TSIA; A pattern transmitter 12-1 generating a test enable and a test data according to the control of the time switch processor; A multiplexer 30 for multiplexing pattern data to a corresponding channel of the subhighway 31 when an enable signal is input from the pattern transmitter 2-1; A pattern receiver 12-2 receiving a test pattern through a corresponding channel of the subhighway 31 from the output of the parallel-serial converter and the demultiplexer 15; A redundancy control unit 1 (8-2) which receives the redundancy control signal OJC from another CMMA and outputs its own redundancy control signal JC; It consists of a latch and the comparison part 12-3.

The first to third control memories 33-1, 33-2, and 33-3 are configured as 1Kx16 or 2K X 16-bit dual-port memories, and the processor matching unit 13-1 stores address and control data. Receive and provide the corresponding address, store the periodic clock of the clock selection and distribution unit 16-1 in the address, output 16-bit control data, and output the first to third control data output latches 22-1, 22-2 and 22-3 latch the outputs of the first to third control memories 33-1, 33-2 and 33-3 and output them to TSIA.

As described above, since the 1920 trunk can be connected on the 2K link by using one control memory and a maintenance apparatus, manufacturing cost can be reduced.

Claims (2)

A digital switch device for accommodating 1920 trunks and connecting on a 2K link, comprising: a first timeslot interchange device (1-1) capable of accommodating 960 trunks; A first data link device (2-1) for interfacing the first timeslot interchange device (1-1) on a 1K link; A second timeslot interchange device 1-2 capable of accommodating a 960 trunk; A second data link device (2-2) for interfacing the second timeslot interchange device (1-2) on a 1K link; And receiving a clock from the first data link device 2-1 and the second data link device 2-2, and receiving data from the first and second timeslot interchange devices 1-1 and 1-2. And a control memory and maintenance device 10 for receiving a signal and providing a control memory function for time slot exchange of voice memories in the first and second timeslot interchange devices 1-1, 1-2. Time switch device with improved trunk capacity. The time switch device according to claim 1, wherein the control memory and the maintenance device are provided with three control memories.