KR0146245B1 - Method of fabricating a capacitor of semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a capacitor of a semiconductor device, comprising: forming a first plate electrode surrounding a surface of a bit line, and connecting the first plate electrode to a surface of a cylindrical charge storage electrode having a plurality of polysilicon layer patterns; Since the second plate electrode is formed to form a capacitor having an increased surface area, the capacitance is increased to increase the reliability of the device operation and to increase the integration of the device.

Description

Capacitor Manufacturing Method of Semiconductor Device

1A to 1C are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to the prior art.

2a to 2h is a manufacturing process diagram of a capacitor of a semiconductor device according to an embodiment of the present invention.

3 is a cross-sectional view of a capacitor manufacturing step of a semiconductor device according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: Semiconductor Substrate 2: Field Oxide

3: gate oxide film 4: gate electrode

5: Diffusion area 6: Spacer

7,15,22: Oxide 8: Nitride

9, 16, 30: planarization layer 10, 12, 18, 23, 26, 29, 31, 34, 36: polycrystalline silicon layer

11, 28: charge storage electrode contact hole 13, 19, 24, 27, 32, 35: photoresist pattern

20: bit line 21: silicide film

25, 33: Dielectric film 17: Bitline contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, a plate electrode is formed on the surface of a cylindrical charge storage electrode and around a bit line to increase the surface area of the capacitor. The present invention relates to a method for manufacturing a capacitor of a semiconductor device.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.

In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.

However, all these methods have their own problems.

That is, for example, Ta ₂ O ₅ , TiO ₂ or SrTiO ₃ have been studied as dielectric materials with high dielectric constants, but these materials have not been confirmed with reliability and thin film characteristics such as junction breakdown voltage. It is difficult to apply to the actual device.

In addition, the method of reducing the dielectric film thickness has a serious effect on the reliability of the capacitor because the dielectric film is destroyed during operation of the device.

In addition, in order to increase the surface area of the capacitor, polycrystalline silicon is formed in multiple layers and penetrates through them to form a fin structure or a maze structure of a cylindrical or rectangular frame shape, or is a right angle of the grain boundary of polycrystalline silicon. H. S. (HSG) method using a selection ratio is used.

However, each of the charge storage electrodes has a problem.

In other words, the fin-type charge storage electrode has a complicated manufacturing process, resulting in low process yield, and the hollow cavity type increases the step difference between the cell region and the peripheral circuit region, thereby reducing the process margin in the subsequent mask process and making the metal process difficult. Cylindrical has a problem that process defects such as polycrystalline polymer of polysilicon remain during formation of the conductive spacers, and thus short circuit occurs, thereby degrading reliability and process yield of device operation.

1A to 1C show a process of manufacturing a charge storage electrode of a semiconductor device according to the prior art, which is an example of a cylindrical charge storage electrode.

First, a field oxide film 2 for device isolation on the semiconductor substrate 1, a gate oxide film 3, a series of gate electrodes 4, and an oxide film 7 pattern overlapping the gate electrode 4. And an oxide spacer 6 on the sidewalls of the gate electrode 4, and a conventional lightly doped drain (LDD) on the semiconductor substrate 1 on both sides of the gate electrode 4 An impurity diffusion region 5 of a structure).

A nitride film 8, which is an etch barrier layer, is then formed on the entire surface of the structure, and the nitride film 8 on the upper portion of the diffusion region 5, which is supposed to be a charge holding electrode contact, and the gate electrode 4 in contact therewith. Is removed to expose the diffusion region 5. (See also Figure 1a.)

Thereafter, a first polycrystalline silicon 10 pattern as a conductive layer is formed on the portion where the nitride film 8 is removed, and the charge storage electrode contact hole exposing the first polycrystalline silicon layer 10 pattern again. The pattern of the planarization layer 9 having 11) is formed by the method of photolithography and photolithography of chemical vapor deposition (hereinafter referred to as CVD) oxide film. Next, a second polysilicon layer 12 is formed on the entire surface of the structure, and a photoresist pattern 13, which is a charge storage electrode etch mask, is formed on a portion where the step is lowered by the charge storage electrode contact hole 11. (See also Figure 1b.)

Thereafter, the second polysilicon layer 12 exposed by the photosensitive film pattern 13 is removed to have a cylindrical shape in contact with the first polysilicon layer 10 pattern inside the charge storage electrode contact hole 11. The second polysilicon layer 12 pattern is formed, and the photoresist pattern 13 and the planarization layer 9 pattern are removed. (See also Figure 1c.)

In the cylindrical charge storage electrode according to the prior art as described above, the charge storage electrode is formed on the upper side of the gate electrode in order to increase the surface area. However, as the device becomes highly integrated, it is difficult to secure sufficient capacitance without increasing the step. There is a problem that inhibits the high integration of the.

The present invention is to solve the above problems, the object of the present invention is to use the plate electrode on the surface of the bit line to increase the surface area of the capacitor to improve the process yield and the reliability of device operation, high integration of the device The present invention provides a method for manufacturing a capacitor of an advantageous semiconductor device.

A feature of the method for manufacturing a capacitor of a semiconductor device according to the present invention for achieving the above object is, on the entire surface of a structure in which a field oxide film, a gate oxide film, a gate electrode and a diffusion region are formed on the semiconductor substrate for device isolation. Forming an etch barrier layer, forming a planarization layer on the etch barrier layer, and forming a bit line contact hole by removing the planarization layer and the etch barrier layer on a portion of the semiconductor substrate, which are supposed to be bit line contacts. Forming a bit line in contact with the semiconductor substrate through the bit line contact hole; exposing the bit line by removing the planarization layer; forming an insulating film on the entire surface of the structure; Forming a first conductive layer on the insulating film; and a portion of the semiconductor substrate that is intended to be a charge storage electrode contact. Forming a first conductive layer pattern exposing the insulating film by etching the first conductive layer in a width wider than that of minutes, forming a first dielectric layer on the entire surface of the structure, and forming a second dielectric layer on the first dielectric layer. Forming a conductive layer, and forming a charge storage electrode contact hole exposing the semiconductor substrate by sequentially removing the second conductive layer from the second conductive layer on the portion of the semiconductor substrate scheduled as the charge storage electrode contact to the etch barrier layer; Forming a third conductive layer on the entire surface of the structure, the third conductive layer being in contact with the semiconductor substrate through the charge storage electrode contact hole and overlapping the second conductive layer; Isolating each of the charge storage electrodes to form a fourth conductive layer pattern overlapping the upper side of the third conductive layer and having a cylindrical sidewall. Forming a charge storage electrode composed of the second, third and fourth conductive layer patterns, forming a second dielectric film on the entire surface of the structure, and forming a fifth conductive layer on the surface of the second dielectric film And exposing a first conductive layer pattern by sequentially removing the fifth conductive layer and the second dielectric layer on the bit line, and contacting the exposed first conductive layer pattern. And forming a sixth conductive layer overlapping with each other to form a plate electrode.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are manufacturing process diagrams of a charge storage electrode of a semiconductor device according to an embodiment of the present invention.

First, a field oxide film 2, a gate oxide film 3, and a series of gate electrodes 4 are formed on the semiconductor substrate 1, and then an oxide spacer (or an oxide spacer) is formed on the sidewall of the gate electrode 4. 6), and a diffusion region 5 having a lightly doped drain (LDD) structure is formed on the semiconductor substrate 1 on both sides of the gate electrode 4.

Subsequently, layers having etching selectivity differences, for example, the first oxide film 15, the nitride film 8, and the first planarization layer 16 are sequentially formed on the entire surface of the structure. The first oxide film 15 and the nitride film 8 become an etching barrier layer for the convenience of the subsequent etching process. (See also FIG. 2A.)

Thereafter, the first planarization layer 16 on the portion scheduled for bit line contact in the diffusion region 5 is sequentially removed from the first oxide film 15 to form a bit line contact hole 17. A conductive layer, for example a first polysilicon layer 18, is applied to the entire surface of the bit line to contact the diffusion region 5 through the bit line contact hole 17, and then the bit line contact hole 17 The first photoresist pattern 19, which is a bit line etch mask, is formed on the first polysilicon layer 18 having the gap. (See also figure 2b).

Thereafter, the first polycrystalline silicon layer 18 exposed by the first photoresist layer pattern 19 is removed by anisotropic etching to form a bit line 20 formed of the first polycrystalline silicon layer 18 pattern. After the first photoresist layer pattern 19 and the first planarization layer 16 are removed to expose the nitride layer 8 and the bit line 20, a transition metal capable of silicide on the exposed surface of the bit line 20 is exposed. For example, the silicide film 21 is formed of any one of Mo, Ti, Ta, Cr, and Nb or selectively W, and the second oxide film 22 is formed on the entire surface of the structure. In this case, the silicide layer 21 may not be formed as a layer for reducing the resistance of the bit line 20. (See also FIG. 2C).

Thereafter, a second polysilicon layer 23, which is a conductive layer, is coated on the second oxide film 22, and a second polysilicon layer on the portion scheduled for charge storage electrode contact in the diffusion region 5 ( After the second photoresist pattern 24 exposing the second photoresist pattern 24 is formed, the second polysilicon layer 23 exposed by the second photoresist pattern 24 is anisotropically etched to form the second photoresist pattern 24. Undercut) forms a pattern of the second polysilicon layer 23 undercut (see also FIG. 2d).

Then, the second photoresist layer pattern 24 is removed, and the first dielectric layer 25 and the third polysilicon layer 26 are sequentially formed on the entire surface of the structure, and then charge is preserved in the diffusion region 5. A third photosensitive film pattern 27 exposing the third polysilicon layer 26 on the upper part of the portion scheduled as the electrode contact is formed, and a third polysilicon layer exposed by the third photosensitive film pattern 27 ( An anisotropic etch sequentially from 26 to the first oxide film 15 is formed to form a charge storage electrode contact hole 28 exposing the diffusion region 5. In this case, the third polysilicon layer 26 is to protect the first dielectric layer 25 during the etching process (see also FIG. 2e).

Thereafter, the third photoresist layer pattern 27 is removed, and a fourth polycrystalline silicon layer 29 is coated on the entire surface of the structure to contact the third polysilicon layer 26 pattern, and then the charge storage electrode The third and fourth polysilicon layers 26 and 29 are contacted with the contact hole 28 and the first dielectric layer 25 is exposed by patterning the third and fourth polysilicon layers 26 and 29 so that a portion defined by the charge storage electrode remains. ) Is also removed to form the third and fourth polysilicon layers 26 and 29 pattern exposing the second polysilicon layer 23 pattern.

Then, the second planarization layer 30 pattern of an oxide film material is formed on the exposed second polysilicon layer 23 pattern to expose the fourth polysilicon layer 29 pattern, and then the entire structure of the structure is exposed. The fifth polysilicon layer 31 is coated on the surface so as to be in contact with the exposed fourth polysilicon layer 29 pattern, and the curved recesses in the structure are filled with the fourth photoresist pattern 32. (See also FIG. 2F).

Thereafter, the fifth polysilicon layer 31 over the second planarization layer 30 pattern exposed by the fourth photoresist layer pattern 32 is removed to form a cylindrical fifth polysilicon layer 31 pattern. The fourth photoresist pattern 32 and the second planarization layer 30 pattern are removed.

Then, the second dielectric layer 33 and the sixth polysilicon layer 34 are sequentially formed on the entire surface of the structure, and then the charge retention is performed in the third and fourth polysilicon layers 26 and 29 pattern. A fifth photosensitive film pattern 35 for exposing the second polysilicon layer 23 pattern between the electrodes is formed.

Thereafter, the sixth polysilicon layer 34 and the second dielectric layer 33 which are exposed by the fifth photoresist pattern 35 are sequentially removed to expose the second polysilicon layer 23 to thereby charge storage electrodes. To separate. (See also Figure 2g).

Next, the fifth photoresist layer pattern 35 is removed, and a seventh polysilicon layer 36 is formed on the entire surface of the structure to expose the exposed second and sixth polycrystalline silicon layers 23 and 34. A plate electrode is formed in contact (see also FIG. 2h).

The first and second dielectric layers 25 and 33 may be formed of a single oxide layer or a stacked structure of an oxide layer, a nitride layer, and an oxide layer.

As described above, a cylindrical charge storage electrode was formed, and a plate electrode was formed not only on the surface thereof but also around the bit line to increase capacitance in proportion to the surface area of the capacitor.

3 is a cross-sectional view of a capacitor manufacturing step of a semiconductor device according to another exemplary embodiment of the present invention. In the process of FIG. 2F, the second photoresist layer pattern 32 is not formed to fill in the main portion, and the second planarization layer 30 is formed. The fourth photosensitive film pattern 32 is formed by a photolithography method so as to expose the upper fifth polysilicon layer 31, and the subsequent steps are performed.

As described above, the method of manufacturing a capacitor of a semiconductor device according to the present invention forms a first plate electrode surrounding a surface of a bit line, and a second plate electrode connected to the first plate electrode on the surface of a cylindrical charge storage electrode. Since the capacitor is formed to form a capacitor having an increased surface area, the capacitance is increased, thereby increasing the reliability of device operation and advantageously in terms of high integration of the device.

Claims (7)

Forming an etch barrier layer on the entire surface of the structure in which a field oxide film, a gate oxide film, a gate electrode and a diffusion region are formed on a semiconductor substrate, and forming a planarization layer on the etch barrier layer; Forming a bit line contact hole by removing a planarization layer and an etch barrier layer on a portion of the semiconductor substrate which are intended as bit line contacts, and forming a bit line in contact with the semiconductor substrate through the bit line contact holes. Exposing the bit line by removing the planarization layer, forming an insulating film on the entire surface of the structure, forming a first polysilicon layer on the insulating film, and charge preservation in the semiconductor substrate. A first polysilicon layer is etched in a wider width than a portion intended as an electrode contact to expose the insulating film. Forming a polysilicon layer pattern, forming a first dielectric layer on the entire surface of the structure, forming a second polysilicon layer on the first dielectric layer, and a charge storage electrode contact on the semiconductor substrate Forming a charge preservation electrode contact hole to expose the semiconductor substrate by sequentially removing the second polycrystalline silicon layer on the portion scheduled to be an etch barrier layer, and contacting the semiconductor substrate through the charge preservation electrode contact hole, Forming a third polysilicon layer overlapping the second single crystal silicon layer on the entire surface of the structure; and removing a predetermined portion from the third and second polysilicon layers and isolating the respective charge storage electrodes. And forming a fourth polysilicon layer pattern overlapping the upper side of the third polysilicon layer and having a cylindrical sidewall. Forming a charge storage electrode composed of the second, third and fourth polysilicon layer patterns, forming a second dielectric film on the entire surface of the structure, and a fifth polysilicon layer on the surface of the second dielectric film Forming a first polycrystalline silicon layer pattern by sequentially removing the fifth polycrystalline silicon layer and the second dielectric layer on the bit line, and contacting the exposed first polycrystalline silicon layer pattern. And forming a sixth polysilicon layer overlapping the fifth polycrystalline silicon layer to form a plate electrode. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein said etching barrier side is formed in a stacked structure of an oxide film and a nitride film. The silicide of one transition metal of claim 1, wherein Mo, Ti, Ta, Cr, and Nb are optionally selected from the group consisting of Mo, Ti, Ta, Cr, and Nb on the surface of the bit line to which the interlayer insulating film is removed to reduce the resistance of the bit line. A method for manufacturing a capacitor of a semiconductor device, characterized by forming a film. The method of claim 1, wherein the selective W silicide layer is formed on a surface of the bit line to which the interlayer insulating layer is removed. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein said insulating film is formed of an oxide film. 2. The method of claim 1, wherein the first to sixth polycrystalline silicon layers are formed of a polycrystalline silicon layer. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein said first and second dielectric films are formed in a single layer structure of an oxide film or a stacked structure of an oxide film-nitride film-oxide film.