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JPWO2019164867A5 - - Google Patents

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Publication number
JPWO2019164867A5
JPWO2019164867A5 JP2020566538A JP2020566538A JPWO2019164867A5 JP WO2019164867 A5 JPWO2019164867 A5 JP WO2019164867A5 JP 2020566538 A JP2020566538 A JP 2020566538A JP 2020566538 A JP2020566538 A JP 2020566538A JP WO2019164867 A5 JPWO2019164867 A5 JP WO2019164867A5
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Prior art keywords
circuit
circuit configuration
lower portion
pixel
voltage transistor
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Granted
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JP2020566538A
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Japanese (ja)
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JP2021514494A (en
JP7371025B2 (en
Publication date
Priority claimed from US16/279,809 external-priority patent/US10950178B2/en
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Publication of JP2021514494A publication Critical patent/JP2021514494A/en
Publication of JPWO2019164867A5 publication Critical patent/JPWO2019164867A5/ja
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Publication of JP7371025B2 publication Critical patent/JP7371025B2/en
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Claims (10)

垂直に積層されたピクセル回路であって、
少なくとも1つの低電圧トランジスタを備える低電圧回路構成と、少なくとも1つのトレンチキャパシタを備えるデータ記憶回路構成とを具備する下側部分と、
少なくとも1つの高電圧トランジスタと、第1の有機発光ダイオード（OLED）を駆動するように構成されたピクセル駆動回路構成とを備え前記下側部分の上方に配置される上側部分であって、第1のシリコン貫通ビア（TSV）と少なくとも1つの高電圧トランジスタとを含む、上側部分と
を備え、
前記上側部分および前記下側部分は、前記第1のTSVを含む単一の電気的接続点を介して電気的に接続される、垂直に積層された回路。 It is a vertically stacked pixel circuit.
A lower portion with a low voltage circuit configuration with at least one low voltage transistor and a data storage circuit configuration with at least one trench capacitor .
A first portion comprising at least one high voltage transistor and a pixel drive circuit configuration configured to drive a first organic light emitting diode (OLED) and located above the lower portion . It features an upper portion, including a silicon through via (TSV) and at least one high voltage transistor .
A vertically stacked circuit in which the upper portion and the lower portion are electrically connected via a single electrical connection point including the first TSV . 前記高電圧トランジスタは、3ボルトよりも高い動作電圧を有し、前記少なくとも1つの低電圧トランジスタは、3ボルト以下の動作電圧を有する、請求項1に記載の回路。 The circuit of claim 1, wherein the high voltage transistor has an operating voltage higher than 3 volts and the at least one low voltage transistor has an operating voltage of 3 volts or less . 前記下側部分は、マトリクスアドレッシング回路構成と、均一性補償回路構成とを備える、請求項1に記載の回路。 The circuit according to claim 1, wherein the lower portion includes a matrix addressing circuit configuration and a uniformity compensation circuit configuration . 前記上側部分は第1のシリコン層上に形成され、前記下側部分は第2のシリコン層上に形成され、前記第1のシリコン層と前記第2のシリコン層は互いに接合されている、請求項1、請求項3に記載の回路。 The upper portion is formed on the first silicon layer, the lower portion is formed on the second silicon layer, and the first silicon layer and the second silicon layer are bonded to each other. The circuit according to claim 1 and claim 3. 前記上側部分はさらに、前記第1のOLEDを備える、請求項1に記載の回路。 The circuit of claim 1, wherein the upper portion further comprises the first OLED . 前記回路の長さおよび幅は、４μｍ × ４μｍ未満である、請求項1に記載の回路。 The circuit according to claim 1, wherein the length and width of the circuit is less than 4 μm × 4 μm . 垂直に積層されたピクセル回路であって、
3ボルト以下の動作電圧を有する少なくとも1つの低電圧トランジスタを備える低電圧回路構成と、少なくとも1つのトレンチキャパシタを備えるデータ記憶回路構成とを具備する下側部分と、
第1の有機発光ダイオード(OLED)および前記第1のOLEDを駆動するように構成されるピクセル駆動回路構成を備え前記下側部分の上方に配置される上側部分であって、第1のシリコン貫通ビア（TSV）と3ボルトより大きい動作電圧を有する少なくとも1つの高電圧トランジスタを備えた高電圧回路構成とを具備する、上側部分と
を備え、
前記上側部分および下側部分は、前記第1のTSVを含む単一の電気的接続点を介して電気的に接続される、垂直に積層されたピクセル回路。 It is a vertically stacked pixel circuit.
A lower portion with a low voltage circuit configuration with at least one low voltage transistor with an operating voltage of 3 volts or less and a data storage circuit configuration with at least one trench capacitor .
An upper portion located above the lower portion with a pixel drive circuit configuration configured to drive the first organic light emitting diode (OLED) and the first OLED , the first silicon penetration. A high voltage circuit configuration with vias (TSVs) and at least one high voltage transistor with an operating voltage greater than 3 volts, with an upper portion ,
The upper and lower portions are vertically stacked pixel circuits that are electrically connected via a single electrical connection point that includes the first TSV . 前記下側部分は、マトリクスアドレッシング回路構成と、均一性補償回路構成とを備える、請求項7に記載のピクセル回路。 The pixel circuit according to claim 7, wherein the lower portion includes a matrix addressing circuit configuration and a uniformity compensation circuit configuration. 前記マトリクスアドレッシング回路構成は、選択スイッチを備え、前記トレンチキャパシタは蓄積キャパシタである、請求項8に記載のピクセル回路。 The pixel circuit of claim 8, wherein the matrix addressing circuit configuration comprises a selection switch, wherein the trench capacitor is a storage capacitor. 複数のサブピクセルを備えるマイクロディスプレイであって、各サブピクセルは、請求項7に記載のピクセル駆動回路を備える、マイクロディスプレイ。 A microdisplay comprising a plurality of subpixels, wherein each subpixel comprises the pixel drive circuit according to claim 7.
JP2020566538A 2018-02-20 2019-02-20 Microdisplay with reduced pixel size and method of forming it Active JP7371025B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862632920P 2018-02-20 2018-02-20
US62/632,920 2018-02-20
US16/279,809 US10950178B2 (en) 2018-02-20 2019-02-19 Microdisplay with reduced pixel size and method of forming same
US16/279,809 2019-02-19
PCT/US2019/018671 WO2019164867A1 (en) 2018-02-20 2019-02-20 3d pixel circuit for microdisplay with reduced pixel size and method of forming same

Publications (3)

Publication Number Publication Date
JP2021514494A JP2021514494A (en) 2021-06-10
JPWO2019164867A5 true JPWO2019164867A5 (en) 2022-03-01
JP7371025B2 JP7371025B2 (en) 2023-10-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020566538A Active JP7371025B2 (en) 2018-02-20 2019-02-20 Microdisplay with reduced pixel size and method of forming it

Country Status (7)

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US (2) US10950178B2 (en)
EP (1) EP3756218A1 (en)
JP (1) JP7371025B2 (en)
KR (1) KR102429648B1 (en)
CN (1) CN111819680B (en)
TW (1) TWI791772B (en)
WO (1) WO2019164867A1 (en)

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KR20230052785A (en) 2020-08-19 2023-04-20 오엘이디워크스 엘엘씨 Pixel Circuit for Crosstalk Reduction
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