JPWO2018181019A1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

Provided is a variable resistance element having improved set voltage variation between elements. A semiconductor device including at least two or more variable resistance elements, a first terminal, and a second terminal, wherein each of the variable resistance elements includes a first electrode, a second electrode, a first electrode, and a second electrode. A resistance change layer sandwiched between the second electrodes, and having a function of reversibly changing a resistance value based on an electric signal applied between the first electrode and the second electrode. The first electrode and the first terminal of the variable resistance element are electrically connected, the second electrode and the second terminal are electrically connected, and each variable resistance layer is connected to each variable resistance element. The elements are separated from each other, the second electrodes are separated from each other between the variable resistance elements, and are electrically connected to each other only through the second terminal.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same.

  2. Description of the Related Art Semiconductor devices (especially silicon devices) are being integrated at a lower power by miniaturization (scaling rule: Moore's law), and development has been advanced at a rate of three times and four times. In recent years, the gate length of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) has been reduced to 20 nm or less. There is a need to improve device performance using an approach different from the scaling rule of the above.

  Examples of the functional element formed inside the copper multilayer wiring structure on the semiconductor device include a variable resistance nonvolatile element (hereinafter, referred to as a “resistance variable element”) and a capacitor (capacitance element).

  Examples of capacitors mounted on a logic LSI (Large Scale Integration) include an embedded DRAM (Dynamic Random Access Memory) and a decoupling capacitor. By mounting these capacitors on copper wiring, it is possible to increase the capacity and reduce the area of the capacitors.

  A device called an FPGA (Field Programmable Gate Array) has been developed as an intermediate position between a gate array and a standard cell. This enables the customer himself to make an arbitrary circuit configuration after manufacturing the chip. As a programmable element, a variable resistance element or the like is interposed in a wiring connection portion so that a customer himself / herself can arbitrarily make electrical connection of the wiring. By using such a semiconductor device, the degree of freedom of a circuit can be improved.

  The variable resistance element is a generic name of an element that stores information by changing a resistance state, has a three-layer structure in which a variable resistance layer is sandwiched between a lower electrode and an upper electrode, and applies a voltage between both electrodes. This utilizes the phenomenon that the resistance change of the resistance change layer occurs. For example, as the resistance change element using the metal bridge formation, there are a ReRAM (Resistive RAM) using a metal oxide layer as a resistance change layer, a solid electrolyte switch element using a solid electrolyte, and the like.

  Several studies on the solid electrolyte switch element have been reported since the late 1990s, and resistance change phenomena due to various solid electrolyte materials have been confirmed. For example, Non-Patent Documents 1 and 2 report a resistance change phenomenon using a chalcogenide compound as a solid electrolyte.

  Hereinafter, the structure and switching operation of a solid electrolyte switch element, which is an example of a variable resistance element, will be briefly described.

  The solid electrolyte switch element has a structure in which a solid electrolyte layer is sandwiched between two electrodes (a lower electrode and an upper electrode). Here, a metal that is chemically active and can be easily oxidized and reduced by applying a voltage is used for one of the two electrodes, and a chemically inactive metal material is used for the other electrode. Used.

  Next, the operation of the solid electrolyte switch element will be described. Hereinafter, as an example, a structure in which a chemically active electrode is used as a lower electrode will be described.

  For example, in a solid electrolyte switch element in an OFF state (high resistance state), when a lower electrode (chemically active electrode) is grounded and a negative voltage is applied to an upper electrode (chemically inactive electrode), Metal atoms constituting the electrode are ionized and eluted into the solid electrolyte layer. Then, the metal ions are attracted to the upper electrode (a chemically inert electrode) side, further receive electrons, become metal atoms, and form metal bridges having conductivity by the metal atoms. When the two electrodes are electrically connected by the metal bridge formed in the solid electrolyte, the switch is turned on (low resistance state). The operation of changing from the “off state” to the “on state” by applying the negative voltage is called “set”.

  On the other hand, in the ON state, when the lower electrode is grounded again and a positive voltage is applied to the upper electrode, the metal atoms constituting the metal bridge are ionized and dissolved in the solid electrolyte layer. Then, the metal ions are pulled back to the lower electrode side, receive electrons, and become metal atoms. As a result, the connection due to the metal bridge disappears, and both electrodes are electrically insulated, so that the switch changes to a high-resistance OFF state. The operation of changing the “ON state” to the “OFF state” by applying the positive voltage is called “reset”. The “set” operation and the “reset” operation are collectively called a “programming” operation.

  As described above, the solid electrolyte switching element can hold the “ON state” and the “OFF state” in a nonvolatile manner while no voltage is applied, and can repeatedly perform the “programming” operation. By utilizing the characteristics of the solid electrolyte switch element, application to a nonvolatile memory or a nonvolatile switch becomes possible.

  An example of a storage element using a solid electrolyte is disclosed in Patent Document 1. The storage element disclosed in Patent Document 1 has a configuration in which a storage layer in which a variable resistance layer and an ion source layer are stacked is provided between a lower electrode and an upper electrode. When the configuration of this storage element is compared with the configuration of the solid electrolyte switch element described above, the variable resistance layer corresponds to a solid electrolyte layer, and the ion source layer corresponds to an electrode for supplying metal ions. The storage element disclosed in Patent Literature 1 has a configuration in which the upper and lower structures are reversed from the structure in which the above-described solid electrolyte switch element employs a chemically active electrode as a lower electrode.

  In the application of the solid electrolyte switching device to a nonvolatile memory and a nonvolatile switch, it is preferable that the “off state” is a lower leak current, that is, a higher resistance. Therefore, in order to increase the resistance in the “off state”, generally, a higher positive voltage is applied during the “reset” operation. However, when a high positive voltage higher than a certain voltage is applied during the “reset” operation, dielectric breakdown occurs in the solid electrolyte layer. Once the dielectric breakdown has occurred, the state remains lower than the normal ON state, and the resistance does not change thereafter. When this positive voltage is applied, a voltage that causes dielectric breakdown is called a dielectric breakdown voltage. Therefore, by designing and manufacturing an element so that the dielectric breakdown voltage becomes high, a high reset voltage can be applied, and an off state with higher resistance can be obtained.

  There is known a method of forming a resistance change element, particularly, such a solid electrolyte switch element using a metal bridge formation inside a copper multilayer wiring on a semiconductor device. For example, Patent Literature 2 and Patent Literature 3 disclose a two-terminal solid electrolyte switch element provided inside a copper multilayer wiring structure on a CMOS substrate and a method of manufacturing the same. Patent Literature 2 and Patent Literature 3 disclose an active electrode for supplying metal ions into a solid electrolyte by providing a copper wiring itself exposed by opening a part of an insulating layer inside a copper multilayer wiring structure on a CMOS substrate. A two-terminal type solid electrolyte switch element is manufactured by using the method described above.

  In the case of using a copper electrode as the lower electrode in manufacturing the solid electrolyte switch element, if the surface of the copper electrode is oxidized, the leakage current and the variation in the off-leak current in the “off state” when a negative voltage is applied increase. Further, the application of the positive voltage causes a decrease in the breakdown voltage during the “reset” operation. Non-Patent Document 3 discloses a method for solving this problem. In Non-Patent Document 3, in the process of forming a stacked structure of a solid electrolyte switch element, the free energy of oxidation is more negative than that of copper in order to prevent oxidation of the copper surface between copper as the lower electrode and the solid electrolyte layer. It has been proposed to deposit a large metal as a valve metal and provide a "buffer structure" that suppresses oxidation of copper by oxidizing the valve metal.

  Non-Patent Document 4 discloses a complementary resistance change element in which two resistance change elements having a structure in which two lower electrodes exposed in the same opening are opposed to each other are connected in series, and the reliability of the resistance state is improved. Techniques for improving are disclosed.

  Patent Document 4 relates to a switching element using an ion conductor, and it has been proposed that a plurality of switch elements are connected in parallel and an ion conductive layer or the like is commonly connected to form a selector element. Patent Document 5 relates to a variable resistance element using an ionic conductor, and it has been proposed that two variable resistance elements be connected via a common electrode, thereby functioning as a three-terminal solid electrolyte switch. ing.

JP 2011-187925 A JP 2011-91317 A International Publication No. 2010/079816 International Publication No. 2008/001712 JP 2014-38984 A

M.N.Kozicki, et al., "Information storage using nanoscale electrodeposition of metal in solid electrolytes", Superlattices and Microstructures, Vol.34, p.459-465, 2003. R. Waser, et al., "Nanoionics-based resistive switching memories", Nature Materials, Vol. 6, p. 833-840, 2007. M. Tada, et al., "Improved ON-State Reliability of Atom Switch Using Alloy Electrodes", IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.60, No.10, p.3534-3540, 2013 M. Tada, et al., "Improved Off-State Reliability of Nonvolatile Resistive Switch With Low Programming Voltage", IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.59, No. 9, p.2357-2362, 2012

  In order to improve the operation yield of the variable resistance element formed in the multilayer copper wiring layer, it is necessary to suppress the variation of the “set voltage” required to change from the “off state” to the “on state”. Desired.

  However, in the configurations disclosed in Non-Patent Documents 3 and 4, the effect of improving the variation of the “set voltage” has not been obtained.

  In addition, if the voltage required for setting is higher than a predetermined applied programming voltage due to the variation of the “set voltage” between the complementary elements, the setting cannot be performed, and the operation yield of the element cannot be improved.

  Therefore, there is a need for a complementary resistance change element that suppresses the variation of the “set voltage” between the complementary resistance change elements and improves the operation yield.

  The present invention has been made to solve the problems of the above-described technology. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device employing a configuration of a variable resistance element in which variation in set voltage between elements is improved, and a method for forming the same.

To achieve the above object, a semiconductor device of the present invention comprises:
A semiconductor device including at least two or more variable resistance elements, a first terminal (first wiring), and a second terminal (second wiring),
The variable resistance elements are respectively:
A first electrode, a second electrode, and a variable resistance layer sandwiched between the first electrode and the second electrode;
A function of reversibly changing a resistance value based on an electric signal applied between the first electrode and the second electrode;
Each first electrode of the variable resistance element is electrically connected to a first terminal, and each second electrode is electrically connected to a second terminal, and
Each of the variable resistance layers is separated from each other between at least two or more variable resistance elements,
The respective second electrodes are separated from each other between the respective variable resistance elements, and are electrically connected to each other only through the second terminal.

Further, the method for manufacturing a semiconductor device of the present invention includes
A method of manufacturing a semiconductor device having a plurality of variable resistance elements provided in a multilayer copper wiring layer on a semiconductor substrate,
Forming an insulative barrier film on a copper wiring that also serves as a first electrode electrically connected to the first terminal;
Forming an opening in the insulating barrier film to expose a surface of the copper wiring also serving as the first electrode;
A step of sequentially forming a buffer layer and a solid electrolyte layer on the entire surface including the opening,
Forming a second electrode connected to a second terminal on the solid electrolyte layer.

  According to the present invention, when a programming voltage is simultaneously applied to a plurality of resistance change elements connected in parallel, and among them, the resistance change element having the lowest set voltage is turned on, the plurality of resistance change elements become constituent elements. Since the semiconductor device described as “set”, the variation of the “set voltage” of the semiconductor device can be suppressed. In other words, the variation of the “set voltage” among the plurality of variable resistance elements, which is a component of the semiconductor device, is not suppressed, but the variation of the “set voltage” of the semiconductor device of the present invention is suppressed.

FIG. 3 is a partial cross-sectional view showing a variable resistance element that is a component of the semiconductor device of the present invention. FIG. 2 is a partial cross-sectional view illustrating a configuration example of a two-terminal semiconductor device according to the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of the semiconductor device according to the first embodiment illustrated in FIG. 2. 5 is a graph comparing a standardized set voltage distribution in a case where two variable resistance elements of 2 Mb scale are connected in parallel with two variable resistance elements in the first embodiment. It is a partial sectional view showing an example of 1 composition of a three-terminal semiconductor device of a 2nd embodiment. FIG. 4 is a circuit diagram illustrating a configuration example of a three-terminal semiconductor device according to a second embodiment. FIG. 13 is a partial cross-sectional view schematically illustrating a configuration of a solid electrolyte switch element including a buffer layer and used as a variable resistance element included in a semiconductor device according to a third embodiment. FIG. 9 schematically illustrates a configuration of a solid electrolyte switch element including a buffer layer including a first metal oxide layer and a second metal oxide layer, which can be used as a variable resistance element included in the semiconductor device according to the third embodiment. 3 is a partial sectional view shown in FIG. A solid electrolyte including a buffer layer including a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer, which can be used as a variable resistance element included in the semiconductor device according to the third embodiment. FIG. 3 is a partial cross-sectional view schematically illustrating a configuration of a switch element. FIG. 14 is a partial cross-sectional view schematically illustrating an example of a configuration provided inside a multilayer wiring structure formed on a semiconductor substrate in a semiconductor device according to a fourth embodiment. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 16 is a partial cross-sectional view for explaining a manufacturing process of a variable resistance element applied when the semiconductor device of the fourth embodiment is provided inside a multilayer wiring structure on a semiconductor substrate. FIG. 13 is a cross-sectional view schematically illustrating a configuration of a three-terminal variable resistance element provided inside a multilayer wiring structure formed on a semiconductor substrate based on the variable resistance element according to the third embodiment and a method for manufacturing the same. . 9 is a table showing the results of measuring the off-leakage current when a negative voltage of 1 V is applied to the variable resistance element of Embodiment 1 and a variable resistance element as a comparative example. 9 is a table showing the results of measuring the dielectric breakdown voltage at the time of reset for the variable resistance element according to the first embodiment and the variable resistance element as a comparative example.

  Before describing embodiments of the present invention in detail, the meanings of terms used in the specification will be described.

  The semiconductor substrate includes a semiconductor element including a MOS transistor and a resistance element, and a substrate on which a semiconductor device in which these semiconductor elements are combined is configured. Further, the semiconductor substrate includes a substrate such as a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, and a substrate for manufacturing a liquid crystal.

  The plasma CVD (Chemical Vapor Deposition) method is, for example, a method in which a gaseous material or a gaseous liquid material (gas molecules) is continuously supplied to a reaction chamber under reduced pressure, and the molecules are excited by plasma energy. This is a method for forming a continuous film on a substrate by a gas phase reaction, a substrate surface reaction, or the like.

  The CMP (Chemical Mechanical Polishing) method is a method in which irregularities on a wafer surface generated during a multilayer wiring forming process are planarized by bringing a polishing liquid into contact with a rotating polishing pad while flowing a polishing liquid over the wafer surface. . The CMP method is used not only when the interlayer insulating film is polished and flattened, but also when an embedded wiring called a damascene wiring is formed. In the case where copper (Cu) is used as a wiring material, a method of forming a damascene wiring will be briefly described. Cu is formed on the insulating film in which a groove is formed in advance. Thereafter, excess Cu on the insulating film is polished and removed by the CMP method, leaving Cu embedded in the groove. Thus, a damascene wiring in which Cu is embedded in the groove is formed.

  The barrier metal refers to a conductive film having a barrier property that covers the side and bottom surfaces of the wiring in order to prevent metal elements forming the wiring from diffusing into an interlayer insulating film or a lower layer. For example, when the material forming the wiring is a metal containing Cu as a main component, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), carbonitride is used to prevent diffusion of copper (Cu). A high melting point metal such as tungsten (WCN) or a nitride thereof, or a laminated film thereof is used as a barrier metal. These films can be easily processed by dry etching and have good compatibility with an LSI manufacturing process before Cu is used as a wiring material.

  The barrier insulating film is formed on the upper surface of the Cu wiring and has a function of preventing oxidation of Cu and diffusion of Cu into the insulating film, and a role as an etching stopper layer during processing. For example, a SiC film, a SiCN film, a SiN film, or a stacked film thereof is used as a barrier insulating film.

  Hereinafter, a variable resistance element according to a preferred embodiment of the present invention and a method for manufacturing the same will be described in detail with reference to the drawings. However, in each embodiment, the present invention will be described in a technically preferable mode for carrying out the present invention, but the scope of the invention is not limited to the embodiment described below.

(First embodiment)
The configuration of the semiconductor device according to the first embodiment of the present invention will be described.

  FIG. 1 is a partial cross-sectional view showing a configuration of a variable resistance element, which is a component of the semiconductor device of the present invention. Notation is adopted.

  FIG. 2 is a partial cross-sectional view illustrating a configuration example of the two-terminal semiconductor device according to the first embodiment.

  FIG. 3 is a circuit diagram showing a circuit configuration of one configuration example of the two-terminal semiconductor device of the first embodiment shown in FIG. In the circuit diagram, the connection form of the terminal of each variable resistance element is indicated by a symbol.

The two-terminal semiconductor device according to the first embodiment is a two-terminal semiconductor device 150 including two variable resistance elements 151a and 151b, a first terminal 153, and a second terminal 154.
Each of the two variable resistance elements 151a and 151b has a first electrode 1, a second electrode 2, and a variable resistance layer 3 sandwiched between the first electrode 1 and the second electrode 2, respectively. A function of reversibly changing a resistance value based on an electric signal applied between the electrode 1 and the second electrode 2;
The first electrode 1 of each of the two variable resistance elements 151a and 151b is electrically connected to the first terminal 153, and the second electrode 2 and the second terminal 154 are electrically connected in parallel.

  Further, as shown in FIG. 2, the resistance change layers 3 of the individual resistance change elements 151a and 151b are separated from each other and independent. When the resistance change layer 3 and the second electrode 2 are not separated and processed between the individual resistance change elements connected in parallel, and the common resistance change layer and the common second electrode are used, respectively, two resistance change When the element shapes are different from each other, the variation (difference) in characteristics between the two variable resistance elements increases due to the difference in shape between the two variable resistance elements. By separating and processing the variable resistance layer 3 and the second electrode 2 between the plurality of variable resistance elements, the shapes of the individual variable resistance elements connected in parallel can be made uniform. Variations (differences) in characteristics between the variable elements can be reduced.

  Note that in the configuration example of the two-terminal semiconductor device illustrated in FIG. 2, both the first terminal 153 and the second terminal 154 have a wiring shape. At this time, the first electrode 1 of each of the variable resistance elements 151a and 152b is in direct contact with the first terminal 153, and the second electrode 2 is connected to the second terminal 154 via each. It is. The configuration of the two-terminal semiconductor device shown in FIG. 2 is an example of the two-terminal semiconductor device of the first embodiment, and the first electrodes 1 of the two variable resistance elements 151a and 151b are If both the first electrode 153 and the second electrode 2 are electrically connected to the second terminal 154, the two variable resistance elements are electrically connected in parallel. For example, a configuration in which the first electrodes 1 of the two variable resistance elements 151a and 152b also serve as the first terminal 153 can be selected. In addition, a configuration in which the second electrode 2 is directly in electrical contact with the second terminal 154 without using a via can be selected. Furthermore, as the shape of the first terminal 153 or the second terminal 154, an island-shaped terminal shape can be selected instead of a wiring shape.

  In the two-terminal semiconductor device according to the first embodiment, when a programming voltage is applied between the first terminal 153 and the second terminal 154, of the two resistance change elements 151a and 151b connected in parallel, When one of the variable resistance elements having a lower “set voltage” changes from the “off (high resistance) state” to the “on (low resistance) state”, the entire two-terminal semiconductor device 150 also turns off (high resistance). ) State changes to the ON (low resistance) state. That is, when the applied programming voltage reaches a lower “set voltage” among the “set voltages” of the two variable resistance elements 151a and 151b, the entire two-terminal semiconductor device 150 is “set”. When one of the two resistance change elements connected in parallel is turned on, it becomes difficult to further increase the applied “programming voltage” and to increase the “set voltage” of the other resistance change elements. As a result, the applied programming voltage exceeds the “set voltage” of one of the variable resistance elements, which is already in the “ON state”, but does not reach the “set voltage” of the other variable resistance element. Therefore, even after the programming operation, the other variable resistance element having the higher “set voltage” remains in the “off state”.

  Here, the application condition of the “programming voltage” necessary for the “set” operation of the two-terminal semiconductor device of the first embodiment is that the “set voltage” of the two “resistance change elements” and the peripheral circuit And the desired "ON state" resistance value. The application of the “programming voltage” may be a pulse application or a sweep application. The “programming voltage” may be applied in any “applied voltage polarity” as long as the potential of the second terminal 154 is “negative voltage” with reference to the potential of the first terminal 153.

  Next, in the case of the “reset” operation, a “reset voltage” is applied between the first terminal 153 and the second terminal 154 as in the “set” operation. At this time, the “reset current” flows through only one of the variable resistance elements that is in the “ON state”. Therefore, the “reset operation” is performed in one of the resistance change elements that is in the “ON state”. On the other hand, no current is supplied to the other variable resistance elements originally remaining in the “off state”, so that there is no effect. As a result, when one of the variable resistance elements that has been in the “ON state” returns to the “OFF state”, the entire two-terminal semiconductor device 150 in which the variable resistance elements 151a and 151b are connected in parallel also has the “OFF state”. Return to. Thus, as in the "set" operation, also in the "reset" operation, of the two resistance change elements connected in parallel, the "set voltage" is lower. Causes a change in resistance.

  FIG. 4 shows a case where the two-terminal semiconductor device according to the first embodiment is "set" in which a single variable resistance element of 2 Mb scale and a two-terminal semiconductor device in which two variable resistance elements are connected in parallel are set. 4 is a graph comparing the normalized “set voltage” distribution. The median value of the “set voltage” variation (distribution) of the variable resistance element alone is normalized to 0, and its standard deviation is normalized to 1. The standard deviation representing the “set voltage” variation (distribution) of the entire two-terminal semiconductor device in which two variable resistance elements are connected in parallel is reduced from 1 to 0.83. At the same time, in the case of a single variable resistance element, the standardized minimum applied programming voltage required to “set” all the 2 Mb elements is 4.8, but a two-terminal type in which two variable resistance elements are connected in parallel. In the case of a semiconductor device, it is confirmed that the normalized minimum applied programming voltage required to “set” all the 2 Mb elements is reduced to 3.0.

  In the first embodiment, as shown in FIGS. 2 and 3, a two-terminal semiconductor device in which two variable resistance elements 151a and 151b are connected in parallel is taken as an example, and the operation principle of the semiconductor device of the present invention is taken. Is explained. Even in the configuration of a two-terminal semiconductor device in which three or more variable resistance elements are connected in parallel, the operation principle is essentially the same. The greater the number of variable resistance elements connected in parallel that constitute the two-terminal semiconductor device, the higher the probability that a variable resistance element having a lower “set voltage” is included. In other words, among the plurality of resistance change elements connected in parallel, the probability that a resistance change element having a “set voltage” lower than the median of the “set voltage” distribution of the resistance change element alone is increased. . As a result, when the number of the variable resistance elements connected in parallel is increased, the “set voltage” variation of the two-terminal semiconductor device in which the variable resistance elements are connected in parallel can be further reduced.

  In a two-terminal semiconductor device in which actual variable resistance elements are connected in parallel, each first electrode 1 and the first terminal 153 of the plurality of variable resistance elements are connected, and each second electrode 2 and the second terminal 154 are connected. Can be confirmed by various measuring instruments. For example, when the two-terminal semiconductor device 150 is formed in a multilayer copper wiring layer on a semiconductor substrate, individual “resistance change elements” are observed by transmission electron microscope (TEM) observation and scanning electron microscope (SEM) observation. By examining the first electrode 1 and the second electrode 2 and the connection form thereof, it can be confirmed that the above-described configuration is provided.

(Second embodiment)
The second embodiment of the present invention is a configuration of a three-terminal semiconductor device composed of a pair of the two-terminal semiconductor device 150 described in the first embodiment.

  A configuration of the three-terminal semiconductor device according to the second embodiment will be described. FIG. 5 is a partial cross-sectional view illustrating a configuration example of a three-terminal semiconductor device according to the second embodiment.

  FIG. 6 is a circuit diagram showing a configuration example of the three-terminal semiconductor device according to the second embodiment shown in FIG. In the circuit diagram, the connection form of the terminals of each variable resistance element is indicated by the symbol shown in FIG.

  As shown in FIG. 5, the three-terminal semiconductor device according to the present embodiment includes a pair of the two-terminal semiconductor devices 150a and 150b described in the first embodiment, and each of the two-terminal semiconductor devices 150a and 150b. Are electrically connected to the control terminal 157. On the other hand, the first terminal 153a of the two-terminal semiconductor device 150a and the first terminal 153b of the two-terminal semiconductor device 150b are electrically connected to the remaining two terminals of the three-terminal semiconductor device, respectively.

  In the three-terminal semiconductor device of the second embodiment, when a “programming voltage” is applied between the first terminal 153a and the control terminal 157 of the two-terminal semiconductor device 150a, the two terminals of the first embodiment are changed. In the same manner as described for the semiconductor device, one of the two variable resistance elements 151a and 151b constituting the two-terminal semiconductor device 150a and connected in parallel has a lower “set voltage”. When the “programming voltage” reaches the “set voltage”, the variable element changes resistance from “off (high resistance) state” to “on (low resistance) state”. That is, when the applied “programming voltage” reaches the lower “set voltage” of the “set voltages” of the two variable resistance elements 151a and 151b, the entire two-terminal semiconductor device 150a is “set”. You. When one of the two resistance change elements connected in parallel is turned on, it becomes difficult to further increase the applied “programming voltage” and to increase the “set voltage” of the other resistance change elements. As a result, the applied programming voltage exceeds the “set voltage” of one of the variable resistance elements, which is already in the “ON state”, but does not reach the “set voltage” of the other variable resistance element. Therefore, even after the “programming operation”, the other variable resistance element having the higher “set voltage” remains in the “off state”.

  Next, when a "programming voltage" is applied between the first terminal 153a and the control terminal 157 of the two-terminal semiconductor device 150b, the two-terminal semiconductor device Of the two variable resistance elements 151a and 151b, which are connected in parallel and constitute the 150b, one of the variable resistance elements having a lower “set voltage” has a “programming voltage” that reaches the “set voltage”. Then, the resistance changes from the “off (high resistance) state” to the “on (low resistance) state”. That is, when the applied “programming voltage” reaches the lower “set voltage” of the “set voltages” of the two variable resistance elements 151a and 151b, the entire two-terminal semiconductor device 150b is “set”. You.

  Also in the three-terminal semiconductor device of the second embodiment, the application conditions of the two-terminal semiconductor devices 150a and 150b and the "programming voltage" required for each "set" operation are determined by the configuration of each two-terminal semiconductor device. In addition to the "set voltage" of the two "variable resistance elements" used in the above, it is determined depending on the form of the peripheral circuit, the desired "ON state" resistance value, and the like. In the “set” operation of each of the two-terminal semiconductor devices 150a and 150b, the application of the “programming voltage” may be a pulse application or a sweep application. Further, as long as the potential of the control terminal 157 becomes “negative voltage” with reference to the potential of the first terminal 153a or the potential of the first terminal 153b, the application of the “programming voltage” is performed using any “applied voltage polarity”. May be.

  The two-terminal semiconductor device 150a and the two-terminal semiconductor device 150b are sequentially "set" and both are set to the "on state", whereby the first terminal 153a and the two-terminal semiconductor device constituting the two-terminal semiconductor device 150a are formed. The switching between the “high resistance state” and the “low resistance state” is performed between the two terminals of the first terminal 153b included in the device 150b. As a result, the two terminals of the first terminal 153a forming the two-terminal semiconductor device 150a and the first terminal 153b forming the two-terminal semiconductor device 150b were electrically connected with low resistance. State.

  In the three-terminal semiconductor device according to the second embodiment, each of the two-terminal semiconductor device 150a and the two-terminal semiconductor device 150b adopts a configuration in which the resistance change elements 151a and 151b are connected in parallel. It is possible to transmit an electric signal between the first terminal 153a and the first terminal 153b while reducing the variation of the “set voltage”.

  The operation mechanism of the “reset” operation of the two-terminal semiconductor device 150a and the two-terminal semiconductor device 150b is essentially the same as the operation mechanism described in the two-terminal semiconductor device of the first embodiment.

  In the "reset" operation, the "reset voltage" is applied between the control terminal 157 and the first terminal 153a or the first terminal 153b, similarly to the "set" operation. At this time, the “reset current” flows through only one of the variable resistance elements that is in the “ON state”. Therefore, the “reset operation” is performed in one of the resistance change elements that is in the “ON state”. On the other hand, no current is supplied to the other variable resistance elements originally remaining in the “off state”, so that there is no effect. As a result, when one of the variable resistance elements that has been in the “ON state” returns to the “OFF state”, the two-terminal type semiconductor device 150a in which the variable resistance elements 151a and 151b are connected in parallel, or the two-terminal type The entire semiconductor device 150b also returns to the “off state”. Thus, as in the "set" operation, also in the "reset" operation, of the two resistance change elements connected in parallel, the "set voltage" is lower. Causes a change in resistance.

  In the second embodiment, as shown in FIGS. 5 and 6, a three-terminal semiconductor device using two-terminal semiconductor devices 150a and 150b in which two variable resistance elements 151a and 151b are connected in parallel is used. The operation principle of the semiconductor device of the present invention will be described by way of example. The principle of operation is essentially the same in a three-terminal semiconductor device using a two-terminal semiconductor device in which three or more variable resistance elements are connected in parallel. Probability that a variable resistance element having a lower “set voltage” is included as the number of variable resistance elements connected in parallel and constituting a two-terminal semiconductor device used in the configuration of a three-terminal semiconductor device increases. Will be higher. In other words, among the plurality of resistance change elements connected in parallel, the probability that a resistance change element having a “set voltage” lower than the median of the “set voltage” distribution of the resistance change element alone is increased. . As a result, when the number of the variable resistance elements connected in parallel is increased, the “set voltage” variation of the two-terminal semiconductor device in which the variable resistance elements are connected in parallel can be further reduced.

  The three-terminal semiconductor device according to the second embodiment is an electric signal switch that transmits between the first terminal 153a and the first terminal 153b. On the other hand, when the first terminal 153a and the first terminal 153b are electrically connected, in the two-terminal semiconductor device 150 described in the first embodiment, the same as when connecting a total of four variable resistance elements in parallel. Configuration.

  The configuration of the three-terminal semiconductor device of the second embodiment is also a pair of two two-terminal semiconductor devices 150a and 150b, and the second terminal 154a that configures each of the two-terminal semiconductor devices 150a and 150b. It can be confirmed by various measuring instruments that both the 154b and the control terminal 157 are electrically connected. For example, when the three-terminal semiconductor device according to the second embodiment is formed in a multilayer copper wiring layer on a semiconductor substrate, the first electrode 1 of each “resistance change element” is observed by TEM observation and SEM observation. The configuration described above can be confirmed by examining the form of connection between the second electrode 2 and the second terminals 154a and 154b and the control terminal 157.

(Third embodiment)
The semiconductor device according to the third embodiment has a configuration in which a solid electrolyte switching element is used as a variable resistance element used in the configuration of the two-terminal semiconductor device described in the first embodiment.

  FIG. 7A is a partial cross-sectional view schematically illustrating a configuration of a solid electrolyte switching element used as a variable resistance element included in the semiconductor device according to the third embodiment.

  As shown in FIG. 7A, the solid electrolyte switch element 159 used in the third embodiment includes a first electrode 1, a second electrode 2, and a resistance change between the first electrode 1 and the second electrode 2. And a layer 3. The resistance change layer 3 is composed of a buffer layer 4 and a solid electrolyte layer 5 through which metal ions can be conducted, in the order close to the first electrode 1.

  The first electrode 1 is made of a material serving as a supply source of metal ions. Preferably, the first electrode 1 is made of a metal material containing copper from the viewpoint of controllability of metal ionization and supply, and the metal ions supplied from this metal material are copper ions.

  The second electrode 2 is made of a material containing a metal that is less ionizable than the metal material used for the first electrode 1. Preferably, the second electrode 2 is made of a material containing Ru from the viewpoint of ease of electrode processing.

  The buffer layer 4 is provided in contact with the entire surface of the first electrode 1 and is made of a material capable of suppressing oxidation of the surface of the first electrode 1. For the purpose of suppressing oxidation of a metal material containing copper, preferably, the buffer layer 4 is preferably made of a material containing at least one of Al, Hf, Ta, Ti, and Zr.

  The solid electrolyte layer 5 has a role of dissolving metal ions supplied from the first electrode 1 by applying a voltage between the first electrode 1 and the second electrode 2. The metal ions, for example, copper ions, dissolved in the solid electrolyte layer 5 are transported by the electric field resulting from the voltage applied between the first electrode 1 and the second electrode 2. In addition, due to the electric field caused by the applied voltage, copper ions are easily eluted from the metal material containing copper, or the copper ions can be reduced to copper and recovered. 5 is made. As the solid electrolyte material for forming the solid electrolyte layer 5, a material that causes little material deterioration due to a switching cycle is preferable. Therefore, the solid electrolyte layer 5 uses, for example, an oxide containing at least one of Al, Co, Fe, Hf, Mn, Si, Ta, Ti, Zn, and Zr, or chalcogenide, amorphous Si, SiOCH, or the like. It is produced.

  The semiconductor device of the third embodiment is a semiconductor device in which at least two or more solid electrolyte switch elements are connected in parallel as variable resistance elements. In the semiconductor device according to the third embodiment, which is manufactured by using the solid electrolyte switch element, the set voltage variation is suppressed similarly to the two-terminal semiconductor device having the configuration described in the first embodiment. Becomes possible.

(Fourth embodiment)
The semiconductor device of the fourth embodiment has a configuration in which the two-terminal semiconductor device of the first embodiment is provided inside a multilayer wiring structure formed on a semiconductor substrate.

  FIG. 8 schematically illustrates an example of a configuration of a semiconductor device according to the fourth embodiment in which a solid electrolyte switch element is employed as a variable resistance element and is provided inside a multilayer wiring structure formed on a semiconductor substrate. 3 is a partial sectional view shown in FIG.

  As shown in FIG. 8, a solid electrolyte switch element 159 is provided on a semiconductor substrate 101 via a first interlayer insulating film 102 as a variable resistance element. The solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment has the same configuration as the solid electrolyte switch element used in the configuration of the semiconductor device of the third embodiment.

  As shown in FIG. 7A, the solid electrolyte switch element 159 described in the third embodiment includes a first electrode 1 and a second electrode 2, and a resistance change layer sandwiched between the first electrode 1 and the second electrode 2. The variable resistance layer 3 includes a buffer layer 4 and a solid electrolyte layer 5 through which the metal ions can be conducted, in the order close to the first electrode 1. The solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment employs the configuration shown in FIG. 7B. In the configuration shown in FIG. 7B, the buffer layer 4 includes the first metal oxide layer 6 and the second metal oxide layer 7. Accordingly, the solid electrolyte switch element 159 used in the semiconductor device according to the fourth embodiment includes a lower wiring 106, a first metal oxide layer (not shown), a second metal oxide layer (not shown), and a solid electrolyte layer. 123, a first upper electrode 124, and a second upper electrode 125.

  As an example, the lower wiring 106, the first metal oxide layer, the second metal oxide layer, the solid electrolyte layer 123, and the first upper electrode 124 may have a configuration illustrated in FIG. The lower wiring 106 corresponds to the first electrode 1 shown in FIG. 7B. The first metal oxide layer 121 corresponds to the first metal oxide layer 6, and the second metal oxide layer 122 corresponds to the second metal oxide layer 7. The solid electrolyte layer 123 corresponds to the solid electrolyte layer 5, and the first upper electrode 124 corresponds to the second electrode 2. Since the operation principle of the solid electrolyte switch element having the configuration shown in FIG. 7B is the same as the operation principle of the solid electrolyte switch element having the configuration shown in FIG. 7A described in the third embodiment, in the fourth embodiment, A detailed description thereof will be omitted.

Also in the solid electrolyte switch element used in the fourth embodiment, by providing the first metal oxide layer 121, it is possible to more effectively reduce the leakage current and reduce the characteristic variation between elements. can do. In the solid electrolyte switching element used in the fourth embodiment, the first metal oxide layer 121 is formed of, for example, TiO _y1 having a 0.5 nm-thickness oxygen composition y1 satisfying 1.5 ≦ y1 ≦ 2.0. Can be produced.

In addition, the second metal oxide layer 127 functions as a passivation layer and can suppress oxidation of the lower wiring 106 including Cu in the lower layer. In the solid electrolyte switching element used in the fourth embodiment, the second metal oxide layer 122 is formed, for example, of AlO _x1 having a 0.3 nm-thickness oxygen composition x1 satisfying 1.3 ≦ x1 ≦ 1.5. Can be produced.

The solid electrolyte layer 123 can be made of, for example, a 6 nm-thick SiOCH film. The first upper electrode 124 can be made of, for example, Ru _0.5 Ti _0.5 with a thickness of 10 nm.

  The second upper electrode 125 is a conductive film having a barrier property, and is formed in order to prevent metal contained in the first upper electrode 124 that contacts the lower part from diffusing into the via plug 144 and the like. The second upper electrode 125 can be made of, for example, Ta having a thickness of 25 nm.

  As shown in FIG. 8, a second hard mask film 128 and a third hard mask film 129 are formed on a stacked body of the first upper electrode 124 and the second upper electrode 125 in the solid electrolyte switch element 159. The side surfaces of the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, the first upper electrode 124, the second upper electrode 125, the second hard mask film 128, and the third hard mask film 129; The upper surface of the first barrier insulating film 107 is covered with a protective insulating film.

  The lower wiring 106 is a wiring embedded via a first barrier metal 105 in a wiring groove formed in the second interlayer insulating film 103 and the first cap insulating film 104. By forming the lower wiring 106 with a metal material containing Cu as a main component, it is used as a lower electrode corresponding to the first electrode 1 in the solid electrolyte switch element having the configuration shown in FIG. 7B. With this configuration, the lower wiring 106 can have a function of ionizing Cu atoms in the lower wiring 106 to elute into the solid electrolyte layer 123. Further, by forming the lower wiring 106 with a Cu material configuration, a metal component which has not been formed into the first metal oxide layer 121 without being oxidized can be alloyed with Cu and diffused into the lower wiring 106. For example, when Cu is used for the lower wiring 106 and the main component of the first metal oxide layer 121 is an oxide made of Ti, the interface between the lower wiring 106 and the first metal oxide layer 121 is An alloy layer containing Cu and Ti as main components is formed.

  The solid electrolyte layer 123 and the lower wiring 106 are connected via an opening of the first barrier insulating film 107 via a first metal oxide layer 121 and a second metal oxide layer 122. At this time, the width of the lower wiring 106 connected to the solid electrolyte layer 123 via the metal oxide layer is preferably larger than the diameter of the opening of the barrier insulating film 107.

  The first barrier metal 105 is a conductive film having the same barrier properties as the second upper electrode 125. The first barrier metal 105 covers the side and bottom surfaces of the lower wiring 106. In the first barrier metal 105 formed of a conductive film having a barrier property, the metal contained in the lower wiring 106 diffuses into the first interlayer insulating film 102, the second interlayer insulating film 103, the first cap insulating film 104, and the like. To prevent In the formation of the first barrier metal 105, for example, when the lower wiring 106 is made of a metal material containing Cu as a main component, a refractory metal such as Ta, TaN, TiN, WCN, a nitride thereof, or the like. A laminated film is used.

  The upper wiring 145 is a wiring buried in a wiring groove formed in the third interlayer insulating film 141 and the second cap insulating film 142 via the second barrier metal 143. The upper wiring 145 is integrated with the via plug 144. The via plug 144 is embedded via a second barrier metal 143 in a lower hole formed in the protective insulating film 130, the third hard mask film 129, and the second hard mask film 128. The via plug 144 is electrically connected to the first upper electrode 124 and the second upper electrode 125 of the solid electrolyte switch element 159 via the second barrier metal 143. The upper wiring 145 and the via plug 144 are manufactured using, for example, Cu.

  The second barrier metal 143 is a conductive film having the same barrier properties as the first barrier metal 105. The second barrier metal 143 covers the side surface and the bottom surface of the upper wiring 145 and the via plug 144. The second barrier metal 143 formed of a conductive film having a barrier property includes a metal contained in the upper wiring 145 and the via plug 144, the first via interlayer insulating film 140, the third interlayer insulating film 141, and the second cap insulating film. 142 to prevent diffusion. For example, when the upper wiring 145 and the via plug 144 are made of a metal material containing Cu as a main component, the second barrier metal 143 is formed of Ta, TaN, TiN, and WCN, similarly to the first barrier metal 105. Such a high melting point metal, its nitride, or the like, or a laminated film thereof is used.

  The second barrier metal 143 is preferably made of the same material as the second upper electrode 125 which is a part of the configuration of the solid electrolyte switch element 159, from the viewpoint of reducing the contact resistance. For example, when the second upper electrode 125 is formed of Ta, it is preferable to use Ta also for manufacturing the second barrier metal 143 that contacts the upper portion.

The third hard mask film 129 is a film that becomes a hard mask when the second hard mask film 128 is etched. The third hard mask film 129 is preferably a different type of film from the second hard mask film 128. For example, when the second hard mask film 128 is a SiCN film, it is possible to use an SiO ₂ film as the third hard mask film 129.

  The protective insulating film 130 prevents the diffusion of constituent atoms (for example, copper ions) from the solid electrolyte switching element 159 to the first via interlayer insulating film 140 without damaging the solid electrolyte switching element 159 with the exposed side surfaces. An insulating film having a function. For forming the protective insulating film 130, for example, a SiN film, a SiCN film, or the like can be used. The first barrier insulating film 107 and the second barrier insulating film 146 are insulating films having a function of preventing diffusion of metal (for example, copper ions).

  In the semiconductor device of the fourth embodiment, as shown in FIG. 8, the lower wiring 106 corresponding to the first electrode 1 and the first metal oxide layer are formed through the opening provided in the first barrier insulating film 107. 121. With this configuration, a Cu electrode that also serves as a Cu wiring can be used as the first electrode 1, and a resistance change element using the Cu electrode can be formed in a multilayer wiring structure on a CMOS substrate. Since the lower electrode of the variable resistance element also has the function of the Cu wiring, the manufacturing process can be simplified.

  Next, a method for manufacturing a solid electrolyte switch element that can be used as a component of the semiconductor device according to the fourth embodiment will be described in the case of the solid electrolyte switch element shown in FIG. 9J that employs the configuration shown in FIG. 7B. I do. The semiconductor device of the fourth embodiment shown in FIG. 8 can be manufactured by applying the manufacturing method of FIGS. 9A to 9J, in which a variable resistance element is provided inside a multilayer wiring structure on a semiconductor substrate.

  9A to 9J are partial cross-sectional views for explaining a manufacturing method for providing a solid electrolyte switch element employing the configuration shown in FIG. 7B inside a multilayer wiring structure on a semiconductor substrate.

First, a first interlayer insulating film 102, a second interlayer insulating film 103, and a first cap insulating film 104 are sequentially formed on a semiconductor substrate 101. The semiconductor substrate 101 here may be the semiconductor substrate itself or a substrate having a semiconductor element (not shown) formed on the substrate surface. For example, the first interlayer insulating film 102 is a 300 nm thick SiO ₂ film, the second interlayer insulating film 103 is a 150 nm thick SiOCH film, and the first cap insulating film 104 is a 100 nm thick SiO ₂ film. Can be made.

  Subsequently, a wiring groove is formed in the laminated film of the first cap insulating film 104, the second interlayer insulating film 103, and the first interlayer insulating film 102 by using a lithography method. This lithography method includes a photoresist forming process for forming a resist of a predetermined pattern on the first cap insulating film 104, a dry etching process for performing anisotropic etching on the laminated film using the resist as a mask, and an etching process. And removing the resist after forming the wiring groove.

  After that, a metal is buried in the wiring groove via the first barrier metal 105 to form the lower wiring 106. The first barrier metal 105 can be formed, for example, with a stacked structure of TaN (thickness: 5 nm) / Ta (thickness: 5 nm). As a material of the lower wiring 106, for example, Cu can be used.

Subsequently, a first barrier insulating film 107 is formed on the first cap insulating film 104 including the lower wiring 106. The first barrier insulating film 107 can be formed of, for example, a 30-nm-thick SiCN film. Next, as shown in FIG. 9A, a first hard mask film 108 is formed on the first barrier insulating film 107. The first hard mask film 108 is preferably made of a material different from that of the first barrier insulating film 107 from the viewpoint of maintaining a large etching selectivity in dry etching. Here, when the first barrier insulating film 107 is formed of a SiCN film, the first hard mask film 108 can be manufactured using, for example, an SiO ₂ film. When the first barrier insulating film 107 is formed of a 30-nm-thick SiCN film, the first hard mask film 108 can be formed using, for example, a 40-nm-thick SiO ₂ film.

Subsequently, a photoresist having a predetermined opening pattern is formed on the first hard mask film 108 and dry etching is performed to form an opening in the first hard mask film 108. The photoresist is removed by O ₂ plasma ashing or the like. Then, by etching back the first barrier insulating film 107 exposed at the bottom of the opening of the first hard mask film 108, an opening exposing a part of the upper surface of the lower wiring 106 is formed in the first barrier insulating film 107. Form. The first hard mask film 108 is formed by using a SiO ₂ film having a thickness of 40 nm, and is thereby etched and removed during the etch back. After the etch back, as shown in FIG. 9B, the surface of the lower wiring 106 exposed at the bottom of the opening is cleaned by plasma irradiation using an organic solvent or a gas containing H ₂ or an inert gas.

  Step A1 is performed until the structure shown in FIG. 9A to FIG. 9B is formed.

In step A1, when the first barrier insulating film 107 is an SiN film or a SiCN film, the etch-back at the time of forming the opening of the first barrier insulating film 107 can be performed using plasma containing CF _4. It is. The conditions are, for example, a condition of a gas flow rate of CF ₄ / Ar = 25/50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 90 W. By lowering the source power or increasing the substrate bias, the ionicity at the time of etching can be improved, and the side wall of the first barrier insulating film 107 can be formed into a tapered shape. Further, the first hard mask film 108 can be removed by etching by this etch back.

  Next, as shown in FIG. 9C, a first metal layer 161 used for forming the first metal oxide layer 121 on the first barrier insulating film 107 including the opening where the lower wiring 106 is exposed, and A second metal layer 162 used to form the second metal oxide layer 122 is deposited in this order. The first metal layer 161 includes at least one of Ti, Zr, and Hf. The second metal layer 162 includes at least one of Al, Nb, and Ta. As an example, the first metal layer 161 can be formed using a 0.5-nm-thick Ti film, and the second metal layer can be formed using a 0.2-nm-thick Al film.

After depositing the first metal layer 161 and the second metal layer 162, the first metal layer 161 and the second metal layer 162 are irradiated with a gas containing O ₂ under reduced pressure without exposing to the atmosphere. Is oxidized. Subsequently, by performing a vacuum heat treatment under a reduced pressure at a temperature higher than the film formation temperature, the first metal oxide layer 121 and the second metal oxide layer 122 are simultaneously formed as illustrated in FIG. 9C.

  Next, a solid electrolyte layer 123 is deposited on the formed second metal oxide layer 122. For example, a 6-nm-thick SiOCH film can be used for manufacturing the solid electrolyte layer 123. In this case, the solid electrolyte layer 123 is deposited by a plasma CVD method, and subsequently, an inert gas plasma treatment is performed.

Subsequently, a first upper electrode 124 and a second upper electrode 125 are formed in this order on the solid electrolyte layer 123 by DC sputtering. The lower wiring 106, the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, the first upper electrode 124, and the second upper electrode 125 constitute a stacked body that becomes the solid electrolyte switch element 159. . The first upper electrode 124 can be formed of, for example, a Ru _0.5 Ti _0.5 film having a thickness of 10 nm. The second upper electrode 125 can be formed of, for example, a Ta film having a thickness of 25 nm. When the first upper electrode 124 is made of Ru or a Ru alloy, the first upper electrode 124 is continuously deposited without being exposed to the air after the deposition of the first upper electrode 124 in order to prevent surface oxidation of the first upper electrode 124. Preferably, two upper electrodes 125 are deposited.

Subsequently, as shown in FIG. 9D, a second hard mask film 128 and a third hard mask film 129 are laminated on the second upper electrode 125 in this order. The second hard mask film 128 is preferably made of the same material as the first barrier insulating film 107 from the viewpoint of adhesion, and can be formed of, for example, a 30-nm-thick SiCN film. The third hard mask film 129 can be made of, for example, an SiO ₂ film having a thickness of 100 nm.

  Step A2 is performed until the structure shown in the order of FIGS. 9C to 9D is formed.

  In Step A2, the first metal layer 161 and the second metal layer 162 can be deposited by a vapor deposition method using resistance heating of a metal raw material, electron beam irradiation, laser irradiation, or a DC sputtering method. As an example, when the first metal layer 161 is formed of a Ti film, a DC sputtering method is used with a target of Ti, a sputtering power of 100 W, a substrate temperature of room temperature, an Ar flow rate of 20 sccm, and a pressure of 0.5 Pa. Thus, a 0.5 nm-thick Ti film for the first metal layer 161 can be deposited. When the second metal layer 162 is formed of an Al film, a DC sputtering method is used, Al is used as a target, a sputtering power of 150 W, a substrate temperature of room temperature, an Ar flow rate of 20 sccm, and a pressure of 0.5 Pa are used. Thus, an Al film having a thickness of 0.2 nm for the second metal layer 162 can be deposited.

Further, in step A2, without air exposure, by performing the oxidation treatment with a gas radiation containing O _2, a first metal oxide layer 121 is formed by oxidation of the first metal layer 161, and a second The degree of oxidation of the second metal oxide layer 122 formed by oxidation of the metal layer 162 can be controlled with high accuracy. As an example, when the first metal layer 161 is formed of a 0.5-nm-thick Ti film and the second metal layer 162 is formed of a 0.2-nm-thick Al film, the substrate temperature is reduced to room temperature. The first metal oxide layer 121 made of Ti oxide and the second metal oxide layer made of Al oxide are irradiated by O ₂ gas irradiation at an O ₂ flow rate of 10 sccm, a pressure of 0.5 Pa, and an irradiation time of 60 seconds. 122 can be formed.

Further, in step A2, for example, in the heat treatment after the above-described oxidation treatment, the first metal layer 161 is formed of a 0.5-nm-thick Ti film, and the second metal layer 162 is formed of a 0.2-nm-thick film. It is preferable to perform the process at a substrate temperature of 400 ° C. or less at a flow rate of N ₂ and O _{2 of} 10/10 sccm, a pressure of 900 Pa, and a processing time of 30 seconds. Due to this heat treatment, the metal component Ti in the first metal oxide layer 121, which has remained unreacted in the above-described oxidation treatment, is diffused by alloying diffusion on the surface of the lower wiring 106 made of Cu. It can be removed from the layer 121. Further, vacuum means a state in which the pressure in the chamber is as low as possible, and is at least lower than the above-described oxidation treatment. The thickness of the first metal oxide layer 121 is preferably 1.0 nm or less, and the thickness of the second metal oxide layer 122 is preferably 0.8 nm or less.

  When an SiOCH film is used for the solid electrolyte layer 123 in Step A2, the SiOCH film is formed by a plasma CVD method under the following conditions. The raw material is a liquid SiOCH monomer molecule, the substrate temperature is 400 ° C. or less, the He flow rate is 500 to 2000 sccm, the raw material flow rate is 0.1 to 0.8 g / min, the plasma CVD chamber pressure is 360 to 700 Pa, and the RF power is 20 to 100 W. The SiOCH film for the solid electrolyte layer 123 can be deposited. Specifically, the SiOCH film for the solid electrolyte layer 123 can be deposited under the conditions of a substrate temperature of 350 ° C., a He flow rate of 1500 sccm, a raw material flow rate of 0.75 g / min, a plasma CVD chamber pressure of 470 Pa, and an RF power of 50 W. In the inert plasma treatment after depositing the SiOCH film for the solid electrolyte layer 123, He is used as an inert gas, the substrate temperature is set to 400 ° C. or less, the He flow rate is 500 to 1500 sccm, and the plasma chamber pressure is 2.7 to 3. It can be performed by setting the RF power to 5 Torr and the RF power to 20 to 200 W, respectively. Specifically, it can be performed under the conditions of a substrate temperature of 350 ° C., a He flow rate of 1000 sccm, a plasma chamber pressure of 360 Pa, an RF power of 50 W, and a processing time of 30 seconds. By this inert plasma treatment, the adhesion to the first upper electrode 124 to be deposited next can be improved.

Further, in the step A2, for example, when a Ru _0.5 Ti _0.5 alloy film is used for manufacturing the first upper electrode 124, a Ru _0.5 Ti _0.5 alloy film may be deposited by simultaneous DC sputtering using Ru and Ti as targets. it can. A Ru _0.5 Ti _0.5 alloy film can be deposited by using a sputtering power of Ru of 120 W, a sputtering power of Ti of 150 W, a substrate temperature of room temperature, an Ar flow rate of 20 sccm, and a pressure of 0.5 Pa. After the deposition of the first upper electrode 124, the second upper electrode 125 is deposited continuously without being exposed to the air. For example, in the case where the second upper electrode 125 is formed of Ta having a thickness of 25 nm, DC sputtering is performed using Ta as a target at a sputtering power of 300 W, a substrate temperature of room temperature, an Ar flow rate of 25 sccm, and a pressure of 0.5 Pa. By using this, after depositing the Ru _0.5 Ti _0.5 alloy film, a Ta film can be deposited continuously without exposure to the air.

  In step A2, both the second hard mask film 128 and the third hard mask film 129 can be formed by using a general plasma CVD method in the technical field of semiconductor manufacturing. At the time of film formation by the plasma CVD method, the film formation temperature can be selected from a range of 200 ° C. to 400 ° C. Here, at the time of film formation by the plasma CVD method, the film formation temperature can be selected to be 350 ° C.

Next, after forming a photoresist having a processed pattern of the variable resistance element 126 on the third hard mask film 129, the third hard mask film 129 is dry-etched until the second hard mask film 128 appears. Subsequently, after removing the photoresist by O ₂ plasma ashing, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, using the third hard mask film 129 as a mask. The second metal oxide layer 122 and the first metal oxide layer 121 are continuously dry-etched. FIG. 9E shows the state after the etching.

  After step A2, the process until the structure illustrated in FIG. 9E is formed is referred to as step A3.

In step A3, it is preferable that the dry etching of the third hard mask film 129 is stopped on the upper surface or inside the second hard mask film 128. In this case, since the solid electrolyte switch element 159 is covered with the second hard mask film 128, it is not exposed to O ₂ plasma. Further, the first upper electrode 124 containing Ru is not exposed to the O ₂ plasma. Therefore, occurrence of side etching on the first upper electrode 124 can be suppressed. Note that a general parallel plate type dry etching apparatus can be used for the dry etching of the third hard mask film 129.

  In step A3, each etching of the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide layer 121 is performed. Can also be performed collectively using a parallel plate type dry etcher.

Etching of the second hard mask film 128 (for example, SiCN film) can be performed under the conditions of a gas flow rate of CF ₄ / Ar = 25/50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 90 W.

In step A3, the etching of the second upper electrode 125 (for example, a Ta film) is performed at a substrate temperature of 90 ° C., a Cl ₂ gas flow rate of 50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 60 W. It can be carried out.

The first upper electrode 124 (for example, Ru _0.5 Ti _0.5 alloy film) is etched at a substrate temperature of room temperature, an O ₂ / Cl ₂ gas flow rate of 160/30 sccm, a pressure of 0.53 Pa, a source power of 300 to 600 W, It can be performed under the condition of a substrate bias power of 100 to 300 W.

Further, when the Ru _0.5 Ti _0.5 alloy film is used for the first upper electrode 124, the etching of the solid electrolyte layer 123 (for example, SiOCH film) can be performed under the same conditions as the etching of the first upper electrode 124. Therefore, the solid electrolyte layer 123 (SiOCH film) and the first upper electrode 124 (Ru _0.5 Ti _0.5 alloy film) can be collectively etched.

Further, a second metal oxide layer 122 (for example, an AlO _x1 film having a thickness of 0.3 nm and an oxygen composition x1 satisfying 1.3 ≦ x1 ≦ 1.5) and a first metal oxide layer 121 (for example, For the etching of a 0.5 nm-thick TiO _y1 film in which the oxygen composition y1 satisfies 1.5 ≦ y1 ≦ 2.0), when a Ru _0.5 Ti _0.5 alloy film is used for the first upper electrode 124, the solid electrolyte layer Similarly to 123 (SiOCH film), the etching can be performed under the same conditions as the etching of the first upper electrode 124 (Ru _0.5 Ti _0.5 alloy film). Therefore, the second metal oxide layer 122 (AlO _x1 film) and the first metal oxide layer 121 (TiO _y1 film) are combined with the first upper electrode 124 (Ru _0.5 Ti _0.5 alloy film) and the solid electrolyte layer 123 (SiOCH film). ) Can be performed collectively.

In step A3, under the above-described conditions, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide After each etching of the layer 121, the remaining thickness of the third hard mask film 129 made of a 100-nm-thick SiO ₂ film can be reduced to 50 nm.

  Next, as shown in FIG. 9F, the third hard mask film 129, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and A protective insulating film is deposited on the upper and side walls of the stacked structure including the first metal oxide layer 121 and the first barrier insulating film 107. The protective insulating film 130 is preferably formed using the same material as the first barrier insulating film 107 and the second hard mask film 128. For example, the protective insulating film 130 can be formed of a 30-nm-thick SiCN film.

Subsequently, as shown in FIG. 9F, a first via interlayer insulating film 140 is deposited on the protective insulating film 130 by using a plasma CVD method. The first via interlayer insulating film 140 can be made of, for example, a 210 nm-thick SiO ₂ film. Next, the first via interlayer insulating film 140 is planarized by using the CMP method. After the planarization, as shown in FIG. 9G, a third interlayer insulating film 141 and a second cap insulating film 142 are deposited on the first via interlayer insulating film 140 in this order. The third interlayer insulating film 141 is formed of a material different from that of the first via interlayer insulating film 140 in order to use the first via interlayer insulating film 140 that contacts the lower portion during etching as an etching stopper layer. The third interlayer insulating film 141 can be formed of, for example, an SiOCH film having a thickness of 150 nm.

  After step S3, the process until the structure illustrated in FIG. 9G is formed is referred to as step A4.

  In step A4, for example, when a SiCN film is used to form the protective insulating film 130, the protective insulating film 130 can be formed by plasma CVD at a substrate temperature of 200 ° C. using tetramethylsilane and ammonia as source gases. By forming the protective insulating film 130 using the SiCN film, all of the first barrier insulating film 107, the protective insulating film 130, and the second hard mask film 128 can be formed of the SiCN film. The first barrier insulating film 107, the protective insulating film 130, and the second hard mask film 128 are formed of the same material, and the periphery of the solid electrolyte switch element 159 is integrated and protected. Properties, water resistance, and oxygen desorption resistance can be improved, and the yield and reliability of the device can be improved.

  Further, in step A4, in flattening the first via interlayer insulating film 140, about 100 nm can be removed from the top surface of the first via interlayer insulating film 140, and the remaining film thickness can be reduced to about 110 nm. At this time, in the CMP (chemical-mechanical polishing) for the first via interlayer insulating film 140, polishing can be performed using a general colloidal silica or ceria-based slurry.

  In step A4, the third interlayer insulating film 141 and the second cap insulating film 142 can be deposited using a general plasma CVD method.

  Next, the upper wiring 145 and the via plug 144 shown in FIG. 9J are formed using the via-first method of the dual damascene method.

In the via-first method, first, a photoresist having a pattern of a via hole 147 for the via plug 144 shown in FIG. 9J is formed on the second cap insulating film 142. Subsequently, as shown in FIG. 9H, the second cap insulating film 142, the third interlayer insulating film 141, the first via interlayer insulating film 140, the protective insulating film 130, and the third hard mask film 129 were penetrated by dry etching. A via hole 147 for the via plug 144 is formed. Thereafter, as shown in FIG. 9H, the photoresist is removed by performing plasma ashing containing H ₂ gas and organic peeling.

Subsequently, a photoresist having a pattern of the wiring groove 148 for the upper wiring 145 shown in FIG. 9J is formed on the second cap insulating film 142, and then the second cap insulating film 142 and the third interlayer insulating film are formed by dry etching. A wiring groove 148 for the upper wiring 145 shown in FIG. 9J is formed in the film 141. Thereafter, as shown in FIG. 9I, the photoresist is removed by performing plasma ashing containing H ₂ gas and organic peeling.

  Step A5 is a step performed after the step A5 until the structure shown in FIG. 9I is formed.

  In step A5, after the via hole 147 is formed, an ARC (Anti-Reflection Coating: anti-reflection film) or the like is buried on the via hole 147 to prevent the bottom of the via hole 147 from penetrating when the wiring groove 148 is formed by dry etching. can do.

  Next, the second upper mask 125 is exposed from the via hole 147 by etching the second hard mask film 128 at the bottom of the via hole 147. Thereafter, the upper wiring 145 (for example, Cu) and the via plug 144 (for example, Cu) are simultaneously formed in the wiring groove 148 and the via hole 147 via the second barrier metal 143 (for example, a Ta film having a thickness of 10 nm). Thereafter, a second barrier insulating film 146 (for example, a 50 nm SiCN film) is deposited on the second cap insulating film 142 including the upper wiring 145, whereby the structure shown in FIG. 9J is formed.

  After step A5, the process until the structure illustrated in FIG. 9J is formed is referred to as step A6.

  In step A6, the formation of the upper wiring 145 can use the same process as the formation of the lower wiring 106 in the lower layer. At this time, the diameter of the bottom of the via plug 144 is preferably smaller than the diameter of the opening of the first barrier insulating film 107. In the solid electrolyte switch element 159 used for manufacturing the semiconductor device of the fourth embodiment, for example, the diameter of the bottom of the via plug 144 is selected to be 60 nm, and the diameter of the opening of the first barrier insulating film 107 is selected to be 100 nm. be able to.

  Further, in step A6, the contact resistance between the via plug 144 and the second upper electrode 125 is reduced by using the same material for the second barrier metal 143 and the second upper electrode 125. 159 can be reduced. As a result, device performance can be improved.

  Next, an embodiment of the above-described variable resistance element will be described.

(Embodiment 1)
In the first embodiment, the variable resistance element 126 according to the third embodiment that employs a variable resistance layer including a buffer layer and a solid electrolyte layer includes a first metal oxide layer 6 and a second metal oxide layer illustrated in FIG. 7B. The buffer layer 4 composed of the oxide layer 7 is employed. Using the configuration of the solid electrolyte switch element 159 shown in FIG. 9J, elements having different combinations of the first metal oxide layer 121 and the second metal oxide layer 122 are manufactured, and the characteristics of the manufactured variable resistance element are evaluated. did.

  In the first embodiment, the variable resistance element 126 of the third embodiment is used as a basic structure, and a buffer layer is formed, and a combination of the first metal oxide layer 121 and the second metal oxide layer 122 is different, for a total of nine types. Was manufactured. Specifically, the following nine types of combinations of the first metal oxide layer 121 and the second metal oxide layer 122 formed on the lower wiring 106 mainly containing Cu are provided.

_{TiO y1 / AlO x1, TiO y1} / NbO x2, TiO y1 / TaO x3,
_{ZrO y2 / AlO x1, ZrO y2} / NbO x2, ZrO y2 / TaO x3,
HfO _y3 / AlO _x1 , HfO _y3 / NbO _x2 , HfO _y3 / TaO _x3
The thickness of the first metal layer 161 for forming the first metal oxide layer 121 is 0.5 nm, and the thickness of the second metal layer 162 for forming the second metal oxide layer 122 is , 0.2 nm. After forming the second metal layer of the first metal layer and the thickness 0.2nm in thickness 0.5 nm, without exposure to the atmosphere, pressure 0.5 Pa, at room temperature, O ₂ in the O ₂ flow rate 10sccm To perform an oxidation treatment. By the oxidation treatment, the first metal layer becomes the first metal oxide layer 121 and the second metal layer becomes the second metal oxide layer 122. The solid electrolyte layer is formed using a 6 nm-thick SiOCH film.

The atomic radius of Cu is 128 pm and the radius of covalent bond is 132 ± 4 pm;
Al has an atomic radius of 143 pm and a covalent bond radius of 121 ± 4 pm;
Nb has an atomic radius of 146 pm and a covalent bond radius of 164 ± 6 pm;
The atomic radius of Ta is 146 pm, and the radius of covalent bond is 170 ± 8 pm;
The atomic radius of Ti is 147 pm, and the covalent bond radius is 160 ± 8 pm;
Zr has an atomic radius of 160 pm and a covalent bond radius of 175 ± 7 pm;
It is reported that the atomic radius of Hf is 159 pm and the covalent bond radius is 175 ± 10 pm.

  The thickness of the second metal layer of 0.2 nm is a value not exceeding twice the atomic radius of Al, Nb, and Ta. The thickness 0.5 nm of the first metal layer is a value not exceeding four times the atomic radius of Ti, Zr, and Hf.

  Further, in order to compare the characteristics with a variable resistance element manufactured in the first embodiment, which selects a combination of the first metal oxide layer 121 and the second metal oxide layer 122, the following variable resistance variable element is used. Got ready.

The resistance change element according to the comparative example employs a structure in which the buffer layer is formed of one type of metal oxide layer. Specifically, the metal oxide layer formed on the lower wiring 106 containing Cu as a main component is made of a metal oxide (TiO _y1 , ZrO _y2 , and HfO _y3 ) used for the first metal oxide layer 121 and a second metal oxide layer. Of the metal oxides (AlO _x1 , NbO _x2 , and TaO _x3 ) used for the two-metal oxide layer 122, the metal oxide layer 122 is formed of only one kind of metal oxide. The thickness of the metal layer for forming one type of metal oxide layer is selected to be 0.7 nm. After forming the metal layer having a thickness of 0.7 nm, the oxidation treatment is performed by irradiating O ₂ at a pressure of 0.5 Pa and room temperature at an O ₂ flow rate of 10 sccm without exposing to the atmosphere. By the oxidation treatment, the metal layer becomes a metal oxide layer. The solid electrolyte layer is formed using a 6 nm-thick SiOCH film.

  Next, the resistance change element of the first embodiment and the resistance change element as a comparative example were evaluated for an off-leak current at the time of setting and a dielectric breakdown voltage at the time of reset. Hereinafter, the evaluation results will be described.

  FIG. 11 is a table showing the results of measuring the off-leak current at the time of setting, specifically, the off-leak current at the time of applying a negative voltage of 1 V, for the variable resistance element of Embodiment 1 and the variable resistance element as a comparative example. It is. The unit of the numerical value shown in FIG. 11 is ampere (A).

  As shown in FIG. 11, in the variable resistance element according to the first embodiment, in any combination of the first metal oxide layer 121 and the second metal oxide layer 122, each is the same as the first metal oxide layer 121. A reduction in the off-leak current at the time of setting is recognized as compared with the variable resistance element as a comparative example, which employs a buffer layer composed of only a metal oxide of the type.

  FIG. 12 is a table showing the results of measuring the dielectric breakdown voltage at reset for the variable resistance element according to the first embodiment and the variable resistance element as a comparative example. The unit of the numerical value shown in FIG. 12 is volt (V).

  As shown in FIG. 12, with respect to the dielectric breakdown voltage at the time of reset, in the variable resistance element according to the first embodiment, in any combination of the first metal oxide layer 121 and the second metal oxide layer 122, It can be seen that the resistance change element is improved as compared with the resistance change element of the comparative example in which the buffer layer made of only the same kind of metal oxide as the first metal oxide layer 121 or the second metal oxide layer 122 is employed.

(Embodiment 2)
Also in the second embodiment, the configuration of the second embodiment, which employs a variable resistance layer including a buffer layer and a solid electrolyte layer, is applied. The variable resistance element 126 shown in FIG. 9J employs the buffer layer 4 composed of the first metal oxide layer 6 and the second metal oxide layer 7 shown in FIG. 7B. Therefore, the resistance change layer includes the first metal oxide layer 121, the second metal oxide layer 122, and the solid electrolyte layer 123. On the other hand, in the second embodiment, the resistance change element in which the buffer layer 4 is constituted by the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 shown in FIG. It was fabricated and the characteristics of the fabricated variable resistance element were evaluated.

In the second embodiment, the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 shown in FIG. 7C are based on the resistance change element 126 of the third embodiment as a basic structure. , And a total of seven types of variable resistance elements having different combinations were prepared. Specifically, the combinations of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 formed on the lower wiring mainly composed of Cu are the following seven types. It is. _{TiO y1 / AlO x1 / TiO y4} , TiO y1 / NbO x2 / TiO y4, TiO y1 / TaO x3 / TiO y4, ZrO y2 / AlO x1 / ZrO y5, ZrO y2 / NbO x2, ZrO y2 / TaO x3 / ZrO y5 , HfO _y3 / AlO _x1 / HfO _y6
y4, y5 and y6 are oxygen compositions of Ti, Zr and Hf oxides (TiO _y4 , ZrO _y5 and HfO _y6 ) constituting the third metal oxide layer 8, respectively.

  A third metal layer for forming the third metal oxide layer 8 was continuously deposited on the second metal layer for forming the second metal oxide layer 7. The thickness of the third metal layer for forming the third metal oxide layer 8 is selected to be 0.2 nm. The basic structure of the resistance change element according to the second embodiment is the same as that of the variable resistance element except that the buffer layer is composed of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8. And the variable resistance element 126 shown in FIG. 9J.

  Next, with respect to the variable resistance element of Embodiment 2, the off-leak current at the time of setting and the dielectric breakdown voltage at the time of reset were evaluated. Hereinafter, the evaluation results will be described.

  As compared with the resistance change element of the comparative example, which employs seven types of resistance change elements of the second embodiment and a buffer layer made of only the same type of metal oxide as the first metal oxide layer 121, respectively. It was confirmed that the off-leakage was reduced and the dielectric breakdown voltage was improved to the same degree as the evaluation result of the variable resistance element of the first embodiment.

Specifically, in the case of a resistance change element according to a comparative example, which is composed of only the same type of metal oxide (TiO _y1 ) as the first metal oxide layer 121 (TiO _y1 ), as shown in FIG. The off-leak current measured when applying a voltage of 1 V was 7 × 10 ⁻⁷ A. On the other hand, in the resistance change element according to the second embodiment, for example, the combination of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 constituting the buffer layer is TiO _y1 / In the case of AlO _x1 / TiO _y4 , the off-leak current measured when a negative voltage of 1 V was applied was reduced to 4 × 10 ⁻⁸ A.

Further, in the case of the resistance change element according to the comparative example, which is made of only the same type of metal oxide (TiO _y1 ) as the first metal oxide layer 121 (TiO _y1 ), as shown in FIG. The measured breakdown voltage is 3.5V. On the other hand, in the variable resistance element according to the second embodiment, for example, a combination of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 constituting the buffer layer Is TiO _y1 / AlO _x1 / TiO _y4 , the breakdown voltage measured when a positive voltage is applied has risen to 4.5V. This is because the insertion of the third metal oxide layer 8 in addition to the first metal oxide layer 6 and the second metal oxide layer 7 allows the second metal oxide layer 8 to be in contact with the lower part of the third metal oxide layer 8. It is considered that this is because the oxygen barrier property due to the passivation of the material layer 7 is controlled.

(Embodiment 3)
The third embodiment is based on the variable resistance element having the configuration shown in FIG. 9J and the method for manufacturing the same described in the fourth embodiment, and is based on a three-terminal variable resistance element in a multilayer wiring structure on a semiconductor substrate. Is provided.

  The configuration of the three-terminal variable resistance element according to the third embodiment will be described. In the third embodiment, a configuration different from the variable resistance element having the configuration shown in FIG. 9J and described in the fourth embodiment will be mainly described, and the configuration described in the fourth embodiment will be described. Detailed description of the same configuration as that of the variable resistance element having the configuration shown in FIG. 9J will be omitted.

  FIG. 10 is a partial cross-sectional view schematically showing a configuration in which the three-terminal variable resistance element according to the third embodiment is provided inside a multilayer wiring structure on a semiconductor substrate.

  As shown in FIG. 10, in a three-terminal variable resistance element 224 according to the third embodiment, a first lower wiring 206a and a second lower wiring 206b are provided as lower electrodes. Then, in one opening formed in the first barrier insulating film 107, the upper surfaces of the first lower wiring 206a and the second lower wiring 206b separated from each other with the first cap insulating film 104 therebetween are partially exposed. are doing. The exposed portion of the upper surface of each of the first lower wiring 206a and the second lower wiring 206b is in contact with the upper first metal oxide layer 121 through the opening together with the upper surface of the first cap insulating film 104. . The area of the copper surface of the first lower wiring 206a and the area of the copper surface of the second lower wiring 206b, which are exposed in the opening, are each less than half the area of the opening.

  When both the first lower wiring 206a and the second lower wiring 206b are made of, for example, Cu, the same structure as the lower wiring 106 having the structure shown in FIG. 9J can be adopted. The variable resistance element having the configuration shown in FIG. 9J and described in the fourth embodiment can be formed by the method described in the manufacturing process.

  In the three-terminal variable resistance element 224 according to the third embodiment, if the first lower wiring 206a is a first electrode and the second lower wiring 206b is a third electrode, the first electrode and the third electrode are provided on the same layer. The second electrode is provided on a layer different from the first and third electrodes.

  Next, a method of manufacturing the three-terminal variable resistance element 224 according to the third embodiment will be described. In the third embodiment, processing different from the manufacturing process of the resistance change element 126 having the configuration shown in FIG. 9J and described in the fourth embodiment will be mainly described. Detailed description of the same processing as the manufacturing process of the resistance change element 126 will be omitted.

In the third embodiment, in forming the opening in the first barrier insulating film 107 by dry etching, the surface of the first cap insulating film 104 sandwiched between the first lower wiring 206a and the second lower wiring 206b is dry-etched. As a result, the film is reduced. Therefore, after the opening is formed, the first metal layer used for forming the first metal oxide layer 121 is formed on the opening including the surfaces of the first lower wiring 206a and the second lower wiring 206b by DC sputtering. 161 and a second metal layer 162 used for forming the second metal oxide layer 122 were sequentially deposited in this order. In the third embodiment, 0.5 nm thick Zr is selected as the first metal layer 161, and 0.2 nm thick Al is selected as the second metal layer 162. Thereafter, the first metal layer 161 and the second metal layer 162 are irradiated with O ₂ gas at an O ₂ flow rate of 10 sccm, a pressure of 0.5 Pa, and an irradiation time of 60 seconds at room temperature without exposure to the air. By oxidation treatment, ZrO _{y2 as} the first metal oxide layer 121 and AlO _x1 as the second metal oxide layer 122 were formed. Subsequently, a heat treatment was performed at a substrate temperature of 400 ° C. or less under the conditions of N ₂ and O ₂ flow rates of 10/10 sccm, a pressure of 900 Pa, and a processing time of 30 seconds. By this heat treatment, the Zr metal component remaining unreacted between the first lower wiring 206a and the second lower wiring 206b and ZrO _{y2 as} the first metal oxide layer 121 is made of Cu It is removed by alloying and diffusion on the surfaces of the lower wiring 206a and the second lower wiring 206b.

  Next, a solid electrolyte layer 123 was deposited on the second metal oxide layer 122. As for the steps after the solid electrolyte layer 123 is deposited, by using the same forming method as the variable resistance element 126 having the configuration shown in FIG. 9J, as shown in FIG. 224 can be formed.

  The three-terminal variable resistance element 224 shown in FIG. 10 employs a configuration in which the variable resistance layer is formed integrally. Further, the second electrode also adopts a configuration integrally formed.

  Similarly to the variable resistance element of the first embodiment, in the three-terminal variable resistance element 224 of the third embodiment formed by the above-described manufacturing process, only the metal oxide of the same type as the first metal oxide layer 121 is used. , A reduction in off-leakage and an improvement in dielectric breakdown voltage were confirmed as compared with a three-terminal variable resistance element as a comparative example employing a buffer layer composed of

More specifically, a three-terminal variable resistance element according to a comparative example adopting a 0.7 nm-thickness buffer layer made of only the same type of metal oxide (ZrO _y2 ) as the first metal oxide layer 121. In this case, the off-leak current measured when a negative voltage of 1 V is applied is 5 × 10 ⁻⁷ A. On the other hand, in the case of the three-terminal variable resistance element 224 of the third embodiment in which ZrO _y2 is used as the first metal oxide layer 121 and AlO _x1 is used as the second metal oxide layer 122, the negative voltage is The off-leak current measured when 1 V was applied was 8 × 10 ⁻⁸ A, and it was confirmed that the off-leak current was sufficiently reduced.

In the case of a three-terminal variable resistance element as a comparative example employing a buffer layer composed of only ZrO _y2 , the breakdown voltage measured when a positive voltage was applied was 3.6 V. On the other hand, in the case of the three-terminal variable resistance element 224 according to the third embodiment, the dielectric breakdown voltage measured when a positive voltage was applied increased to 4.3V. In the third embodiment, as an example, the three-terminal variable resistance element 224 using ZrO _y2 as the first metal oxide layer 121 and AlO _x1 as the second metal oxide layer 122 has been described. The combination of the first metal oxide layer 121 and the second metal oxide layer 122 constituting the buffer layer is not limited to this combination of material configurations (ZrO _y2 / AlO _x1 ), but is exemplified in the first embodiment. Other eight types of combinations may be used.

  From the above results, by applying the variable resistance element of the present invention and the method of manufacturing the same to not only the two-terminal type variable resistance element but also the three-terminal type variable resistance element, the off-leak current at the time of applying a negative voltage is reduced, In addition, it was found that the dielectric breakdown voltage when a positive voltage was applied (during reset) was improved.

  The present invention has been described based on the embodiments and the embodiments. These embodiments and embodiments are only for describing the present invention with specific examples, and are not meant to limit the technical scope of the present invention. It will be understood by those skilled in the art that various modifications and improvements can be made based on the above description, and these are also included in the technical scope of the present invention.

  In the above embodiments and embodiments, as a background of the present invention, a semiconductor device having a CMOS circuit to which the present invention is applied will be described in detail, and a variable resistance element mounted in a multilayer wiring structure on a semiconductor substrate will be formed. Examples have been described. However, the invention is not limited to the illustrated embodiments and implementations.

  The present invention relates to a semiconductor product having a memory circuit such as a DRAM, an SRAM (Static RAM), a flash memory, an FRAM (Ferro-Electric RAM), a capacitor, a bipolar transistor, and a semiconductor product having a logic circuit such as a microprocessor. Alternatively, the present invention can be applied to a metal wiring forming step of a board or a package on which these are simultaneously mounted. In addition, the present invention can be applied to a wiring forming step of connecting a semiconductor device to an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, a MEMS (Micro-Electro-Mechanical Systems), or the like.

  The solid electrolyte switching element according to the present invention, which is formed in a copper wiring layer and has a plurality of variable resistance elements connected in parallel, is, for example, a programmable element used in a configuration of an FPGA (Field Programmable Gate Array). It is used as

  The solid electrolyte switching element type semiconductor device according to the present invention uses a non-volatile memory or a non-volatile switch by utilizing its "programming" operation, in particular, the effect of suppressing the variation of the set voltage during the "set" operation. , A semiconductor product having a memory circuit, a logic circuit such as a microprocessor, or the like.

  The present invention has been described above using the above-described embodiment as a typical example. However, the invention is not limited to the embodiments described above. That is, the present invention can apply various aspects that can be understood by those skilled in the art within the scope of the present invention.

  This application claims priority based on Japanese Patent Application No. 2017-714485 filed on Mar. 31, 2017, the disclosure of which is incorporated herein in its entirety.

REFERENCE SIGNS LIST 1 first electrode 2 second electrode 3 variable resistance layer 4 buffer layer 5 solid electrolyte layer 101 semiconductor substrate 102 first interlayer insulating film 103 second interlayer insulating film 104 first cap insulating film 105 first barrier metal 106 lower wiring 107 1 barrier insulating film 108 first hard mask film 120 buffer layer 121 first metal oxide layer 122 second metal oxide layer 123 solid electrolyte layer 124 first upper electrode 125 second upper electrode 128 second hard mask film 129 third Hard mask film 130 Protective insulating film 140 First via interlayer insulating film 141 Third interlayer insulating film 142 Second cap insulating film 143 Second barrier metal 144 Via plug 145 Upper wiring 146 Second barrier insulating film 147 Via hole 148 Wiring for upper wiring Groove 126, 151, 151a, 151b Resistance change element 150, 150a, 150b Two-terminal semiconductor device 153, 153a, 153b First terminal 154, 154a, 154b Second terminal 157 Control terminal 159 Solid electrolyte switch element 161 First metal layer 162 Second metal layer 206a First lower Wiring 206b Second lower wiring 224 Three-terminal resistance change element

Claims (10)

A semiconductor device including at least two or more variable resistance elements, a first terminal (first wiring), and a second terminal (second wiring),
The variable resistance elements are respectively:
A first electrode, a second electrode, and a variable resistance layer sandwiched between the first electrode and the second electrode;
A function of reversibly changing a resistance value based on an electric signal applied between the first electrode and the second electrode;
Each first electrode of the variable resistance element is electrically connected to a first terminal, and each second electrode is electrically connected to a second terminal, and
Each of the variable resistance layers is separated from each other between at least two or more variable resistance elements,
A semiconductor device, wherein each of the second electrodes is separated from each other between the variable resistance elements, and is electrically connected to each other only through the second terminal. A semiconductor device comprising a pair of the semiconductor device according to claim 1 as a component,
The semiconductor device pair is
A semiconductor device, wherein the second terminals constituting each semiconductor device are electrically connected in series. The first electrode of the resistance change element is made of a material containing a metal atom serving as a supply source of metal ions,
The second electrode is made of a material made of a metal atom that is less ionizable than the metal atom, which is included in a material forming the first electrode,
The resistance change layer includes a buffer layer and a solid electrolyte layer through which the metal ions can conduct,
The buffer layer is in contact with the first electrode, the solid electrolyte layer is in contact with the second electrode,
The variable resistance element,
When a voltage is applied between the first electrode and the second electrode, the metal atoms included in the first electrode are ionized,
The metal ion supplied from the first electrode is injected into the solid electrolyte layer through the buffer layer, whereby the resistance is reversibly changed, and the solid electrolyte switch element is characterized in that: The semiconductor device according to claim 2. The metal ion is a copper ion,
The first electrode of the variable resistance element is made of a material containing copper,
The second electrode is made of a material containing Ru,
The semiconductor device according to claim 3, wherein the buffer layer contains at least one metal element selected from the group consisting of Al, Hf, Ta, Ti, and Zr.   The semiconductor device according to claim 1, wherein the variable resistance element is provided in a multilayer copper wiring layer on a semiconductor substrate. The variable resistance element is provided on a copper wiring,
The first electrode constituting the variable resistance element also serves as a part of the copper wiring,
A part of the insulating barrier film provided on the first electrode has at least one or more openings,
The structure in which the surface of at least one or more of the first electrodes partially exposed at the bottom of the opening is in contact with the buffer layer through the opening. 6. The semiconductor device according to claim 5. For each variable resistance element constituting the semiconductor device,
7. The semiconductor device according to claim 6, wherein the shape of the copper wiring serving also as the first electrode partially exposed at the bottom of the opening is the same. For each variable resistance element constituting the semiconductor device,
The shape of the copper wiring serving also as the first electrode partially exposed at the bottom of the opening is:
The semiconductor device according to claim 6, wherein the semiconductor device is oriented in the same direction in the plane of the semiconductor substrate, or rotated 180 ° to face each other. For each variable resistance element constituting the semiconductor device,
The shape of the copper wiring serving also as the first electrode partially exposed at the bottom of the opening is:
9. The semiconductor device according to claim 8, wherein a tip of the copper wiring has a shape protruding from one end of a bottom of the opening along the direction of the orientation. A method of manufacturing a semiconductor device having a plurality of variable resistance elements provided in a multilayer copper wiring layer on a semiconductor substrate,
Forming an insulating barrier film on a copper wiring which also serves as a first electrode electrically connected to the first terminal;
Forming an opening in the insulating barrier film to expose a copper wiring surface also serving as the first electrode;
On the entire surface including the opening, a buffer layer and a solid electrolyte layer are sequentially formed,
Forming a second electrode connected to the second terminal on the solid electrolyte layer;
A method for manufacturing a semiconductor device, wherein the semiconductor device is the semiconductor device according to claim 1.

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