JPWO2017122416A1 - Semiconductor device - Google Patents

Abstract

In a semiconductor device provided with an electromagnetic shield, electromagnetic noise is reduced while suppressing a decrease in inductance. The semiconductor device includes a substrate, an inductor, and a shield with an upper layer slit. In this semiconductor device, an inductor is disposed on the substrate. In this semiconductor device, the shield with the upper layer slit is disposed above the inductor with a predetermined direction perpendicular to the substrate plane of the substrate as an upper direction, and a slit is formed along a direction parallel to the substrate plane.

Description

  The present technology relates to a semiconductor device. Specifically, the present invention relates to a semiconductor device provided with an electromagnetic shield.

  Conventionally, in a semiconductor device, in order to reduce electromagnetic noise due to electrostatic induction or electromagnetic induction, a conductor or a magnetic body is often disposed as an electromagnetic shield around a circuit to be protected. For example, a semiconductor device has been proposed in which a linear conductor is wired around an inductor as an electromagnetic shield to reduce electromagnetic noise generated in the inductor (see, for example, Patent Document 1).

JP 2009-188343 A

  However, in the above-described semiconductor device, when a circuit is distributed and arranged in a plurality of stacked semiconductor chips, electromagnetic noise generated in the inductor may not be sufficiently reduced. This is because when wiring is used as an electromagnetic shield, electromagnetic noise due to a magnetic field from a direction parallel to the substrate can be reduced, but electromagnetic noise due to a magnetic field from a direction perpendicular to the substrate cannot be reduced. is there. On the other hand, when the upper and lower surfaces of the inductor are covered with a plate-shaped electromagnetic shield, the magnetic noise in the direction perpendicular to the substrate can be blocked to sufficiently reduce the electromagnetic noise, but the vortex generated by the electromagnetic shield has been reduced. There is a possibility that the inductance of the inductor is reduced by the current. This is because an eddy current generates a magnetic field in a direction opposite to the direction of the magnetic field generated by the inductor, and a back electromotive force is generated in the inductor by the magnetic field. When the inductance decreases, the Q value of the inductor deteriorates, leading to a decrease in signal quality. For example, when an inductor is used in the LC resonance circuit, the oscillation frequency is changed. For this reason, it is desirable that the amount of decrease in inductance is small. As described above, it is difficult for the above-described linear or plate-shaped electromagnetic shield to reduce electromagnetic noise while suppressing a decrease in inductance.

  The present technology has been created in view of such a situation, and an object of the present technology is to reduce electromagnetic noise while suppressing a decrease in inductance in a semiconductor device provided with an electromagnetic shield.

  The present technology has been made to solve the above-described problems, and a first side of the present technology is that the inductor is disposed on the substrate on which the inductor is disposed and a predetermined direction perpendicular to the substrate plane of the substrate is the upward direction. And a shield with an upper layer slit, which is an electromagnetic shield in which a slit is formed along a direction parallel to the substrate plane. Thereby, the shield with the upper layer slit has an effect of reducing electromagnetic noise.

  The first side surface may further include a circuit arrangement board on which a circuit is arranged, and the circuit arrangement board may be laminated on the board. This brings about the effect | action that electromagnetic noise reduces in the semiconductor device with which the circuit arrangement board | substrate was laminated | stacked.

  In the first aspect, the inductor includes a first wire wound clockwise from a predetermined start point to a predetermined connection point about a first central axis perpendicular to the substrate plane, and the substrate. A second wiring wound in a counterclockwise direction from the predetermined connection point to a predetermined end point with a second central axis different from the first central axis as an axis perpendicular to the plane Also good. This brings about the effect | action that the magnetic field of a reverse direction arises in each of the 1st and 2nd wiring.

  In the first aspect, the slit may be formed along a direction parallel to a straight line connecting the first central axis and the second central axis. Thereby, the effect | action that generation | occurrence | production of the eddy current in an insertion shield is suppressed is brought about.

  In the first aspect, the inductor is wound along a spiral path that turns a plurality of times from a predetermined start point to a predetermined connection point about a predetermined central axis perpendicular to the substrate plane. And a second wiring wound along a spiral path that turns a plurality of times from the predetermined connection point to a predetermined end point about the predetermined central axis. Each time the first wiring turns from the predetermined start point to the predetermined connection point, the turning radius decreases, and the second wiring extends from the predetermined connection point to the predetermined end point. The turning radius may increase each time the vehicle turns. This brings about the effect | action of reducing the electromagnetic noise which arises in the inductor which outputs a differential signal.

  In the first aspect, the inductor may include a wiring wound along a spiral path. This brings about the effect | action of reducing the electromagnetic noise which arises in a spiral inductor.

  Further, in the first aspect, an outer peripheral shield that is an electromagnetic shield surrounding the outer periphery of the inductor may be further provided. This brings about the effect | action of reducing the electromagnetic noise by the magnetic field produced in the circuit of the outer periphery of an inductor.

  The first side surface may further include a lower layer shield that is an electromagnetic shield disposed below the inductor. This brings about the effect | action of reducing the electromagnetic noise by the magnetic field produced in the circuit under an inductor.

  The first side surface may further include a shield with a lower layer slit disposed below the inductor and having a slit formed in a direction parallel to the substrate plane. This brings about the effect | action of reducing the electromagnetic noise by the magnetic field produced in the circuit under an inductor.

  In the first aspect, a fixed potential may be applied to the shield with the upper layer slit. This brings about the effect | action of reducing the electromagnetic noise by electrostatic induction.

  The first aspect may further include a capacitor connected to the inductor, and the inductor and the capacitor may resonate. This brings about the effect | action of reducing electromagnetic noise in a resonance circuit.

Further, according to the first aspect, the phase comparator that compares the phases of the input signal and the feedback signal and outputs a detection signal indicating the phase difference, and the voltage signal of the voltage corresponding to the phase difference indicated by the detection signal And a frequency divider that divides the oscillation signal generated by the resonance circuit including the inductor and the capacitor and feeds back to the phase difference detector as the feedback signal. May be a variable capacitor whose capacitance value changes according to the voltage signal. This brings about the effect that the cycle of the input signal is multiplied.

  In the first aspect, the input signal may be a clock signal. As a result, the clock signal is multiplied.

  According to the present technology, in a semiconductor device provided with an electromagnetic shield, an excellent effect that electromagnetic noise can be reduced while suppressing a decrease in inductance can be achieved. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram showing an example of 1 composition of a semiconductor device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a phase locked loop in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a voltage controlled oscillator and an electromagnetic shield in a 1st embodiment of this art. 1 is an example of a perspective view of a semiconductor device according to a first embodiment of the present technology. 1 is an example of a plan view of an inductor according to a first embodiment of the present technology. It is an example of the top view of the upper layer shield in 1st Embodiment of this technique. It is a figure showing an example of the direction of the current which flows into the inductor in a 1st embodiment of this art. It is a figure showing an example of a direction of an induction current in an upper shield in a 1st embodiment of this art. It is a figure for demonstrating the measuring method of the insulation level in 1st Embodiment of this technique. It is a graph which shows the insulation level for every frequency in a 1st embodiment of this art. It is a graph which shows the inductance for every frequency in a 1st embodiment of this art. It is a graph which shows Q value for every frequency in a 1st embodiment of this art. It is an example of a top view of an inductor in a 2nd embodiment of this art. It is an example of the top view of the inductor in the 3rd embodiment of this art. It is a circuit diagram showing an example of 1 composition of a voltage controlled oscillator and an electromagnetic shield in a 4th embodiment of this art. It is an example of the perspective view of the inductor and electromagnetic shield in 4th Embodiment of this technique. It is an example of sectional drawing of an inductor and an electromagnetic shield in a 4th embodiment of this art.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (example in which a shield with a slit is inserted between an inductor and a circuit)
2. Second Embodiment (Example in which a shield with a slit is inserted between an inductor for generating a differential signal and a circuit)
3. Third Embodiment (Example in which a shield with a slit is inserted between a spiral inductor and a circuit)
4). Fourth Embodiment (Example in which a shield with a slit is inserted between an inductor and a circuit, and a lower shield and an outer shield are provided)

<1. First Embodiment>
[Configuration example of semiconductor device]
FIG. 1 is a block diagram illustrating a configuration example of the semiconductor device 100 according to the embodiment of the present technology. As this semiconductor device 100, for example, a device equipped with an image sensor, an LSI (Large Scale Integration), or the like is assumed. The semiconductor device 100 is provided with a plurality of stacked semiconductor chips such as the upper chip 110 and the lower chip 150. A logic circuit 111 is arranged on the upper chip 110. In the lower chip 150, a logic circuit 151 and a phase synchronization circuit 200 are arranged.

  Although two semiconductor chips are stacked, the number of stacked semiconductor chips is not limited to two, and may be three or more.

  The logic circuit 111 executes predetermined processing. The logic circuit 111 transmits / receives data to / from the lower logic circuit 151 via the signal line 119. As the logic circuit 111, for example, a pixel circuit or a vertical drive circuit that drives the pixel circuit is assumed.

Logic circuit 151, in synchronization with the clock signal _{CLK out} from the phase synchronization circuit 200, and executes a predetermined process. As the logic circuit 151, for example, an AD (Analog to Digital) converter or a horizontal driving circuit for driving the AD converter is assumed.

The phase synchronization circuit 200 receives a clock signal CLK _in having a predetermined period generated by an external crystal oscillator or the like. The phase synchronization circuit 200 multiplies the clock signal CLK _in by a predetermined multiplication ratio and outputs it as a clock signal CLK _out to the logic circuit 151 via the signal line 209.

[Configuration example of phase synchronization circuit]
FIG. 2 is a block diagram illustrating a configuration example of the phase synchronization circuit 200 according to the first embodiment. The phase synchronization circuit 200 includes a phase comparator 210, a charge pump 220, a frequency divider 230, and a voltage controlled oscillator 240.

The phase comparator 210 compares the phase of the clock signal CLK _in from the crystal oscillator 152 and the clock signal CLK _fb from the frequency divider 230. The phase comparator 210 generates detection signals UP and DN indicating the phase difference between the signals based on the comparison result, and supplies the detection signals UP and DN to the charge pump 220. For example, the difference between the pulse widths of the detection signals UP and DN indicates the phase difference between the clock signal CLK _in and the clock signal CLK _fb .

  The charge pump 220 generates a control signal Vc having a voltage corresponding to the phase difference indicated by the detection signals UP and DN. The charge pump 220 supplies a control signal Vc to the voltage controlled oscillator 240.

The voltage controlled oscillator 240 generates a clock signal CLK _out having a frequency corresponding to the voltage of the control signal Vc, and supplies the clock signal CLK _out to the frequency divider 230 and the logic circuit 151. The clock signal CLK _out is, for example, a single end signal.

Divider 230 is for dividing the clock signal _{CLK out} from the voltage controlled oscillator 240 at a predetermined frequency division ratio. The frequency divider 230 _feeds back the frequency- _divided signal to the phase comparator 210 as the clock signal CLK _fb . By thus feeding back a divided signal of the clock signal CLK _out from the voltage controlled oscillator 240, phase synchronization circuit 200 can generate a multiplied signal of the clock signal CLK _in.

[Configuration example of voltage controlled oscillator]
FIG. 3 is a circuit diagram showing a configuration example of the voltage controlled oscillator 240 and the electromagnetic shield in the first embodiment. The voltage controlled oscillator 240 includes an amplifier circuit 241, an inductor 250, and a variable capacitor 242. The variable capacitor 242 and the inductor 250 are connected to the amplifier circuit 241 in parallel. Further, the upper shield 260 is laminated above the inductor 250 with the direction from the lower chip 150 toward the upper chip 110 as the upward direction.

  The variable capacitor 242 is a capacitor whose electric capacity changes according to the voltage of the control signal Vc from the charge pump 220. For example, a varicap diode is used as the variable capacitor 242. The variable capacitor 242 is an example of a capacitor described in the claims.

  The inductor 250 resonates with the variable capacitor 242 to generate a clock signal. The inductor 250 generates a magnetic field in the upward direction or the downward direction.

Amplifier circuit 241 is for amplifying the signal generated by the LC resonance circuit composed of the variable capacitance 242 and the inductor 250, is supplied to the frequency divider 230 and the logic circuit 151 as the clock signal _{CLK out.}

  The upper layer shield 260 is an electromagnetic shield in which slits are formed along directions parallel to the respective substrate planes of the upper chip 110 and the lower chip 150. The upper shield 260 is applied with a predetermined fixed potential (for example, ground potential). The upper shield 260 shields electromagnetic noise caused by the magnetic field generated in the upper logic circuit 111, and protects the lower inductor 250 from the electromagnetic noise.

  Although the potential of the upper shield 260 is a fixed potential, it may be a floating potential. In this case, the upper shield 260 functions as a magnetic field shield that shields only electromagnetic noise due to electromagnetic induction. When it is necessary to shield electromagnetic noise due to electrostatic induction, a fixed potential is applied to the upper shield 260.

  Further, although the upper shield 260 is disposed above the inductor 250 in the voltage controlled oscillator 240, it is disposed above the inductor provided in a circuit (buffer circuit, clock distribution circuit, etc.) other than the voltage controlled oscillator 240. Also good.

  FIG. 4 is an example of a perspective view of the semiconductor device according to the first embodiment. A in the figure is an example of a perspective view of the upper chip 110 and the lower chip 150. B in the figure is an example of an enlarged perspective view of the upper shield 260, and c in the figure is an example of an enlarged perspective view of the inductor 250.

  As illustrated in a in FIG. 4, the inductor 250 is disposed on the lower chip 150, and the upper layer shield 260 is laminated thereon. In other words, the upper shield 260 is inserted between the inductor 250 and the upper chip 110. Then, the logic circuit 111 is disposed on the upper chip 110 above the upper shield 260. In this logic circuit 111, it is assumed that an inductor having the same shape as the inductor 250 is not provided above the inductor 250.

  The upper chip 110 is an example of a circuit arrangement board described in the claims, and the lower chip 150 is an example of an inductor arrangement board described in the claims. The upper layer shield 260 is an example of a shield with an upper layer slit described in the claims.

  Further, although the upper layer shield 260 is inserted between the inductor 250 and the upper chip 110, the configuration is not limited to this configuration as long as the upper layer shield 260 is disposed between the inductor 250 and other circuits. . For example, the upper layer shield 260 may be provided on the upper chip 110, and the logic circuit 111 may be stacked thereon.

  Further, as illustrated in FIG. 4 b, the upper shield 260 is formed with a predetermined number of slits along a direction parallel to the substrate plane of the upper chip 110 and the lower chip 150.

  Further, as illustrated in c in FIG. 4, the inductor 250 includes a connected wiring 251 and a wiring 252. These wirings 251 and 252 are wound in a circle around a central axis perpendicular to the substrate plane. These wirings 251 and 252 are stacked in a plurality of layers. Note that these wirings may be a single layer instead of a plurality of layers.

  The centers of the wiring 251 and the wiring 252 are not the same, and are arranged at a certain distance. A direction parallel to a straight line connecting these centers is hereinafter referred to as an X direction. A direction parallel to the substrate plane and perpendicular to the X direction is hereinafter referred to as a Y direction. A direction perpendicular to the substrate plane is hereinafter referred to as a Z direction. The slit of the upper shield 260 described above is formed along the X direction.

[Inductor configuration example]
FIG. 5 is an example of a plan view of the inductor 250 according to the first embodiment. The inductor 250 includes a wiring 251 and a wiring 252 connected to each other. Here, one end of the wiring 251 that is not connected to the wiring 252 is set as a start point 501 and the other end is set as a connection point 502. One end of the wiring 252 that is not connected to the wiring 251 is defined as an end point 503.

  The wiring 251 is wound clockwise from the start point 501 to the connection point 502 around a central axis parallel to the Z direction. On the other hand, the wiring 252 is wound counterclockwise from the connection point 502 to the end point 503 around the central axis parallel to the Z direction. For example, the number of turns of the wirings 251 and 252 is two. The number of windings is not limited to two.

  The centers of the wiring 251 and the wiring 252 are not the same, and these centers are arranged on a straight line parallel to the X direction. In such an 8-shaped inductor 250, when a current is passed from one of the start point 501 and the end point 503 to the other, a magnetic field in the opposite direction is generated between the wiring 251 and the wiring 252. For example, when an upward magnetic field is generated in the wiring 251, a downward magnetic field is generated in the wiring 252.

[Configuration example of upper shield]
FIG. 6 is an example of a plan view of the upper shield 260 in the first embodiment. A predetermined number of slits are formed in the upper shield 260 along the X direction. Further, a predetermined fixed potential (ground potential or the like) is applied to the upper layer shield 260.

  FIG. 7 is a diagram illustrating an example of the direction of the current flowing through the inductor 250 according to the first embodiment. When a current flows from the start point 501 to the end point 503, a current flows clockwise in the wiring 251 and a current flows counterclockwise in the wiring 252.

  FIG. 8 is a diagram illustrating an example of the direction of the induced current in the upper shield 260 according to the first embodiment. In the figure, a thick dotted line indicates a current flowing through the wiring 251, and a thin dotted line indicates an eddy current induced in the upper shield 260 by a magnetic field generated in the wiring 251. A thick solid line indicates a path of current flowing through the wiring 252, and a thin solid line indicates eddy current induced in the upper shield 260 by a magnetic field generated in the wiring 252.

  A current flows clockwise in the wiring 251, and a downward magnetic field is generated by the current. This magnetic field causes counterclockwise eddy current (dotted line) to flow through the upper shield 260 in accordance with the law of electromagnetic induction. On the other hand, in the wiring 252, a current flows counterclockwise, and an upward magnetic field is generated by the current. This magnetic field causes a clockwise eddy current (solid line) to flow through the upper shield 260 in accordance with the law of electromagnetic induction.

As described above, the slit in the upper shield 260 is formed along the X direction. In the inductor 250, the wirings 251 and 252 are arranged along the X direction. Therefore, with the wiring 251 side as the left side and the wiring 252 side as the right side, the eddy current induced on the right side of the upper shield 260 flows to the left along the slit, and the eddy current induced on the left side flows to the right along the slit. Come on. These eddy currents cancel each other because their directions are opposite to each other. For this reason, almost no eddy current is generated in the entire upper shield 260, and there is no possibility that a counter electromotive force is generated in the inductor 250 by the magnetic field generated by the eddy current. Therefore, a decrease in the inductance of inductor 250 due to the counter electromotive force can be suppressed. Moreover, the fall of Q value of the inductor 250 can be suppressed by suppressing the fall of an inductance. Here, the Q value is represented by the following equation, for example.
Q = 2πfL / R
In the above equation, L represents the inductance of the inductor 250, and the unit is, for example, Henry (H). f indicates an oscillation frequency when the inductor 250 resonates with the variable capacitor 242 or the like, and the unit is, for example, hertz (Hz). R represents the internal resistance of the inductance 250, and its unit is, for example, ohm (Ω).

  An eddy current is also generated in the upper shield 260 by a magnetic field generated in the logic circuit 111 above the inductor 250. However, as described above, no element having the same shape as the inductor 250 is provided above the inductor 250. . For this reason, the eddy current generated by the magnetic field from the logic circuit 111 is not canceled, and the magnetic field from the logic circuit 111 is canceled by the reverse magnetic field generated by the eddy current. Thereby, electromagnetic noise from above is shielded. Therefore, it is possible to protect the inductor 250 from the electromagnetic noise by reducing the electromagnetic noise caused by the magnetic field generated in the circuit other than the inductor 250 while suppressing the decrease in the inductance of the inductor 250.

  Here, it is assumed that the upper shield 260 of the comparative example in which slits are formed along the Y direction, not the X direction. In this comparative example, an eddy current flows in the Y direction along the slit. However, since the wirings 251 and 252 are arranged in the X direction, the eddy current induced on the right side of the upper shield 260 does not flow to the left side, and the eddy current induced on the left side does not flow to the right side. Therefore, the eddy current is not canceled except in the vicinity of the center, and the inductance of the inductor 250 may be reduced by the magnetic field generated by the eddy current.

  In addition, when the slit itself is not provided in the upper layer shield 260 regardless of the direction, the direction of the eddy current is not limited by the slit, so the total current value of the eddy current is more than that when the slit is provided. Also grows. For this reason, compared with the case where a slit is provided, the fall amount of an inductance will become large.

FIG. 9 is a diagram for explaining a method of measuring an insulation level in the first embodiment. An inductor 302 having a shape (such as a spiral shape) different from that of the inductor 250 is disposed above the upper layer shield 260, and the AC power supply 301 is connected to the inductor 302. The supply current of the AC power supply 301 when the frequency of the AC signal from the AC power supply 301 is f is measured as i _in (f). The unit of the frequency f is, for example, hertz (Hz). Further, both ends of the inductance 250 are grounded. The current of the positive phase signal induced in the inductor 250 by the magnetic field generated by the inductor 302 is measured as i _p (f), and the current of the negative phase signal is measured as i _n (f). The unit of these currents is, for example, ampere (A). Based on these measured values, the insulation level LV _ISO is calculated by the following equation.

The insulation level LV _ISO indicates a high effect of shielding electromagnetic noise generated in a circuit above the inductor 250 (such as the inductor 302). It means that the smaller the value of the insulation level LV _ISO, the higher the electromagnetic noise shielding effect. The unit of the insulation level LV _ISO is decibel (dB).

FIG. 10 is a graph showing the insulation level for each frequency in the first embodiment. In the figure, the vertical axis represents the insulation level LV _ISO (dB), and the horizontal axis represents the frequency f (Hz) of the AC signal. In the figure, the dotted curve indicates the characteristic of the insulation level LV _ISO when the upper shield 260 is not provided, and the solid curve indicates the characteristic of the insulation level LV _ISO when the upper shield 260 is provided.

As illustrated in FIG. 10, by providing the upper shield 260, the insulation level LV _ISO can be made lower than when the upper shield 260 is not provided. In other words, the shielding effect of electromagnetic noise from circuits other than the inductor 250 can be improved.

  FIG. 11 is a graph showing the inductance for each frequency in the first embodiment. In the drawing, the vertical axis represents the inductance L (H) of the inductor 250, and the horizontal axis represents the frequency f (Hz) of the AC signal. In the figure, the dotted curve indicates the characteristic of the inductance L when the upper layer shield 260 is not provided, and the solid line curve indicates the characteristic of the inductance L when the upper layer shield 260 is provided.

  As illustrated in FIG. 11, even if the upper shield 260 is provided, the value of the inductance L hardly decreases (deteriorates) as compared to the case where the upper shield 260 is not provided.

  FIG. 12 is a graph showing the Q value for each frequency according to the first embodiment. In the drawing, the vertical axis indicates the Q value of the inductor 250, and the horizontal axis indicates the frequency f (Hz) of the AC signal. In the figure, a dotted curve indicates the Q value characteristic when the upper shield 260 is not provided, and a solid curve indicates the Q value characteristic when the upper shield 260 is provided.

  As illustrated in FIG. 12, even when the upper shield 260 is provided, the Q value hardly decreases (deteriorates) compared to the case where the upper shield 260 is not provided.

  As illustrated in FIGS. 10 to 12, by providing the upper shield 260, it is possible to reduce electromagnetic noise while suppressing deterioration of the inductance L and Q value.

  As described above, according to the first embodiment of the present technology, since the upper shield 260 having the slit is inserted between the inductor 250 and the logic circuit 111, electromagnetic noise due to the magnetic field generated in the logic circuit 111 is reduced. can do. In addition, since the eddy current is reduced by the slit of the upper shield 260, a decrease in the inductance of the inductor 250 can be suppressed.

<2. Second Embodiment>
In the first embodiment described above, the upper layer shield 260 is arranged above the 8-shaped inductor 250 to protect the inductor 250 from electromagnetic noise. However, an inductor having a shape other than the 8-shaped inductor 250 is used. It can also be protected. For example, when a clock signal is a differential signal, an inductor having a special shape in which two spiral wires having the same center are connected is used. The semiconductor device 100 of the second embodiment is different from the first embodiment in that the inductor 265 composed of two spiral wires having the same center is the protection target.

  FIG. 13 is an example of a plan view of the inductor 265 according to the second embodiment. An upper shield 260 is disposed above the inductor 265. In the second embodiment, the slit direction of the upper shield 260 may be a direction parallel to the substrate plane, and is not limited to the X direction.

  The inductor 265 includes a wiring 266 and a wiring 267 that are connected to each other. Here, one end of the wiring 266 that is not connected to the wiring 267 is set as a start point 511 and the other end is set as a connection point 512. One end of the wiring 267 that is not connected to the wiring 266 is set as an end point 513.

  The wiring 266 is wound along a spiral path that turns clockwise a plurality of times from the start point 511 to the connection point 512 around the central axis parallel to the Z-axis direction. On the other hand, the wiring 267 is wound along a spiral path that turns clockwise a plurality of times from the connection point 512 to the end point 513 around the same central axis as the wiring 266. Further, the wiring 266 has a smaller turning radius each time it turns from the start point 511 to the connection point 512, and the wiring 267 has a larger turning radius every time it turns from the connection point 512 to the end point 513. A normal phase signal is input / output at the start point 511, and a negative phase signal is input / output at the end point 513. Thus, since the wiring 266 and the wiring 267 have a contrasting shape, the duty ratios of the normal-phase signal and the negative-phase signal can be made approximately the same.

  When the inductor 265 having the above-described shape is protected by the upper layer shield 260, the direction of the current flowing through the wiring 266 and the wiring 267 is the same as that of the 8-shaped inductor 250 of the first embodiment. The eddy current generated at 260 is not canceled out. For this reason, although the effect which suppresses the fall of an inductance is higher than the plate-shaped electromagnetic shield without a slit, it becomes low compared with 1st Embodiment. However, instead, the magnetic field generated in the inductor 265 due to the eddy current can be canceled, so that electromagnetic noise generated in the upper logic circuit 111 can be reduced. That is, the upper layer shield 260 can protect the logic circuit 111 from electromagnetic noise in addition to the inductor 265.

  As described above, according to the second embodiment of the present technology, the upper layer shield 260 is inserted between the inductor 265 including the two spiral wires having the same center and the logic circuit 111. Thus, the logic circuit 111 can also be protected from electromagnetic noise. Further, by using the inductor 265 composed of two spiral wires, when the differential signal is output, the respective duty ratios of the positive phase signal and the negative phase signal in the differential signal are made equal. Can do.

<3. Third Embodiment>
In the first embodiment described above, the upper layer shield 260 is arranged above the 8-shaped inductor 250 to protect the inductor 250 from electromagnetic noise. However, an inductor having a shape other than the 8-shaped inductor 250 is used. It can also be protected. For example, when the clock signal is a single-ended signal, a spiral inductor can be used instead of the figure eight shape. The semiconductor device 100 according to the third embodiment is different from the first embodiment in that a spiral inductor 270 is to be protected.

  FIG. 14 is an example of a plan view of the inductor 270 according to the third embodiment. An upper shield 260 is disposed above the inductor 270. In the third embodiment, the slit direction of the upper shield 260 may be a direction parallel to the substrate plane, and is not limited to the X direction.

  The inductor 270 is composed of wiring wound in a spiral shape from a start point 521 to an end point 522 around a central axis parallel to the Z direction.

  When the inductor 270 having the above-described shape is protected by the upper shield 260, the effect of suppressing the decrease in inductance is higher than that of the plate-shaped electromagnetic shield without slits, but is lower than that of the first embodiment. However, instead, the upper layer shield 260 can shield electromagnetic noise generated in the upper logic circuit 111.

  Thus, according to the third embodiment of the present technology, since the upper shield 260 is inserted between the spiral inductor 270 and the logic circuit 111, the logic circuit 111 is also protected from electromagnetic noise in addition to the inductor 270. can do. In addition, a single-ended signal can be output by a simple spiral inductor 270 as compared with the figure 8 shape.

<4. Fourth Embodiment>
In the first embodiment described above, the electromagnetic shield (upper layer shield 260) is disposed only above the inductor 250, but a magnetic field generated in a circuit below the inductor 250 or on the same substrate (lower chip 150). May cause electromagnetic noise. It is difficult to reduce such electromagnetic noise only with the upper shield 260. The semiconductor device 100 according to the fourth embodiment is different from that according to the first embodiment in that electromagnetic noise caused by circuits below the inductor 250 or on the same substrate is reduced.

  FIG. 15 is a circuit diagram showing a configuration example of the voltage controlled oscillator 240 and the electromagnetic shield in the fourth embodiment. In the fourth embodiment, in addition to the upper layer shield 260, an outer peripheral shield 280 and a lower layer shield 290 are further provided as electromagnetic shields.

  The outer peripheral shield 280 is an electromagnetic shield that surrounds the outer periphery of the inductor 250 in the lower chip 150. For example, conductive wiring surrounding the inductor 250 is used as the outer peripheral shield 280. The potential of the outer shield 280 is, for example, a floating potential. Note that the potential of the outer shield 280 may be a fixed potential.

  The lower shield 290 is an electromagnetic shield disposed below the inductor 250. The lower layer shield 290 is inserted between the lower chip 150 and the inductor 250, for example. A fixed potential (such as a ground potential) is applied to the lower shield 290. Note that the potential of the lower shield 290 may be a floating potential.

  FIG. 16 is an example of a perspective view of the inductor 250 and the electromagnetic shield in the fourth embodiment. In the figure, “a” is an example of a perspective view of the upper shield 260, and “b” in the figure is an example of a perspective view of the inductor 250. Further, c in the figure is an example of a perspective view of the outer periphery shield 280. This outer peripheral shield 280 is laminated according to the height of the inductor 250. In the drawing, d is an example of a perspective view of the lower layer shield 290. As the lower layer shield 290, for example, a PGS (patterned ground shield) having a certain pattern (such as a shape similar to X) is used. Instead of PGS, a shield having the same shape as the upper layer shield 260 may be disposed as the lower layer shield 290.

  In addition, although both the outer periphery shield 280 and the lower layer shield 290 are arrange | positioned, you may arrange | position only one of these.

  FIG. 17 is an example of a cross-sectional view of the inductor 250 and the electromagnetic shield in the fourth embodiment. As illustrated in the figure, the side surface of the inductor 250 is covered with the outer shield 280, the upper surface is covered with the upper layer shield 260, and the lower surface is covered with the lower layer shield 290. For this reason, the inductor 250 can be protected from electromagnetic noise due to a magnetic field generated in a circuit above, below and below the inductor 250. In addition, the circuit below the inductor 250 and the circuit on the lower chip 150 can be protected from electromagnetic noise caused by the magnetic field generated in the inductor 250.

  As described above, according to the fourth embodiment of the present technology, since the outer peripheral shield 280 and the lower shield 290 are further arranged on the outer periphery and the lower side of the inductor 250, the magnetic field from the circuits on the same substrate and the lower side as the inductor 250 Electromagnetic noise can be reduced.

  The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.

  In addition, the effect described in this specification is an illustration to the last, Comprising: It does not limit and there may exist another effect.

In addition, this technique can also take the following structures.
(1) a substrate on which an inductor is disposed;
A shield with an upper layer slit, which is an electromagnetic shield that is disposed above the inductor with a predetermined direction perpendicular to the substrate plane of the substrate as an upward direction, and in which a slit is formed along a direction parallel to the substrate plane. Semiconductor device.
(2) further comprising a circuit arrangement board on which the circuit is arranged;
The semiconductor device according to (1), wherein the circuit arrangement substrate is stacked on the substrate.
(3) The inductor is
A first wire wound clockwise from a predetermined start point to a predetermined connection point about a first central axis perpendicular to the substrate plane;
A second wire wound counterclockwise from the predetermined connection point to a predetermined end point about a second central axis that is perpendicular to the substrate plane and is different from the first central axis The semiconductor device according to (1), comprising:
(4) The semiconductor device according to (3), wherein the slit is formed along a direction parallel to a straight line connecting the first central axis and the second central axis.
(5) The inductor is
A first wiring wound along a spiral path that is swung a plurality of times from a predetermined start point to a predetermined connection point about a predetermined central axis perpendicular to the substrate plane;
A second wiring wound along a spiral path that swivels a plurality of times from the predetermined connection point to a predetermined end point around the predetermined central axis;
The turning radius of the first wiring decreases each time it turns from the predetermined starting point to the predetermined connecting point,
2. The semiconductor device according to claim 1, wherein the second wiring has a turning radius that increases each time the second wiring turns from the predetermined connection point to the predetermined end point. The semiconductor device according to (1).
(6) The semiconductor device according to (1), wherein the inductor includes a wiring wound along a spiral path.
(7) The semiconductor device according to any one of (1) to (6), further including an outer peripheral shield that is an electromagnetic shield surrounding an outer periphery of the inductor.
(8) The semiconductor device according to any one of (1) to (7), further including a lower-layer shield that is an electromagnetic shield disposed below the inductor.
(9) The shield according to any one of (1) to (8), further including a shield with a lower layer slit disposed below the inductor and having a slit formed in a direction parallel to the plane of the substrate. Semiconductor device.
(10) The semiconductor device according to any one of (1) to (9), wherein a fixed potential is applied to the shield with the upper layer slit.
(11) further comprising a capacitor connected to the inductor;
The semiconductor device according to any one of (1) to (10), wherein the inductor and the capacitor resonate.
(12) a phase comparator that compares the phases of the input signal and the feedback signal and outputs a detection signal indicating a phase difference;
A charge pump that generates a voltage signal of a voltage corresponding to the phase difference indicated by the detection signal;
A frequency divider that divides an oscillation signal generated by a resonance circuit including the inductor and the capacitor and feeds back as a feedback signal to the phase difference detector;
The semiconductor device according to (11), wherein the capacitor is a variable capacitor whose capacitance value changes according to the voltage signal.
(13) The semiconductor device according to (12), wherein the input signal is a clock signal.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 110 Upper chip | tip 111,151 Logic circuit 150 Lower chip | tip 200 Phase synchronous circuit 210 Phase comparator 220 Charge pump 230 Frequency divider 240 Voltage control oscillator 241 Amplifier circuit 242 Variable capacity 250, 265, 270, 302 Inductor 260 Upper layer Shield 280 Outer shield 290 Lower shield 301 AC power supply

Claims (13)

A substrate on which an inductor is disposed;
A shield with an upper layer slit, which is an electromagnetic shield that is disposed above the inductor with a predetermined direction perpendicular to the substrate plane of the substrate as an upward direction, and in which a slit is formed along a direction parallel to the substrate plane. Semiconductor device. A circuit arrangement board on which the circuit is arranged;
The semiconductor device according to claim 1, wherein the circuit arrangement substrate is stacked on the substrate. The inductor is
A first wire wound clockwise from a predetermined start point to a predetermined connection point about a first central axis perpendicular to the substrate plane;
A second wire wound counterclockwise from the predetermined connection point to a predetermined end point about a second central axis that is perpendicular to the substrate plane and is different from the first central axis The semiconductor device according to claim 1, further comprising: The semiconductor device according to claim 3, wherein the slit is formed along a direction parallel to a straight line connecting the first central axis and the second central axis. The inductor is
A first wiring wound along a spiral path that is swung a plurality of times from a predetermined start point to a predetermined connection point about a predetermined central axis perpendicular to the substrate plane;
A second wiring wound along a spiral path that swivels a plurality of times from the predetermined connection point to a predetermined end point around the predetermined central axis;
The turning radius of the first wiring decreases each time it turns from the predetermined starting point to the predetermined connecting point,
2. The semiconductor device according to claim 1, wherein the second wiring has a turning radius that increases each time the second wiring turns from the predetermined connection point to the predetermined end point. The semiconductor device according to claim 1, wherein the inductor includes a wiring wound along a spiral path. The semiconductor device according to claim 1, further comprising an outer peripheral shield that is an electromagnetic shield surrounding an outer periphery of the inductor.   The semiconductor device according to claim 1, further comprising a lower layer shield which is an electromagnetic shield disposed below the inductor.   The semiconductor device according to claim 1, further comprising a shield with a lower layer slit disposed below the inductor and having a slit formed along a direction parallel to the plane of the substrate. The semiconductor device according to claim 1, wherein a fixed potential is applied to the shield with the upper layer slit. Further comprising a capacitor connected to the inductor;
The semiconductor device according to claim 1, wherein the inductor and the capacitor resonate. A phase comparator that compares the phase of the input signal and the feedback signal and outputs a detection signal indicating a phase difference;
A charge pump that generates a voltage signal of a voltage corresponding to the phase difference indicated by the detection signal;
A frequency divider that divides an oscillation signal generated by a resonance circuit including the inductor and the capacitor and feeds back as a feedback signal to the phase difference detector;
The semiconductor device according to claim 11, wherein the capacitor is a variable capacitor whose capacitance value changes in accordance with the voltage signal. The semiconductor device according to claim 12, wherein the input signal is a clock signal.

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