JPWO2015001603A1 - Semiconductor switching element drive circuit and power conversion device using the same - Google Patents

Abstract

In a semiconductor switching element driving circuit that is connected to the gate of a unipolar semiconductor switching element having a pn junction between the gate and the source, such as JFET and SIT, and that drives the semiconductor switching element on and off, the semiconductor switching is performed when conducting. On-drive circuit that applies gate-source voltage between the gate and source of the element, current detection means for detecting the main circuit current, and the gate-source voltage according to the value of the main circuit current when conducting And a gate-source voltage control means to be changed. Thereby, the loss at the time of conduction including the power loss caused by the gate current is reduced.

Description

  INDUSTRIAL APPLICABILITY The present invention is suitable for a driving circuit for a semiconductor switching element, particularly a junction field effect transistor (hereinafter abbreviated as JFET), a static induction transistor (hereinafter abbreviated as SIT), and the like. The present invention relates to a circuit and a power conversion device using the circuit.

  In recent years, semiconductor elements made of wide gap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have attracted attention. These materials have a dielectric breakdown voltage strength as high as about 10 times that of Si, and the thickness of the drift layer for securing a withstand voltage can be reduced to about 1/10 of Si. For this reason, since the on-resistance of the semiconductor element, particularly the power device, is reduced, the power loss generated by the semiconductor element during conduction can be reduced. Under these circumstances, a unipolar SiC junction field effect transistor (hereinafter referred to as SiC-JFET), which is relatively easy to form a device as a switching element, has been mass-produced.

As a technique related to a drive circuit for switching and driving such a SiC-JFET, a technique described in Patent Document 1 is known. In the present technology, a gate drive voltage for turning on is applied between the gate and source of the SiC-JFET through two resistors connected in series. A MOSFET is connected in parallel to one of the two resistors. The MOSFET is turned off at room temperature (25 ° C.) and turned on at a high temperature (250 ° C.). Thus, at the time of high temperature, since the gate resistance is reduced, between the gate and source, forward rise voltage V _F over a large voltage between the gate and source is applied. For this reason, the SiC-JFET can be operated in a bipolar manner to reduce the on-resistance.

JP 2009-239214 A

In the prior art described above, in order to reduce the on-resistance, for applying a voltage V _F above voltage rise between the gate and the source, through a large gate current I _G. The power loss by the gate current I _G is generated, but not any consideration is given such a power loss in the prior art. However, as described next, for conduction loss of SiC-JFET, it can not be ignored influence of power loss or gate loss generated by the gate current I _G.

When the switching element is conducting, the conduction loss P _Rds generated from the on-resistance R _ds is generally expressed by the equation shown in Equation (1). In the formula (1), a and I _d are a constant and a drain current, respectively.

Ｒ_ｄｓは図２（ａ）に示したようにＶ_ＧＳに反比例して小さくなるため、ある程度のゲート電圧を持たなければ、導通損失が増加してしまう。さらに、Ｐ_Ｒｄｓは、ドレイン電流Ｉ_ｄの２乗にも比例することから、主回路電流の値、すなわち負荷率（Load Factor：以下ＬＦと略記）によっても大きく変化する。

Since R _ds decreases in inverse proportion to V _GS as shown in FIG. 2A, the conduction loss increases without a certain gate voltage. Furthermore, P _Rds, since it also proportional to the square of the drain current I _d, the value of the main circuit current, i.e. the load factor: varies greatly depending (Load Factor hereinafter LF hereinafter).

Here, in the structure of the JFET including the SiC-JFET, the gate layer and the source layer form a pn junction, and the current / voltage characteristics between the gate and the source exhibit forward diode characteristics when conducting. Accordingly, as shown in FIG. 2 (b), the gate current I _G in proportion to the gate-source voltage V _GS increases. JFET During conduction, since the flow is relatively large _{I G} than other switching elements such as MOSFET, could largely ignored in the case of other switching elements, the gate loss _{P Ig} of formula (2) is a JFET In case it cannot be ignored. In Expression (2), V _G is a gate drive voltage generated by the drive circuit.

上述したように、Ｉ_ＧはＶ_ＧＳに比例して大きくなることから、ＪＦＥＴのゲート駆動電圧Ｖ_Ｇをオンに必要な最低限の電圧にすることにより、Ｐ_Ｉｇを低減することができる。

As described above, since I _G increases in proportion to V _GS , P _Ig can be reduced by setting the gate drive voltage V _G of the JFET to the minimum voltage necessary for turning on.

Taking this P _Ig into account, the conduction loss P _{loss_on} is expressed by Equation (3).

すなわち、ＪＦＥＴを用いる場合には、Ｒ_ｄｓを小さくして、すなわちＰ_Ｒｄｓを小さくして導通時損失Ｐ_{ｌｏｓｓ＿ｏｎ}を低減させようとすると、ゲート・ソース間電圧Ｖ_ＧＳをある程度高く保つ必要がある。これによって大きなＩ_Ｇが流れて、Ｐ_Ｉｇが増加する。すなわち、Ｐ_ＲｄｓとＰ_Ｉｇの間にはトレードオフ関係が存在する。さらに、Ｐ_Ｒｄｓは図３に示すように、負荷率ＬＦすなわち主回路電流値によっても変化することから、ゲート電圧が一定である場合には、主回路電流値によっては、電力損失を増加させてしまう可能性がある。また、Ｐ_ＲｄｓおよびＰ_Ｉｇは、ＪＦＥＴの温度によってもその特性は変動する（図２（ｂ）参照）。

That is, when JFET is used, it is necessary to keep the gate-source voltage V _GS high to some extent if R _ds is reduced, that is, if P _Rds is reduced to reduce the conduction loss P _{loss_on} . Thus if a large _{I G flows, P Ig} is increased. In other _words, a trade-off relationship exists between the _{P Rds} and _{P Ig.} Further, as shown in FIG. 3, _PRds also varies depending on the load factor LF, that is, the main circuit current value. Therefore, when the gate voltage is constant, depending on the main circuit current value, the power loss is increased. There is a possibility. The characteristics of P _Rds and P _Ig also vary depending on the temperature of the JFET (see FIG. 2B).

As shown in FIG. 4, with respect to certain LF or main circuit current _{that, P Loss_on,} unlike _{P Rds} made smaller as increasing the gate voltage _{V GS,} the loss becomes minimum at a certain gate voltage. _{Therefore, P Ig is} small but compared with _{P Rds,} it can not be ignored in _{P loss_on. Furthermore,} minimum point _{P Loss_on,} since there is a temperature dependence _{P Rds} and _{P Ig} constituting the _{P Loss_on,} varies depending on the temperature.

As can be seen from the above, P _{loss_on} cannot be minimized by merely increasing the gate voltage. Therefore, the conventional technique described in Patent Document 1 has a problem that it is difficult to reliably reduce the conduction loss of the SiC-JFET.

  Accordingly, the present invention provides a drive circuit capable of reliably reducing loss during conduction of a unipolar semiconductor switching element having a pn junction between a gate and a source such as a SiC-JFET, and an inverter device using the drive circuit. .

  The semiconductor switching element drive circuit of the present invention is a semiconductor switching element drive circuit that is connected to the gate of a unipolar semiconductor switching element having a pn junction between the gate and the source and drives the semiconductor switching element on and off. An on-drive circuit section for applying a gate-source voltage between the gate and source of the semiconductor switching element when the semiconductor switching element is conductive, and a current detection means for detecting a main circuit current flowing through the semiconductor switching element And gate-source voltage control means for changing the gate-source voltage according to the value of the main circuit current detected by the current detection means when the semiconductor switching element is conductive. And

  In addition, the power converter of the present invention includes a series connection circuit in which unipolar first and second semiconductor switching elements each having a pn junction between a gate and a source are connected in series, for the number of AC phases, and the series connection First and second DC terminals connected to respective terminals of the circuit, AC terminals consisting of interconnection points of the first and second semiconductor switching elements, and gates of the first and second semiconductor switching circuits, respectively. 2. A power conversion device comprising two drive circuits, wherein the first drive circuit has a gate-source connection between the gate and source of the first semiconductor switching element when the first semiconductor switching element is conductive. A first on-drive circuit section for applying a voltage, and the second drive circuit when the second semiconductor switching element is turned on; A second on-drive circuit section for applying a gate-source voltage between the gate and source of the switching element, current detection means for detecting a main circuit current flowing in the semiconductor switching element, and the first semiconductor switching When the element is turned on, the gate-source voltage of the first semiconductor switching element is changed according to the value of the main circuit current detected by the current detection means, and the second semiconductor switching element is turned on. And a gate-source voltage control means for changing a gate-source voltage of the second semiconductor switching element according to a value of the main circuit current detected by the current detection means. To do.

  According to the present invention, it is possible to reduce power loss including gate loss, which occurs when a unipolar semiconductor switching element having a pn junction between a gate and a source is conductive. Furthermore, the power loss which a power converter device generate | occur | produces can be reduced by applying the drive circuit by this invention to a power converter device.

  Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments.

1 shows a driving circuit for a semiconductor switching element according to a first embodiment. An example of the relationship between on-resistance and gate voltage is shown. An example of the relationship between gate current and gate voltage is shown. An example of the relationship between conduction loss and gate loss and gate voltage is shown. An example of the relationship between loss during conduction and gate voltage is shown. The operation | movement waveform in a 1st Example is shown. The drive circuit of the semiconductor switching element which is a 2nd Example is shown. The operation | movement waveform in a 2nd Example is shown. The other operation | movement waveform in a 2nd Example is shown. The power converter device which is a 3rd Example is shown. The power converter device which is a 4th Example is shown.

  A driving circuit according to the present invention is a driving circuit for a semiconductor switching element that drives an on / off of a unipolar semiconductor switching element having a pn junction between a gate and a source. The gate-source voltage is changed according to the value. As a result, loss during conduction including loss due to on-resistance and gate loss can be reduced.

  One embodiment of the present invention is a driving circuit for a semiconductor switching element that is connected to a gate of a unipolar semiconductor switching element having a pn junction between a gate and a source and drives the semiconductor switching element on and off. This drive circuit includes an on-drive circuit section that applies a gate-source voltage between the gate and source of the semiconductor switching element and a current that detects a main circuit current flowing through the semiconductor switching element when the semiconductor switching element is conductive. Detection means; and gate-source voltage control means for changing the gate-source voltage in accordance with the value of the main circuit current detected by the current detection means when the semiconductor switching element is conductive.

  In the above aspect, the gate-source voltage is preferably changed so that the sum of the power loss caused by the on-resistance of the semiconductor switching element and the power loss caused by the gate current is within a minimum range with respect to the main circuit current. . Thereby, the loss at the time of conduction | electrical_connection is reduced reliably.

  The semiconductor switching element is a unipolar semiconductor switching element having a pn junction between the gate and the source, such as the above-described JFET or SIT.

  The constituent material of the semiconductor switching element may be not only a wide gap semiconductor such as SiC but also silicon.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a driving circuit for a semiconductor switching element according to a first embodiment of the present invention. In addition, although the main circuit element in a present Example and the other Example mentioned later is SiC-JFET, it is only described as JFET.

  The main circuit 100 includes a gate resistor 105a connected between the gates of JFET101 and JFET101, which are switching elements, and an output of a gate drive circuit 110 described later, a speed-up capacitor 105b connected in parallel to the gate resistor 105a, and the JFET101. A current transformer 108a that detects the flowing main circuit current and a temperature detection circuit 108b that detects the temperature of the JFET 101 are configured. A driving circuit 110 that drives the JFET 101 on and off is connected to the gate of the JFET 101 via a gate resistor 105a and a speed-up capacitor 105b.

  The drive circuit 110 has an npn transistor 114 that outputs a gate drive voltage for turning on to an emitter, with a collector connected to the gate power supply 117 for turn-on via a gate power supply 117 for turn-on and a gate resistor 113a. Prepare. A gate resistance switching pMOS 112a is connected in parallel to the gate resistance 113a. When the pMOS 112a is turned on, both ends of the gate resistance 113a are short-circuited.

  Further, the drive circuit 110 has a collector connected to the off-gate power source 118 via the off-gate power source 118 and the gate resistor 116 as an off-drive circuit unit, and outputs a gate drive voltage for off to the emitter. 115.

  When the npn transistor 114 and the pnp transistor 115 are complementarily driven by the drive logic circuit 111, the drive circuit 110 outputs gate drive voltages for on and off. Further, the gate-source voltage control circuit 109 provides a gate resistance switching signal to the pMOS 112a based on the main circuit current detected by the current transformer 108a and the temperature of the JFET 101 detected by the temperature detection circuit 108b. The total resistance value of the gate resistance connected between the JFET 101 and the on-gate power supply 117, that is, the effective gate resistance value in the on-drive circuit unit of the drive circuit 110 is controlled. In this embodiment, the gate resistance value is controlled to be either a resistance value corresponding to the on-resistance of the pMOS 112a or a resistance value of the gate resistance 113a, which is sufficiently smaller than the gate resistance 113a.

As described above, in this embodiment, in the drive circuit 110, the gate resistance value for turning on is switched based on the main circuit current and the temperature of the JFET 101. Accordingly, have the property of gate current _{I G} is proportional to the voltage _{V GS} between the gate and the source, and the on-resistance _{R ds} by conduction losses _{P Rds} is JFET101 is generated having a characteristic which is proportional to the square of the main circuit current The loss during conduction including the gate loss can be reduced to a minimum value or a value close thereto.

  Next, the operation of this embodiment will be described.

The main circuit current detected by the current transformer 108a is smaller than a preset current reference value I ₀ (see FIG. 5), and the temperature of the JFET 101 detected by the temperature detection circuit 108b is preset. When the temperature is lower than the temperature reference value T ₀ , the gate-source voltage control circuit 109 transmits an off control signal to the pMOS 112a. At this time, since the pMOS 112a is in an off state, the gate resistor 113a is not short-circuited. Therefore, the effective gate resistance value between the gate of the JFET 101 and the on-gate power supply 117 is the sum of the resistance values of the gate resistance 105a and the gate resistance 113a. When the detected main circuit current is larger than the current reference value (approximately ½ or more of the rated value) and the detected temperature is lower than the temperature reference value, the gate-source voltage control circuit 109 is turned off to the pMOS 112a. A control signal for transferring from ON to ON is transmitted. At this time, since the pMOS 112a is turned on, the gate resistor 113a is short-circuited. For this reason, the effective gate resistance value becomes substantially equal to the resistance value of the gate resistance 105a and becomes smaller. Therefore, the voltage value shared by the gate resistance in the gate drive voltage is reduced, and the voltage value applied between the gate and source of the JFET 101 can be increased accordingly.

Here, the gate-source voltage V _GS is set so that the conduction loss including the gate loss is close to the minimum value in each case where the main circuit current is smaller than the current reference value and larger. Controlled by switching. For example, in FIG. 4, when LF = 50 to 100%, loss during conduction can be minimized by controlling V _GS within the range of the gate control voltage in the figure. For such _VGS control, the relationship as shown in FIG. 4 is obtained in advance by actual measurement, simulation, or the like, and the resistance values of the gate resistors 105a and 113a and the voltage value of the gate power supply 117 are appropriately set based on the results. Set.

  Note that a shunt resistor, a JFET with a current sensing function, or the like may be used to detect the main circuit current. Further, the location where the main circuit current is detected may be on the drain side of the JFET 101 in addition to the source side of the JFET 101 as in this embodiment. Further, as the main circuit current detection means, the main circuit current value may be calculated from the load factor monitored by the control system during power supply operation, such as a server power supply. On the other hand, as the temperature detection circuit 108b, for example, a circuit using a temperature detection element such as a thermistor can be used.

  FIG. 5 shows operation waveforms in this embodiment. In the figure, the drain current of the JFET 101, that is, the main circuit current, the ON / OFF state of the gate resistance switching pMOS 112a, the ON resistance of the JFET 101, the gate current, and the loss during conduction are shown from the top. The conduction loss shown here is the sum of the conduction loss caused by the on-resistance of the JFET 101 and the gate loss caused by the gate current (the same applies to FIGS. 7 and 8 described later). In the present embodiment using a two-stage gate resistance value indicated by a solid line, compared to the case of using a conventional fixed gate resistance indicated by a broken line in the figure, the on-resistance can be reduced, Also, the increase in gate current can be suppressed to a constant value. Thereby, the loss at the time of conduction | electrical_connection of JFET101 can be reduced reliably.

  In FIG. 5, as a reference example, the operation waveform is shown by a one-dot chain line even when a gate current larger than that of the present embodiment is passed. As shown in this reference example, when the gate current is increased, the on-resistance is reduced, but the gate loss is increased, so that the conduction loss is larger than that of the present example and the conventional example.

  In this embodiment, by providing the speed-up capacitor 105b, the influence of the change in the gate resistance value on the JFET switching characteristics such as the turn-on characteristic and the turn-off characteristic can be reduced. For this reason, even if the value of the gate resistance changes, it is possible to drive at high speed without changing the switching speed and to suppress an increase in switching loss.

  FIG. 6 shows a driving circuit for a semiconductor switching element according to the second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same symbols. In the second embodiment, unlike the first embodiment, the gate resistance is switched in three stages. For this reason, in the ON drive circuit section of the drive circuit 110 that drives the JFET 101, a series connection circuit of the gate resistance switching pMOS 112b and the gate resistance 113b is further connected in parallel to the gate resistance 113a.

  In this embodiment, the gate resistance is switched in three stages. However, by increasing the number of gate resistance switching pMOS and gate resistance series-connected circuits connected in parallel to the gate resistance 113a, the gate resistance can be changed in four or more stages. You can also switch.

  FIG. 7 shows operation waveforms of the second embodiment. In the figure, from the top, the drain current of the JFET 101, that is, the main circuit current, the on / off state of the gate resistance switching pMOS 112a, the on / off state of the gate resistance switching pMOS 112b, the on resistance of the JFET 101, the gate current, and the conduction loss are shown. .

If the main circuit current of the first value smaller than the current reference value _{I 1,} the gate-source voltage control circuit 109 transmits the respective off control signal to pMOS112a and PMOS112b. At this time, since the pMOS 112a and the pMOS 112b are in the off state, the effective gate resistance value is the sum of the resistance values of the gate resistance 105a and the gate resistance 113a, and is the largest resistance value in the three stages. For this reason, the voltage applied between the gate and the source of the JFET 101 is the smallest.

When the main circuit current becomes larger than the preset first current reference value I ₁ (approximately 1/3 or more of the rated value), the gate-source voltage control circuit 109 keeps the pMOS 112a in the off state and the pMOS 112b A control signal for transferring the signal from OFF to ON is transmitted. At this time, since the pMOS 112a is in the off state and the pMOS 112b is in the on state, the effective gate resistance value is the sum of the parallel resistance value of the gate resistance 113a and the gate resistance 113b and the resistance value of the gate resistance 105a. It becomes the second largest resistance value in three stages. Therefore, the voltage applied between the gate and source of JFET 101 is slightly increased. As a result, the on-resistance is reduced and the gate current is also suppressed, so that loss during conduction can be reduced.

Further, when the main circuit current is larger than the first current reference value I ₁ and exceeds the preset second current reference value I ₂ (approximately 2/3 or more of the rated value), the gate-source connection The voltage control circuit 109 transmits control signals for shifting the pMOS 112a from off to on and the pMOS 112b from on to off. At this time, since the pMOS 112a is turned on, the effective gate resistance value becomes the resistance value of the gate resistance 105a, which is the smallest among the three stages. For this reason, the voltage applied between the gate and the source of JFET 101 is maximized, and the gate-source voltage value that suppresses the sum of the conduction loss caused by the on-resistance and the gate loss caused by the gate current to a minimum or close to the minimum is obtained. Reduced.

  FIG. 8 shows another operation waveform in the second embodiment. From the top, the drain current of the JFET 101, that is, the main circuit current, the detection temperature of the JFET, the on / off state of the gate resistance switching pMOS 112a, the on / off state of the gate resistance switching pMOS 112b, the on resistance of the JFET 101, the gate current, Indicates loss during conduction.

  When the main circuit current detected by the current transformer 108a is smaller than a preset current reference value and the temperature of the JFET 101 detected by the temperature detection circuit 108b is lower than a preset temperature reference value, The source voltage control circuit 109 transmits an off control signal to each of the pMOS 112a and the pMOS 112b. At this time, the effective gate resistance value is the sum of the resistance values of the gate resistance 105a and the gate resistance 113a, which is the largest resistance value among the three stages. For this reason, the voltage applied between the gate and the source of the JFET 101 is the smallest.

When the main circuit current becomes larger than the preset current reference value I ₀ (approximately 1/3 or more of the rated value), the gate-source voltage control circuit 109 keeps the pMOS 112a off and the pMOS 112b is turned off. Transmits a control signal for turning on. At this time, since the pMOS 112a is in the off state and the pMOS 112b is in the on state, the effective gate resistance value is the sum of the parallel resistance value of the gate resistance 113a and the gate resistance 113b and the resistance value of the gate resistance 105a. It becomes the second largest resistance value in three stages. Therefore, the voltage applied between the gate and source of JFET 101 is slightly increased. As a result, the on-resistance is reduced and the gate current is also suppressed, so that loss during conduction can be reduced.

Further, the main circuit current value does not change, and when the detected temperature becomes higher than the preset temperature reference value T ₀ , the gate-source voltage control circuit 109 turns the pMOS 112a from off to on and turns on the pMOS 112b. A control signal for transferring from OFF to OFF is transmitted. At this time, since the pMOS 112a is turned on, the effective gate resistance value becomes the resistance value of the gate resistance 105a, which is the smallest among the three stages. For this reason, the voltage applied between the gate and the source of JFET 101 is maximized, and the gate-source voltage value that suppresses the sum of the conduction loss caused by the on-resistance and the gate loss caused by the gate current to a minimum or close to the minimum is obtained. Reduced.

  In this embodiment as well, by providing the speed-up capacitor 105b as in the first embodiment, it is possible to drive at high speed without changing the switching speed and to suppress an increase in switching loss. .

  FIG. 9 shows a power converter according to a third embodiment of the present invention. In this figure, the same components as those in the embodiment of FIG.

  The power conversion device of FIG. 9 is an inverter device, and converts the DC power of the DC power source 107 into AC power by switching on and off JFETs 101 and 102 in the main circuit 100. A main circuit 100 in the figure is one phase of an inverter device, and has a series connection circuit of JFET 101 and JFET 102. Although not shown, this series connection circuit is provided for the number of AC phases, for example, three for a three-phase AC.

  Both ends of the series connection circuit of JFET 101 and JFET 102, that is, a DC terminal, are connected to DC power supply 107 via main circuit wiring inductances 127 and 128. The AC power is output from an interconnection point between JFET 101 and JFET 102, that is, an AC terminal. JFETs 101 and 102 are connected in parallel to unipolar diodes 103 and 104 such as Schottky barrier diodes, respectively. These diodes function as freewheeling diodes.

  As in the first embodiment, the drive circuit 110 shown in FIG. 1 is connected to the gate of the JFET 101 via a gate resistor 105a and a speed-up capacitor 105b. Similar to JFET 101, drive circuit 120 having the same configuration as drive circuit 110 shown in FIG. 1 is connected to the gate of JFET 102 via gate resistor 106a and speed-up capacitor 106b. However, the gate-source voltage control circuit 109 in the drive circuit 110 also transmits a control signal for switching the gate resistance to the drive circuit 120.

  Each drive logic circuit in drive circuits 110 and 120 drives npn and pnp transistors in each drive circuit on and off in response to a command signal from control circuit 121. In this embodiment, the current transformer 108a for detecting the main circuit current is inserted into the AC output wiring taken out from the connection point between the JFET 101 and the JFET 102. The temperature detection circuit 108b detects the temperature of the JFET 102 on behalf of the JFETs 101 and 102, but may detect the temperature of the JFET 101. Further, each temperature of JFET 101 and JFET 102 may be detected.

  Similarly to the first embodiment, the drive circuits 110 and 120 drive the JFETs 101 and 102 while switching the gate resistance when conducting. As a result, the conduction loss including the gate loss in JFETs 101 and 102 can be reduced to a minimum value or a value close to the minimum value. Therefore, the power loss generated by the inverter device can be reduced.

  In FIG. 10, the power converter device which is the 4th Example of this invention is shown. In the figure, the same components as those in the embodiment of FIGS.

  In the present embodiment, unlike the third embodiment, the drive circuit of the second embodiment shown in FIG. 6 is used as the drive circuits 110 and 120.

  As in the second embodiment, the drive circuits 110 and 120 drive the JFETs 101 and 102 while switching the gate resistance when conducting. As a result, the conduction loss including gate loss in the JFETs 101 and 102 can be reduced to a minimum value or a value close to the minimum value. Therefore, the power loss generated by the inverter device can be reduced.

  In addition, this invention is not limited to each embodiment mentioned above, Various modifications are included. For example, each of the above-described embodiments has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. A part of the configuration of an embodiment can be replaced with the configuration of another embodiment, and further, the configuration of another embodiment can be added to the configuration of an embodiment. Furthermore, it is possible to add, delete, or replace other configurations for a part of the configuration of each embodiment.

  For example, the above-described embodiments can be applied not only to JFETs but also to SITs. These semiconductor switching elements may be either a normally-on type or a normally-off type. Furthermore, as a semiconductor material constituting the semiconductor switching element, a wide gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN), or silicon (Si) that has been conventionally used can be applied. When a wide gap semiconductor is used, the forward voltage of the pn junction is high and the gate loss is large, so that the effect of the present invention is great.

  Further, the npn transistor 114 and the pnp transistor 115 in the drive circuit can be replaced with other switching elements such as pMOS and nMOS. Furthermore, the gate-source voltage of the semiconductor switching element may be changed by switching the voltage value of the on-gate power supply.

  The power converter may be a forward converter as well as an inverter, that is, an inverse converter. The free wheel diode used in the main circuit in these power converters may be a bipolar pn diode.

DESCRIPTION OF SYMBOLS 100 ... Main circuit, 101, 102 ... JFET, 103, 104 ... Diode, 105a, 106a, 113a, 113b, 116 ... Gate resistance, 105b, 106b ... Speed-up capacitor, 107 ... DC power supply, 108a ... Rent transformer, 108b ... Temperature detection circuit 109 ... Gate-source voltage control circuit 110, 120 ... Drive circuit, 111 ... Drive logic circuit, 112a, 112b ... pMOS, 114 ... npn transistor, 115 ... pnp transistor, 117, 118 ... Gate power supply, 121 ... Control circuit, 127,128 ... Main circuit wiring inductance

Claims (14)

A semiconductor switching element driving circuit connected to a gate of a unipolar semiconductor switching element having a pn junction between a gate and a source and driving the semiconductor switching element on and off,
An on-drive circuit unit that applies a gate-source voltage between the gate and source of the semiconductor switching element when the semiconductor switching element is conductive;
Current detection means for detecting a main circuit current flowing through the semiconductor switching element;
Gate-source voltage control means for changing the gate-source voltage according to the value of the main circuit current detected by the current detection means when the semiconductor switching element is conductive. Semiconductor switching element drive circuit. In the drive circuit of the semiconductor switching element according to claim 1,
The semiconductor switching element drive circuit, wherein a gate current in the semiconductor switching element increases in proportion to the gate-source voltage. In the semiconductor switching element drive circuit according to claim 2,
The gate-source voltage control means is configured to calculate a sum of a power loss caused by an on-resistance of the semiconductor switching element and a power loss caused by the gate current with respect to the main circuit current flowing through the semiconductor switching element during the conduction. A drive circuit for a semiconductor switching element, wherein the gate-source voltage is changed so as to be minimized. In the drive circuit of the semiconductor switching element according to claim 3,
The gate-source voltage control means changes the resistance value of a gate resistor connected between the gate of the semiconductor switching element and a gate power supply included in the on-drive circuit unit, thereby A drive circuit for a semiconductor switching element, wherein the voltage is changed. In the drive circuit of the semiconductor switching element according to claim 4,
A drive circuit for a semiconductor switching element, comprising: a speed-up capacitor connected between a gate of the semiconductor switching element and a gate power supply included in the ON drive circuit unit. In the drive circuit of the semiconductor switching element according to claim 1,
Furthermore, it comprises a temperature detection means for detecting the temperature of the semiconductor switching element,
The gate-source voltage control means is responsive to the value of the main circuit current detected by the current detection means and the temperature value detected by the temperature detection means when the semiconductor switching element is conductive. A drive circuit for a semiconductor switching element, wherein the gate-source voltage is changed. In the drive circuit of the semiconductor switching element according to claim 1,
A semiconductor switching element driving circuit, wherein the semiconductor material constituting the semiconductor switching element is a wide gap semiconductor. A unipolar type first and second semiconductor switching elements each having a pn junction between the gate and the source are provided in series connection circuits for the number of AC phases, and a DC terminal consisting of both ends of the series connection circuit; A power conversion device comprising: an AC terminal comprising an interconnection point of first and second semiconductor switching elements; and first and second drive circuits connected to the gates of the first and second semiconductor switching, respectively. Because
The first driving circuit includes a first on-driving circuit unit that applies a gate-source voltage between a gate and a source of the first semiconductor switching element when the first semiconductor switching element is conductive;
The second drive circuit includes a second on-drive circuit unit that applies a gate-source voltage between the gate and the source of the second semiconductor switching element when the second semiconductor switching element is conductive;
Current detection means for detecting a main circuit current flowing through the semiconductor switching element;
The gate-source voltage of the first semiconductor switching element is changed according to the value of the main circuit current detected by the current detecting means when the first semiconductor switching element is turned on, and the second Gate-source voltage control means for changing the gate-source voltage of the second semiconductor switching element according to the value of the main circuit current detected by the current detection means when the semiconductor switching element is turned on; A power conversion device comprising: In the power converter device described in Claim 8,
The power conversion device according to claim 1, wherein gate currents in the first and second semiconductor switching elements increase in proportion to the gate-source voltage. In the power converter device described in Claim 9,
The gate-source voltage control means has a minimum range in which the sum of the power loss caused by the on-resistance of the first semiconductor switching element and the power loss caused by the gate current is reduced with respect to the main circuit current during the conduction. As described above, the gate-source voltage of the first semiconductor switching element is changed, and the sum of the power loss caused by the on-resistance of the second semiconductor switching element and the power loss caused by the gate current is minimized. A power conversion device that changes a gate-source voltage of the second semiconductor switching element so as to be in a range. In the power converter device described in Claim 10,
The gate-source voltage control means changes a resistance value of a gate resistor connected between a gate of the switching element of the first semiconductor and a gate power supply included in the first on-use drive circuit unit. Changing the gate-source voltage of the switching element of the first semiconductor,
The gate-source voltage control means changes a resistance value of a gate resistor connected between a gate of the second semiconductor switching element and a gate power supply included in the second on-drive circuit unit. To change the gate-source voltage of the switching element of the second semiconductor. In the power converter device described in Claim 11,
A speed-up capacitor connected between a gate of the first semiconductor switching element and a gate power supply included in the first on-drive circuit unit; a gate of the second semiconductor switching element; and the second on-state A power conversion device comprising: a speed-up capacitor connected between a gate power supply included in the drive circuit unit for use. In the power converter device described in Claim 8,
And a temperature detecting means for detecting the temperature of the first semiconductor switching element or the second semiconductor switching element,
The gate-source voltage control means is responsive to the value of the main circuit current detected by the current detection means and the temperature value detected by the temperature detection means when the semiconductor switching element is conductive. A power conversion device that changes the gate-source voltage of the first and second semiconductor switching elements. In the power converter device described in Claim 8,
A power conversion device, wherein the semiconductor material constituting the first and second semiconductor switching elements is a wide gap semiconductor.

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