JPWO2009154242A1 - Manufacturing method of MIS field effect transistor - Google Patents

Abstract

Provided is a method for manufacturing a MIS field effect transistor that can manufacture a MISFET having a shallow junction and low parasitic resistance by making the source / drain extension region tip and the gate electrode end approach each other with good controllability without short-circuiting. Forming a gate electrode on the semiconductor substrate via the gate insulating film (S1), forming an insulating film on the semiconductor substrate including the gate electrode surface (S2), and covering the surface of the gate electrode of the insulating film; A step (S3) of modifying the portion so that the etching rate is slow, a step (S4) of removing an unmodified portion of the insulating film from the surface of the semiconductor substrate by isotropic etching, and a modification. Using the formed insulating film as a mask, a step (S5) of selectively forming a semiconductor film on the surface of the semiconductor substrate, and a step of forming source / drain portions based on the semiconductor film (S6) are included.

Description

  The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a MIS (Metal Insulator Semiconductor) type field effect transistor having no deterioration phenomenon called a short channel effect and low parasitic resistance.

  In recent years, with the development of information and communication equipment, the processing capability required for LSIs is increasing, and the speed of MIS field effect transistors has been increased. This speeding up has been promoted mainly by miniaturization of the structure, but it is difficult to reduce the thickness of the gate insulating film due to physical factors. (Hereinafter, the MIS field effect transistor is also referred to as MISFET (Metal Insulator Semiconductor Field Effect Transistor).)

  For this reason, it has become important to reduce the parasitic resistance of the MISFET and improve the characteristics. In particular, the source / drain extension regions have shallow junctions to prevent a MISFET deterioration phenomenon called a short channel effect, and have a large parasitic resistance. Therefore, if the parasitic resistance of the source / drain extension region can be reduced, the performance of the MISFET can be improved.

  On the other hand, as a method for reducing the parasitic resistance of the source / drain region while keeping the junction shallow, a technique for raising the source / drain extension region is known. According to this technology, the physical depth of the source / drain extension region that determines the parasitic resistance can be increased while keeping the junction depth that affects the electrical operation of the MISFET shallow, so that the shallow junction and the low parasitic resistance can be achieved. It is possible to achieve both.

  Methods for raising the source / drain extension regions are disclosed in Patent Documents 1 to 4.

  Patent Document 1 discloses the simplest method. In this method, after a gate electrode made of a polycrystalline semiconductor film is formed on a semiconductor substrate via a gate insulating film, the semiconductor film is selectively deposited only on the semiconductor surface directly by a selective growth method. However, in this method, since the semiconductor film is also deposited on the side surface of the gate electrode, the raised height must be set to be equal to or lower than the gate insulating film in order to prevent a short circuit with the source / drain extension region.

  Patent Document 2 discloses that a gate electrode material is a metal in order to eliminate such a restriction. In this method, since the gate electrode cannot be formed of a polycrystalline semiconductor, there are significant restrictions.

  Patent Document 3 discloses these two problems, that is, a method in which the gate electrode is formed of a polycrystalline semiconductor and the raised height is set to be higher than that of the gate insulating film. That is, after the insulating film is isotropically deposited on the entire surface including the gate electrode, the surface of the semiconductor substrate is exposed by anisotropic etching to form a structure in which only the side surface of the gate electrode is covered with the insulating film spacer. Thereafter, if a semiconductor film is selectively deposited, it is possible to raise the height exceeding the gate insulating film while preventing a short circuit between the gate electrode and the source / drain extension region.

  However, in the method disclosed in Patent Document 3, the raised source / drain extension region tip is separated from the gate electrode end by the thickness of the insulating film spacer. Then, the channel and the source / drain extension region are separated from each other, and the parasitic resistance increases. This is called an offset. When the offset occurs, the original purpose of reducing the parasitic resistance is lost. If an attempt is made to eliminate the offset by ion implantation or impurity diffusion in order to prevent this, since the junction spreads in the depth direction, the original purpose of reducing the junction depth is still lost.

  Therefore, in the method disclosed in Patent Document 3, it is important to make the insulating film spacer film thickness as thin as possible. Although the thickness of the insulating film spacer is a design matter, there is actually a lower limit in terms of process controllability and stability. For example, when the film thickness of the insulating film spacer is 2 nm or less, the anisotropic etching time is too short (about several seconds), the end point cannot be detected, and the substrate must be etched to some extent. This is a phenomenon peculiar to anisotropic etching with a finite selectivity. In this case, an extra semiconductor film must be deposited in order to refill the substrate etching portion, resulting in an increase in cost. In addition, since the etching depth of the substrate is time-controlled, the final raised height varies depending on the etching rate. In particular, the latter (which causes variations in the final raised height due to variations in the etching rate) is a major problem.

  1 to 4 show a method of forming a raised source / drain extension region (a method disclosed in Patent Document 3) by protecting the side wall of the gate electrode with a single-layer side wall protective film. This is the most common method for raising the source / drain extension regions.

  First, after forming an element isolation region 2 in which an oxide film is embedded in a silicon substrate 1, an insulating film 3, a non-doped polycrystalline silicon film 4, and a silicon nitride film 21 are formed (FIG. 1A), and these are patterned. Then, the gate insulating film 6, the gate electrode 22, and the top protective film 23 for protecting the top of the gate electrode from silicon growth are formed (FIG. 1B).

  Next, a silicon oxide film 24 is deposited on the entire surface of the substrate (FIG. 1C). Here, the film thickness of the silicon oxide film 24 is set to 5 nm or more in consideration of the stability of end point detection during anisotropic dry etching. Thereafter, a sidewall protective film 25 that protects the gate electrode sidewall from silicon growth is formed by anisotropic etching (FIG. 2A).

  At this time, overetching is always performed in consideration of the etching rate and the variation in the film thickness of the silicon oxide film 24 in the silicon substrate. Over-etching is to perform etching longer than the etching time expected from the etching rate. Typically, etching is performed for 1.5 times the expected etching time.

  In the case of anisotropic etching, since the etching selectivity between the silicon substrate 1 and the silicon oxide film 24 is finite, the silicon substrate is also slightly scraped. This amount of shaving varies depending on the in-plane variation in the thickness of the silicon oxide film 24 and the in-plane variation in the etching rate of the silicon substrate 1. Further, as shown in FIG. 2A, the oxide film inside the element isolation region 2 also recedes.

  Next, by using a selective growth method, silicon is selectively grown only on the exposed surface of the silicon substrate 1 while doping boron, thereby forming a raised source / drain extension region 10 (FIG. 2B). .

  Next, a silicon oxide film 11 is deposited on the entire surface of the substrate (FIG. 2C), and sidewall spacers 12 are formed by etch back (FIG. 3A). An oxide film that has not been removed by etching remains as a residual oxide film 26 on the element isolation region 2.

  Thereafter, boron is ion-implanted into the silicon substrate 1 using the gate electrode 22, the sidewall protective film 25, and the sidewall spacers 12 as a mask to form deep source / drain regions 13 (FIG. 3B). At this time, boron is simultaneously implanted into the gate electrode 22 to become a boron-doped gate electrode 27.

  When the boron-doped gate electrode 27 is formed in this manner, the distance between the raised source / drain extension region 10 and the boron-doped gate electrode 27 is separated by the thickness of the sidewall protective film 25 (referred to as offset). In this case, a large parasitic resistance is generated between the channel immediately below the boron-doped gate electrode 27 of the MISFET and the raised source / drain extension region 10.

  In order to prevent this, after forming the deep source / drain extension region 13, heat treatment is performed to diffuse impurities from the raised source / drain extension region 10, and the channel just below the source / drain extension region 10 and the boron-doped gate electrode 27. Impurity diffusion region 14 is formed so as to be connected (overlapped) (FIG. 3C). At this time, the impurity diffusion region 14 extends in the depth direction, which is contrary to the purpose of forming a shallow junction.

  Next, the top protective film 23 is removed with phosphoric acid or the like (FIG. 4A). Next, nickel is deposited and heat treatment is performed to cause silicidation reaction between the deep source / drain region 13 and the surface of the boron-doped gate electrode 27 to form nickel silicide layers 15 and 15 ′. Excess nickel is removed (FIG. 4B).

  In the structure shown in FIG. 4B, since the side wall of the boron doped gate electrode 27 is protected by the side wall protective film 25, the raised source / drain extension region 10 and the gate boron doped gate electrode 27 may be short-circuited. No.

  However, if the raised source / drain extension region 10 and the boron doped gate electrode 27 are overlapped, the junction becomes deep. If the junction of the source / drain extension regions becomes deep, various MISFET deterioration factors called short channel effects appear.

  Patent Document 4 discloses a method of reducing the distance between the raised source / drain extension region tip and the gate electrode end. The spacer for protecting the gate side wall has a two-layer structure, and the first layer is L-shaped. After the spacer is formed on the side wall of the gate electrode by anisotropic etching, a portion in contact with the L-shaped first layer substrate is etched in the lateral direction by isotropic etching to form a notch. After that, if the semiconductor film is selectively deposited, the semiconductor film is deposited in the notch portion, so that the distance between the raised portion end and the gate electrode end can be adjusted by the lateral etching amount.

  5 to 8 show a method in which the side wall protective film on the side wall of the gate electrode has a two-layer structure, and a notch is made in the first layer to bring the tip of the raised source / drain extension region close to the gate electrode end (Patent Document). 4).

  First, after forming an element isolation region 2 in which an oxide film is embedded in a silicon substrate 1, an insulating film 3, a non-doped polycrystalline silicon film 4, and a silicon nitride film 21 are formed (FIG. 5A), and these are patterned. Then, the gate insulating film 6, the gate electrode 22, and the top protective film 23 for protecting the top of the gate electrode from silicon growth are formed (FIG. 5B).

  Next, a silicon oxide film 31 and a silicon nitride film 32 are sequentially deposited on the entire surface of the substrate (FIG. 5C). Here, the film thickness of the silicon oxide film 31 is set to 5 nm or more in consideration of the stability of end point detection during anisotropic dry etching and the spillability of dilute hydrofluoric acid. The film thickness of the silicon nitride film 32 is set to 3 nm or more in consideration of the covering ability of the silicon oxide film 31. Thereafter, sidewall protective films 34 and 35 for protecting the gate electrode sidewall from silicon growth are formed by anisotropic etching (FIG. 6A).

  At this time, overetching is always performed in consideration of the etching rate and the variation in the thickness of the silicon oxide film 31 and the silicon nitride film 32 in the silicon substrate. As described above, the over-etching is to perform etching longer than the etching time expected from the etching rate, and the etching is typically performed for 1.5 times the expected etching time.

  In the case of anisotropic etching, since the etching selectivity between the silicon substrate 1 and the silicon oxide film 31 is finite, the silicon substrate is also slightly scraped. This amount of shaving varies due to in-plane variations in the film thickness of the silicon oxide film 31 and the silicon nitride film 32 and in-plane variations in the etching rate of the silicon substrate 1. Further, as shown in FIG. 6A, the oxide film inside the element isolation region 2 also recedes during the anisotropic etching.

  Next, the exposed portion of the sidewall protective film 34 is isotropically etched using dilute hydrofluoric acid to form a notch portion 36, and the sidewall protective film 34 ′ in which the exposed portion of the silicon substrate 1 has receded to the vicinity of the gate electrode is formed. It forms (FIG.6 (b)). In practice, the notch is also formed in the vicinity of the top of the gate electrode 22 of the side wall protective film 34, but is omitted from FIG.

  When the notch portion 36 is formed, the oxide film in the element isolation region 2 recedes as much as the lateral depth of the notch portion 36. Further, as shown in FIG. 6B, there is a possibility that the etching proceeds too much due to the variation in the etching rate and the gate electrode exposed portion 37 is generated.

  Next, by using a selective growth method, silicon is selectively grown only on the exposed surface of the silicon substrate 1 while doping boron to form a raised source / drain extension region 10 (FIG. 6C). . At this time, if the gate electrode exposed portion 37 exists, silicon grows in that portion, and a source / drain extension region short-circuit portion 38 is generated.

  Next, a silicon oxide film 11 is deposited on the entire surface of the substrate (FIG. 7A), and sidewall spacers 12 are formed by etch back (FIG. 7B). An oxide film that has not been removed by etching remains as a residual oxide film 26 on the element isolation region 2.

  Thereafter, boron is ion-implanted into the silicon substrate 1 using the gate electrode 22, the side wall protective film 34 ′, the side wall protective film 35, and the side wall spacer 12 as a mask to form deep source / drain regions 13 (FIG. 7C). )). At this time, boron is simultaneously implanted into the gate electrode 22 to become a boron-doped gate electrode 27.

  When the boron-doped gate electrode 27 is formed in this way, the distance between the raised source / drain extension region 10 and the boron-doped gate electrode 27 is separated by the thickness of the sidewall protective film 34 '(referred to as offset). In this case, a large parasitic resistance is generated between the channel immediately below the boron-doped gate electrode 27 of the MISFET and the raised source / drain extension region 10.

  In order to prevent this, a deep source / drain extension region 13 is formed so as to connect (overlap) the source / drain extension region and the channel just below the boron-doped gate electrode 27, and then heat treatment is applied to raise the source / drain extension. Impurities are diffused from the extension region 10 to form an impurity diffusion region 14 (FIG. 8A). At this time, the impurity diffusion region 14 extends in the depth direction, which is contrary to the purpose of forming a shallow junction. However, compared with Patent Document 3 (FIG. 3C), since the distance between the raised source / drain extension region 10 and the boron-doped gate electrode 27 is short, the diffusion distance of the impurity diffusion region 14 is small and the influence is small. .

  Next, the top protective film 23 is removed with phosphoric acid or the like (FIG. 8B). Next, nickel is deposited and heat treatment is performed to cause silicidation reaction between the deep source / drain region 13 and the surface of the boron-doped gate electrode 27 to form nickel silicide layers 15 and 15 ′. Excess nickel is removed (FIG. 8C).

JP 7-86579 A JP-A-3-050771 JP 2007-31376 A JP 2000-49348 A

  However, using the notch structure as in the method disclosed in Patent Document 4 has a problem in mass production. First, since the depth of the notch is controlled by the etching time, if the etching rate varies within the wafer surface, the notch depth tends to vary. This is a process problem common to the problem of Patent Document 3.

  Another problem is that the silicon substrate 1 is scraped when the silicon oxide film 24 is over-etched. That is, in order to refill the etching portion of the silicon substrate 1, an extra silicon film must be deposited, resulting in an increase in cost. In addition, due to variations in the etching depth of the silicon substrate 1, variations in the final raised height will occur. These cause variations in the characteristics of the MISFET and reduce the yield. These are problems that always occur as long as the shape is formed by anisotropic etching.

  In particular, if the depth of the notch portion 36 is increased in order to make the distance between the raised end of the source / drain extension region 10 and the end of the gate electrode 22 as close as possible, the notch advances to the portion in contact with the gate electrode 22, and the gate There is a possibility that the electrode 22 is exposed and a gate electrode exposed portion 37 is formed. If the semiconductor film is deposited even though the gate electrode exposed portion 37 exists, the source / drain extension region short-circuit portion 38 is generated, causing a short circuit between the source / drain extension region 10 and the gate electrode 22. In the above manufacturing method example, since the formation of the notch portion 36 is performed by controlling the etching time, the gate electrode exposed portion 37 is likely to occur, and the source / drain extension region short-circuit portion 38 is likely to be formed. When the source / drain extension region short-circuit portion 38 is formed, a leak current flows between the source / drain and the gate electrode of the MISFET, and the off characteristics of the MISFET are significantly deteriorated.

  In order to prevent this, the distance between the raised tip of the source / drain extension region 10 and the end of the gate electrode 22 must be separated to some extent, and the distance between the tip of the source / drain extension region 10 and the end of the gate electrode 22 is also reduced. It is necessary to set a lower limit in

  Further, since the oxide film etching is performed twice, that is, anisotropic etching at the time of forming the spacer and isotropic etching at the time of forming the notch, the buried oxide film in the element isolation region 2 recedes during this time. Then, depending on the manufacturing method of the MISFET, a short circuit may be caused between the drain electrode and the substrate during the salicide process. As a result, the leakage current increases and the power consumption of the MISFET increases.

  As described above, in the methods disclosed in each patent document, there is a limit in bringing the raised source / drain extension region tip and the gate electrode end close to each other, reducing parasitic resistance and reducing the junction depth. There is a trade-off relationship. In addition, some problems due to the manufacturing process occur as described above.

  The present invention has been made in view of such a problem. The MIS can manufacture a MISFET having a shallow junction and low parasitic resistance by bringing the tip of the source / drain extension region and the gate electrode end close to each other with good controllability without short-circuiting. An object of the present invention is to provide a method for manufacturing a type field effect transistor.

  In order to achieve the above object, the present invention provides a method of manufacturing a MIS field effect transistor, which includes a step of forming a gate electrode on a semiconductor substrate through a gate insulating film, and a semiconductor substrate including a gate electrode surface A step of forming an insulating film thereon, a modification step of modifying the portion of the insulating film that covers the surface of the gate electrode so that the etching rate is slow, a portion of the insulating film that is not modified, etc. Removing from the surface of the semiconductor substrate by isotropic etching; selectively forming a semiconductor film on the surface of the semiconductor substrate using the modified insulating film covering the surface of the gate electrode as a mask; and The present invention provides a method for manufacturing a MIS type field effect transistor, which includes a step of forming a source / drain portion on the basis thereof.

  According to the present invention, there is provided a method for manufacturing a MIS field effect transistor capable of manufacturing a MISFET having a shallow junction and low parasitic resistance by bringing the source / drain extension region tip and the gate electrode end close to each other with good controllability without short-circuiting. Can be provided.

It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 3. FIG. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 3. FIG. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 3. FIG. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 3. FIG. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 4. FIG. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 4. FIG. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 4. FIG. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor disclosed by patent document 4. FIG. It is a figure which shows the flow of the manufacturing method of the MIS type | mold field effect transistor which concerns on this invention. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor which concerns on suitable embodiment of this invention. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor which concerns on suitable embodiment of this invention. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor which concerns on suitable embodiment of this invention. It is a figure which shows an example of the process of the manufacturing method of the MIS type | mold field effect transistor which concerns on suitable embodiment of this invention.

  As shown in FIG. 9, the method for manufacturing a MIS field effect transistor according to the present invention includes a step of forming a gate electrode on a semiconductor substrate via a gate insulating film (step S1), and a semiconductor substrate including a gate electrode surface. A step of forming an insulating film thereon (step S2), a modification step of modifying a portion of the insulating film covering the surface of the gate electrode so as to reduce the etching rate (step S3), and a modification of the insulating film; The step of removing the unpolished portion from the surface of the semiconductor substrate by isotropic etching (step S4) and the modified insulating film covering the surface of the gate electrode as a mask are selectively used on the surface of the semiconductor substrate. A step of forming a semiconductor film (step S5), and a step of forming source / drain portions based on the semiconductor film (step S6).

According to the present invention, since the insulating film on the surface of the semiconductor substrate can be etched by isotropic etching, an etchant having a high selectivity can be used.
This is due to the following reason. First, anisotropic etching is performed in a state where the etchant has a larger kinetic energy in a specific direction in order to produce anisotropy. Therefore, the sputtering effect by a physical action is necessarily included. Therefore, etching always occurs regardless of the material.
On the other hand, in the case of isotropic etching, the etching proceeds purely by the chemical action of the etchant. Therefore, an infinite selection ratio can be taken between different materials. For example, dilute hydrofluoric acid etches the silicon oxide film, but does not etch the silicon substrate at all.

  As a result of using an etchant with a high selectivity, there is no problem that the surface of the semiconductor substrate is etched, so that the oxide film covering the gate electrode surface in a self-aligning manner can be made sufficiently thin. Therefore, a structure in which the distance between the gate electrode and the raised source / drain extension region is sufficiently close can be easily realized without short-circuiting the two.

  In addition, since the insulating film can be etched with better control than anisotropic etching, the problem of etching the surface of the semiconductor substrate due to overetching and the problem of the oxide film retreating in the element isolation region do not occur.

  Further, since the shape is formed by utilizing the difference in etching rate instead of controlling the etching time, unlike the cited document 4, the shape is not easily affected by variations in the etching rate and etching time.

  Further, since only the insulating film in contact with the gate electrode can be selectively slowed down, the insulating film covering the surface of the gate electrode can be formed with high accuracy in a self-aligning manner.

  By these effects, a structure in which the distance between the gate electrode and the raised source / drain extension region is sufficiently close can be realized stably and simply without short-circuiting the two. As a result, it is possible to create a MISFET with low parasitic resistance, no short channel effect, and small variations.

  Hereinafter, preferred embodiments of the present invention will be described.

FIG. 10 to FIG. 13 show an example of the steps of the method for manufacturing the MIS field effect transistor according to the preferred embodiment of the present invention.
First, after an element isolation region 2 in which an oxide film is embedded is formed on a silicon substrate 1, an insulating film 3 and a non-doped polycrystalline silicon film 4 are formed (FIG. 10A). Thereafter, boron is added to the non-doped polycrystalline silicon film 4 by ion implantation to convert it into a boron-added polycrystalline silicon film 5 (FIG. 10B).

  Next, these are patterned to form the gate insulating film 6 and the gate electrode 7 (FIG. 10C). Each process shown in FIGS. 10A to 10C corresponds to the process in step S1 in FIG.

  Next, a silicon oxide film 8 is deposited on the entire surface of the substrate (FIG. 11A). At this time, it is sufficient that the surface of the gate electrode 7 is not exposed, and there is no lower limit to the thickness of the silicon oxide film 8. For example, a very thin film of about 1.5 nm may be formed. The process shown in FIG. 11A corresponds to the process of step S2 of FIG.

  Thereafter, boron is diffused from the gate electrode 7 into a portion of the silicon oxide film 8 in contact with the surface of the gate electrode 7 by heat treatment to be modified into a boron-added gate electrode protective film 9 (FIG. 11B). The process shown in FIG. 11B corresponds to the process of step S3 in FIG.

  Thereafter, only the silicon oxide film 8 on the surface of the silicon substrate 1 is selectively removed with dilute hydrofluoric acid (FIG. 11C). That is, since the etching rate of the boron-added silicon oxide film is smaller than that of the silicon oxide film not doped with boron, the surface of the gate electrode is covered with the silicon oxide film in a self-aligned manner by adjusting the etching time. Can be formed. Such a technique is disclosed in Japanese Patent Laid-Open No. 56-042346, “Journal of the Korean Physical Society”, Korea, 1998, November, vol. 33, p. S99. The process shown in FIG. 11C corresponds to the process of step S4 in FIG.

  Since dilute hydrofluoric acid can make the etching selectivity between the silicon oxide film and silicon infinite, the etching of the silicon substrate 1 does not occur. If the concentration of dilute hydrofluoric acid is adjusted to be low, the etching rate of the silicon oxide film can be suppressed sufficiently low, so that the silicon oxide film on the surface of the silicon substrate 1 does not cause the oxide film in the element isolation region 2 to retract. Only 8 can be removed.

  Next, by using a selective growth method, silicon is selectively grown only on the exposed surface of the silicon substrate 1 while doping boron to form a raised source / drain extension region 10 (FIG. 12A). . Note that after growing non-doped silicon on the exposed surface of the silicon substrate 1, boron is ion-implanted using the gate electrode 7 as a mask to form a silicon layer doped with boron on the silicon substrate 1. The source / drain extension region 10 may be used. That is, silicon deposition and boron doping may be performed in parallel, or boron may be doped after silicon deposition is completed. The process shown in FIG. 12A corresponds to the process of step S5 in FIG.

  Next, a silicon oxide film 11 is deposited on the entire surface of the substrate (FIG. 12B), and sidewall spacers 12 are formed by etch back (FIG. 12C). At this time, the boron-added gate electrode protective film 9 on the top of the gate electrode is etched together with the silicon oxide film 11.

  Thereafter, using the gate electrode 7, the boron-added gate electrode protective film 9 and the sidewall spacer 12 as a mask, the silicon substrate 1 is doped with boron (for example, by ion implantation) to form deep source / drain regions 13 (FIG. 13). (A)).

  Since the horizontal distance between the raised source / drain extension region 10 and the gate electrode 7 is exactly zero and not offset, there is no problem in the operation as the MISFET. However, when the source / drain extension region 10 and the gate electrode 7 are overlapped, the parasitic resistance is further reduced and the MISFET has less variation.

For this reason, after forming the deep source / drain regions 13, heat treatment is performed to diffuse the impurities from the raised source / drain extension regions 10, thereby forming the impurity diffusion regions 14 (FIG. 13B). At this time, since the impurity diffusion region 14 extends in the depth direction, the junction becomes deep. However, since the spread of the impurity diffusion region 14 necessary for realizing the overlap is much smaller than that in Patent Documents 3 and 4, the junction depth is hardly increased, and the short channel effect is not achieved. The deterioration factor called is not generated.
The process shown in FIGS. 12B to 13B corresponds to the process of step S6 in FIG.

  Next, nickel is deposited and heat treatment is performed to cause a silicidation reaction between the deep source / drain region 13 and the surface of the gate electrode 7 to form nickel silicide layers 15 and 15 ′. Excess nickel is removed (FIG. 13C).

  As described above, the manufacturing method of the MIS field effect transistor according to this embodiment uses dilute hydrofluoric acid as an etchant for isotropic etching when the oxide film on the surface of the silicon substrate 1 is removed. At the time of removal, the silicon substrate 1 is not etched. Further, if the concentration of dilute hydrofluoric acid is adjusted to be low, the etching rate of the silicon oxide film can be suppressed sufficiently low, so that the silicon on the surface of the silicon substrate 1 does not cause the oxide film in the element isolation region 2 to recede. Only the oxide film 8 can be removed.

  Further, the horizontal distance between the raised source / drain extension region 10 and the gate electrode 7 can be made zero without short-circuiting them.

  As a result, it is possible to form a MISFET having a small parasitic resistance, little variation, and no short channel effect.

  The structure of the MISFET manufactured by applying the manufacturing method of the MIS field effect transistor according to the present embodiment (or in the process of manufacturing) includes cross-sectional observation of the transistor with a transmission electron microscope and the like, and EDX (energy dispersive X-ray analysis). It can be confirmed by combining with the composition analysis by equipment: Energy Dispersive X-ray spectrometer).

In addition, the said embodiment is an example of suitable implementation of this invention, and this invention is not limited to this.
For example, in the above embodiment, boron is used as an impurity for slowing the etching rate, but nitrogen may be used. When nitrogen is added to the silicon oxide film, the properties are close to those of the silicon nitride film, so that the etching selectivity can be obtained by hydrofluoric acid. That is, if impurities that can be modified into films having different scientific properties and an etchant that can reflect the difference in the scientific properties as an etching selectivity are used in combination, the types of impurities and etchants are arbitrary.
Further, although thermal diffusion is used in the above-described embodiment as a method for incorporating impurities that slow the etching rate into the silicon oxide film, an oxidation reaction can also be used. If the surface of the polycrystalline silicon gate electrode containing boron is oxidized, an oxide film containing boron is automatically formed.
In the above embodiment, the nickel silicide layer is formed in the source / drain region. However, if the source / drain region having a sufficiently small resistance component can be formed, the nickel silicide layer is not necessarily provided.
In the above description, a P-channel type MISFET is taken as an example. However, it goes without saying that an N-channel type MISFET can be formed by changing impurities doped in the silicon substrate and the source / drain extension regions.
As described above, the present invention can be variously modified.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-158956 for which it applied on June 18, 2008, and takes in those the indications of all here.

1 Silicon substrate 2 Element isolation region 3 Insulating film 4 Non-doped polycrystalline silicon film 5 Boron-doped polycrystalline silicon film 6 Gate insulating films 7 and 22 Gate electrode 8 Silicon oxide film 9 Boron-added gate electrode protective film 10 Raised source / drain extension Region 11, 24, 31 Silicon oxide film 12 Side wall spacer 13 Deep source / drain region 14 Impurity diffusion region 15, 15 ′ Nickel silicide layer 21, 32 Silicon nitride film 23 Top-part protective film 25, 34, 35 Side wall protective film 26 Residual oxide film 27 Boron doped gate electrode 34 'Recessed sidewall protective film 36 Notch portion 37 Gate electrode exposed portion 38 Source / drain extension region short-circuit portion

Claims (12)

A method of manufacturing a MIS field effect transistor, comprising:
Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming an insulating film on a semiconductor substrate including the gate electrode surface;
A modification step of modifying a portion of the insulating film covering the surface of the gate electrode so as to reduce an etching rate;
Removing the unmodified portion of the insulating film from the surface of the semiconductor substrate by isotropic etching;
Forming a semiconductor film selectively on the surface of the semiconductor substrate using the modified insulating film covering the surface of the gate electrode as a mask;
Forming a source / drain portion based on the semiconductor film. A method of manufacturing a MIS field effect transistor.   2. The method of manufacturing a MIS field effect transistor according to claim 1, wherein the semiconductor film is formed while doping with a first impurity.   2. The method of manufacturing a MIS field effect transistor according to claim 1, wherein after forming the semiconductor film, the semiconductor layer is doped with a first impurity using the gate electrode as a mask. The step of forming the source / drain portion includes:
Forming a mask layer covering the side surface of the gate electrode and the semiconductor film in the vicinity of the gate electrode;
4. The method of manufacturing a MIS field effect transistor according to claim 1, further comprising a step of doping the semiconductor film with a first impurity using the mask layer as a mask. 5.   3. The step of forming the source / drain portion includes a step of diffusing the first impurity from a semiconductor film doped with the first impurity into the semiconductor substrate by heat treatment. 5. A method for manufacturing a MIS field effect transistor according to any one of items 1 to 4. The reforming step includes
A step of incorporating a second impurity having a property of slowing down an etching rate of the insulating film added to the gate electrode into a portion of the insulating film covering the surface of the gate electrode. The method for manufacturing a MIS field effect transistor according to claim 1. Forming the gate electrode on the semiconductor substrate,
Forming a gate insulating film and a non-doped semiconductor film on the semiconductor substrate;
Adding the second impurity to the non-doped semiconductor film to transform it into an impurity-added semiconductor film;
7. The method of manufacturing a MIS field effect transistor according to claim 6, further comprising a step of removing the gate insulating film and the impurity-added semiconductor film from the semiconductor substrate except for a predetermined region.   By diffusing the second impurity added in the gate electrode or oxidizing the surface of the gate electrode, the second impurity is applied to a portion of the insulating film covering the surface of the gate electrode. 8. The method for producing a MIS field effect transistor according to claim 6, wherein the MIS type field effect transistor is incorporated.   9. The method of manufacturing a MIS field effect transistor according to claim 6, wherein the second impurity is nitrogen or boron.   10. The method for manufacturing a MIS field effect transistor according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the insulating film is a silicon oxide film.   11. The method of manufacturing a MIS field effect transistor according to claim 10, wherein the isotropic etching is performed with a solution containing hydrofluoric acid. 12. The method of manufacturing a MIS field effect transistor according to claim 1, further comprising a step of forming a conductive layer on a part of the source / drain portion.

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