JPS6395813A - Missing pkase detection circuit for inverter - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an open phase protection circuit for a multi-phase inverter including three phases.

[Prior art and its problems]

As a conventional open-phase detection circuit for this type of inverter, one that utilizes the waveform change of the three-phase output current when the phase is open is known, taking the three-phase inverter shown in FIGS. 4(a) and (b) as an example. . (a) of FIG. 4 shows a case where the three-phase inverter output current is normal for each phase, and (b) between the cores shows the U-phase and V-phase current waveforms with a W-phase loss. In other words, W-phase missing phase U-phase current I
u has the same magnitude as the V-phase current Iv, and its phase is reversed. Conversely, the V+1 current Iv becomes equal to the inversion current of the U-phase current Iu. If the reversal currents for this winter phase currents Iu, Iv, and Iw are expressed as Tu%Tv and Tw, the above phase current relationship for the W phase with and without phase is J:u = Iv,
Express it as Iv = Iu, Iw = O. Similarly, V
Mutual deficit and mutuality are Iw = Iu, Iu = Iw, Iv
= 0, and for U mutually exclusive and mutually compatible v = Iw, Iw =
The relationships Iv and Iu = O hold true. In other words, when one of the three phases has an open phase, the phase current of one of the other two phases becomes equal to the reversal current of the remaining phases. The conventional three-phase inverter defect detection circuit calculates a combination of the above-mentioned relationships, so the circuit configuration has to be complicated.

[Purpose of the invention]

In view of the above, the present invention has a Bf circuit configuration compared to the conventional method.
An object of the present invention is to provide an inverter open-phase detection circuit that is designed to improve reliability and detection operation reliability.

[Summary of the Invention] In order to achieve the above object, the present invention includes a DC current transformer that detects the DC input current value of an inverter, and a plurality of DC current transformers that respectively detect the current value of each phase of the multiphase AC output current of the inverter. An AC current transformer, an operational term 1i1 unit that reduces and transforms the detected current value of the DC transformer into an appropriate value, and each phase of the polyphase AC output current using the output value of the operational amplifier as a reference value. A plurality of current comparators that determine the magnitude of the detected value, a plurality of time relays that receive the manual force value as input, an OR element that receives the output signal of the plurality of time relays as input, and an output of the inverter. It consists of a frequency limiter that emits an output signal when the AC frequency is above a specific value (-), and an AND element that receives the output signal of the +7 mitter and the output signal of the OR element, and outputs the AC output of the inverter. When there is no open phase in each phase, the current value of each AC output phase is smaller than the current reference value determined by the +jir calculation amplifier, which is determined as a value through which the AC output phase current always passes. If the period becomes longer than the setting time of the plurality of time-limited relays, which are all set to be the same as a period longer than the cycle corresponding to the minimum operating frequency of the inverter and have an appropriate fluctuation margin, the state is different from which output. This is an inverter open phase detection circuit that generates an open phase signal when a phase error occurs in the inverter output phase (this is also considered as an output phase open state of the inverter).

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 1 is a circuit diagram showing an embodiment of the present invention using a three-phase inverter as an example of a phase loss detection target, and Fig. 2 is a detection operation waveform corresponding to Fig. 1, taking as an example the U-phase current phase loss. FIG. 3 is a detection operation waveform diagram in which the inverter output frequency is reduced to 1/2 of that in FIG. 2.

In FIG. 1, a DC power supply 1 supplies power to a three-phase transistor inverter 20 whose basic elements are a transistor 2 and a free-wheeling diode 3.
2, three-phase variable frequency AC power is supplied. The detection current Ide of the DC current transformer 4 for detecting the input side DC current of the inverter 20 and the AC current transformer 5m forming the output AC current transformation circuit 5.

The detection values Iu, Iv and Iw of the three-phase AC output current of the inverter 20 detected by the inverter 5b and 5C are respectively applied to the open phase calculation circuit 21. The arithmetic circuit 2
In 1, the operational amplifier 6 is a calculation unit for reducing the value of the DC detection current Idc, and the current comparator 8a is a calculation unit for comparing the output value of the amplifier 6 and the current detection value Iu. , the time limit capacitor 9a, the time limit resistor 10a, and the voltage comparator 11a constitute a time limit relay circuit for the duration of the current detection value Iu. Similarly, a current comparator 8b, a timed capacitor 9b, a timed resistor 101) and a voltage comparator 11b
is for comparison and judgment of the current detected value 1v,
Current comparator 8C, time limit capacitor 9C, time limit resistor 10e
and the voltage comparator 11c are for comparing and determining the current detection value Iw.

The logical sum element (OR element) 12 is the voltage comparator 11a, ll
The output signals of b and lie are input, and the output signals are sent to an AND element (A
The output signal of the NI3 element 13 becomes the required open phase detection signal of the inverter 20.

In the embodiment of the present invention, the DC current Idc is input to an operational amplifier 6, which converts it to a threshold value of 1/2 and outputs it as Ide/2. The current value Ide/2 is the three-phase AC output current detection value Iu,
This serves as a reference value for comparison calculations with Iv and Iw, and if there is no open-phase abnormality in each phase of the three-phase AC output of the inverter 20, each of the currents Iu, Iv, and Iw is required in its time fluctuation. This value is set as the value that is passed through. The above-mentioned comparison operation of the magnitudes of both AC and DC currents is performed in current comparators 8a, 8b and 8c, respectively, according to the currents Iu, Iv and Iw. For example, regarding the U-phase current, the current Iu is the reference value Idc.
/2, the current comparator 8a issues an output signal, and the terminal voltage Vc of the next stage time-limiting capacitor 9a becomes a negative potential ■
When the current Iu becomes larger than its reference value Idc/2, the current comparator 8
a inverts the output and sets the terminal voltage V of the time capacitor 9a.
c is reset to a negative potential ~-. When the U-phase output circuit is normal, the charging and resetting operations of the terminal voltage Vc are repeated for each cycle of the current Iu, and the value of the voltage Vc never reaches the zero potential OV. FIG. 2 shows the fluctuation pattern of the voltage Vc and current Iu mentioned above. In FIG. 2, if the current Iu disappears as an open phase at time Tf, the terminal voltage Vc will change at time Tf.
After the elapse of s, the voltage reaches zero potential OV, and at this point the next stage voltage comparator 11a issues an output signal indicating the occurrence of an open phase. That is, the time Ts gives the setting time of the time-limited relay circuit, and is determined by the value C of the time-limited capacitor 9a and the time-limited resistor 10a.
The value R is given by T$=0.693RC. Incidentally, the charging time constant of the terminal voltage Vc is RC.

Figure 3 shows the U-phase current Iu(f) of frequency f shown in Figure 2 and its 1/! This figure also shows the operation pattern of open phase detection for the current Iu(Mf) having a frequency of With respect to Iu(+f), they become 'n and n, respectively.

Also, is the time for the terminal voltage Vc to reach the operating signal potential OV of the voltage comparator 11a shorter than the time T2?
It will be longer than To. Therefore, the current Iu(ft>
In this case, even during normal operation, the voltage comparator 11a will generate an open phase signal. In order to avoid this, the set time Ts of the time-limited relay circuit is determined to be longer than the time corresponding to W in the current waveform at the lowest operating frequency of the inverter 20 with an appropriate margin. The set time Ts is also used in common as the time for checking phase failure for the other phase currents Iv and Iw, and the calculation results for checking phase failure are calculated using voltage comparators in the same way as for the U-phase current Iu. 11
b and llc, and becomes an input signal to an OR element (ORT: child) 12 together with the output signal of the voltage comparator 11a. Frequency 17 for emitting an output signal It is input to an AND element (AND element) 13 together with the Mitsutaf output signal, and the AND element generates an output signal S on the condition that both signals are input at the same time.

Therefore, the reliability of the signal S is increased by being constrained by two factors: time confirmation by the set time Ts of the time-limited relay circuit and frequency confirmation by frequency + J Mitsutaf, and the reliability of the signal S is increased by This is an open phase detection signal that is output when an open phase abnormality occurs in any of the three AC output phases of the inverter 20 in a state where the AC output phase is greater than a specified value.

〔Effect of the invention〕

As described above, the present invention simplifies the circuit configuration compared to conventional means because the open phase detection of each phase of the AC output of the inverter is performed by direct determination based on the magnitude and duration of each AC phase current. It is designed to be simple, and in principle can be generally applied to multi-phase AC circuits including three-phase, and is designed to improve reliability so as to avoid false detection due to instantaneous interruptions in the output AC current. be.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
Corresponding to the figure, FIG. 3 is a detection operation waveform diagram exemplifying the U-phase current phase loss.
Figure 4 (a) is a detection operation waveform diagram that also shows the case where the three-phase AC output current is normal. FIG. 3 is a waveform diagram of U-phase and V-phase currents with a W phase missing in FIG. l...DC power supply, 2...transistor, 3...commutated diode, 4...DC current transformer, 5...output AC current transformation circuit,
5a, 5b, 5c...AC current transformer, 6...arithmetic amplifier,
7...Frequency limiter, 8a, 8b, 8c...Current comparator, 9a, 9b, 9c...Time capacitor, 10a, 1
0b, 10c...Timed resistance, 11a, 11b, 11c...
・Voltage comparator, 12-0 Ri element, 13...AND element,
2o...Inverter, 21...Open phase calculation circuit, 22...
Impark load, S... Inverter open phase signal. ,,Q1'Figure 2Figure 3(Q)Figure 4

Claims (1)

[Claims] a DC current transformer that detects the DC input current value of the inverter;
a plurality of AC current transformers that respectively detect the current values of each phase of the multiphase AC output current of the inverter; an operational amplifier that converts the detected current value of the DC current transformer into a suitable value; and the calculation. a plurality of current comparators that determine the magnitude of each phase detection value of the multiphase AC output current using the output value of the amplifier as a reference value; a plurality of time relays that receive the comparator output signal as input; A logical sum element which receives a time relay output signal as an input, a frequency limiter which emits an output signal when the output AC frequency of the inverter is above a specific value, and the limiter output signal and the output signal of the logical sum element as inputs. A period in which each phase current detection value of the multiphase AC output current is smaller than a current reference value by the operational amplifier is determined in relation to the lowest operating frequency of the inverter. In addition, if the time becomes longer than the setting time of the plurality of time-limited relays, which is set as a common value for the plurality of time-limited relays, no matter which output phase this state occurs, this is treated as an output phase open state of the inverter. An open phase detection circuit for an inverter, characterized in that it emits an open phase signal.