JPS6393214A - Set/reset circuit for flip flop - Google Patents

Abstract

PURPOSE:To eliminate signal delay and to facilitate detecting the position where trouble occurs, by combining two NAND circuits and AND circuits in the circuit whose set or reset are determined at the time of power-on in accordance with application of the signal in the high level or the low level to a state determining signal terminal. CONSTITUTION:Two NAND circuits 21 and 22 and two AND circuits 23 and 24 are provided, and a voltage obtained by integrating a supply voltage 5 by a resistance 12 and a capacitor 13 is applied to one terminal of each of circuits 21 and 22, and the other terminals are connected to input and output terminals of an inverter 9 for a signal terminal 2 of the signal which determines the state of a flip flop FF 1, and one terminal of the circuit 23 and that of the circuit 24 are connected to a reset terminal 3 and a set terminal 4, and the other terminals are connected to output terminals of circuits 21 and 22 and respective output terminals of AND circuits are individually connected to the set terminal and the reset terminal of the FF 1. Thus, the signal applied to the terminal 2 is immediately operated by the combinational circuit of AND circuits and NAND circuits to determine the state of the FF 1 as an automatic reset circuit or an automatic set circuit. Therefore, the signal propagation time is shortened. The position where trouble occurs is easily detected because of the simple constitution.

Description

[Detailed description of the invention] [Summary] Set and reset flip-flops when power is turned on.
In a circuit that is determined by the application of "H" and "L" signals to the signal terminal for determining the state, a flip-flop circuit that combines two sets of NAND circuits and AND circuits enables reliable operation and enables early detection in the event of a failure. This is a set/reset operation circuit for the

[Industrial Application Field] The present invention relates to a circuit that determines the cent reset of a flip-flop when power is turned on by applying an "H" or "L" signal to a state determining signal terminal.

Conventionally, this type of circuit uses a complicated circuit, so there is a delay in operation, making it difficult to find the target circuit when a failure occurs. It was requested that a solution be found.

[Prior Art] In a flip-flop used to control electromagnetic components to be driven or not driven, a circuit is known which is provided with a signal terminal used to specify the set/reset state of the component when power is turned on to the system. It is. FIG. 4 is an excerpted drawing of a similar circuit described in Japanese Patent Application Laid-Open No. 58-135539.

In FIG. 4, reference numeral 1 denotes a flip-flop, and its output controls electromagnetic components such as an electromagnetic relay 20 to be driven or not. 6 For example, when the output terminal Q of the flip-flop 1 is "H", a current flows through the relay 20. When the terminal Q is set to "L", it becomes non-driven.

To perform such control, normally when a signal "L" is applied to the S terminal 4 and a signal "H" is applied to the R terminal 3, the output terminal Q becomes "L" and the other output terminal Q becomes "H". When simply applying a signal 'H' to the S terminal 4 and a signal 'L' to the R terminal 3, the output terminal Q becomes "H" and the other output terminal Q becomes "L".

This circuit operates when flip-flop 1 is activated when commercial power is turned on, or when commercial power is interrupted and restored shortly during normal operation.
There are cases where it is desired to specify the state of the output terminal Q of the device as "H" or "L". A terminal 2 is used when performing the specified operation. That is, if an "H" signal is applied to the A terminal 2 at the same time as the power is turned on, or an oven is applied, the flip-flop 1 is turned on and the output of the terminal Q becomes "L". A terminal 2
The circuit from 1 to flip-flop 1 operates as an automatic reset circuit. Conversely, when the A terminal 2 is set to "L" or grounded, the flip-flop 1 is set and the output of the terminal Q becomes "H". In this case, it operates as an automatic setting circuit.

This operation will be further explained with reference to the waveform diagram in FIG.

FIG. 5(a) shows changes in the value of power supply voltage Vcc. This voltage is applied to terminal 5 and charges capacitor 13 via resistor 12. When the charging voltage of the capacitor 13 becomes equal to the sum of the voltage between the diode and the base-emitter of the transistor 1o, the transistor 10 is turned on and its collector voltage becomes "L". At that time, the output of the inverter 8 becomes "H", and the output of the inverter 6 becomes "L" as shown in FIG. 5 (bl).

On the other hand, if the A terminal 2 is in the oven state, when the voltage VCCO value of the terminal 5 becomes normal when the power is turned on, the transistor 11 is turned on and the output of the inverter 9 is changed to
It becomes "H" as shown in C). At this time, the output of the inverter 7 is "L" as shown in FIG.
Since the outputs of inverter 9 and inverter 6 are wired (AND circuit), the signal is as shown in Figure 5 +e)
It becomes as shown in . Line L will soon change from “H” to “L”
”. This is because, as will be described later, the switch changes when the capacitor 13 is fully charged.The line L changes to “H”.
9', flip-flop 1 is set via OR circuit 15. The signal on line M remains at L'' as shown in FIG. 5(r).

At this time, if A terminal 2 is grounded, transistor 1
1 is off, its collector potential is "H", the output of the inverter 9 is "L", and the flip-flop 1 is reset.

When the A terminal 2 is open, a signal delay occurs in the inverter 8.6, and a wired connection (AND circuit) is made on the output side of the inverter 6, so when the capacitor 13 is fully charged, the line N has a Figure 5 (a trigger pulse shown as gl appears).

[Problems to be Solved by the Invention] The circuit shown in Figure 4 uses a large number of inverters 6 to 9, and the output of inverter 6 constitutes an AND circuit with wired connections, so it is difficult to propagate signals. It was time consuming and had a large signal delay.

Furthermore, when a failure occurs, it is extremely difficult to determine, for example, which inverter has gone bad.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-flop set/reset circuit which improves the above-mentioned drawbacks, eliminates signal delay with a relatively simple circuit, and allows the location of failure to be distinguished and determined.

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In Figure 1, 1 is a flip-flop, 2 is a flip-flop 1
3 is a reset signal application terminal, 4 is a signal terminal for determining the state of
1 is a set signal application terminal, 5 is a power supply voltage Vcc application terminal, 8 and 9 are inverters, 12.19 is a resistive element, 13 is a capacitor, 20 is an electromagnetic component such as an electromagnetic relay, 21.
22 is a NAND circuit, and 23 and 24 are AND circuits.

A logical operation is performed on the value obtained by integrating the power supply voltage Vcc by the resistive element 12 and the capacitor 13 and the signal at the state determination signal terminal 2 of the flip-flop 1. In a flip-flop set/reset circuit that further performs other logical operations on the output signal with the signals from the reset terminal 3 and set terminal 4 and applies it to the set/reset terminal of the flip-flop 1, the present invention has the following configuration. It is said that That is, it is equipped with two sets of NAND circuits 21, 22 and two sets of AND circuits 23, 24, and a voltage obtained by integrating the power supply voltage 5 is applied to one terminal of each of the NAND circuits 21, 22, and the other terminal of each of the NAND circuits 21, 22 is The input/output terminals of the inverter 9 are connected to the state determination signal terminal 2 of the flip-flop 1, one terminal of each AND circuit 23.24 is connected to the reset terminal 3 and the cent terminal 4, and the other terminal is connected to each NAND circuit 21.24. 22 output terminals, and each output terminal of the AND circuit is connected to the set terminal and reset terminal of the flip-flop 1, respectively.

[Function] With the circuit configuration shown in FIG. 1, the signal applied to the state verification signal application terminal 2 is immediately calculated by a circuit that combines an AND circuit and a NAND circuit, and is applied to the flip-flop 1.
The state of is determined as an automatic reset circuit/automatic set circuit. Therefore, the signal propagation time can be shortened and it is easy to integrate the circuit.

[Embodiment] FIG. 2 specifically shows the configuration of the NAND circuit and AND circuit portion in FIG. 1 as an embodiment of the present invention. In FIG. 2, VDD+VSS indicates a power supply terminal, and each component uses a field effect transistor FET. The two drain terminals of each FET are connected to each other.

FIG. 3 shows an operating waveform diagram of FIG. 2. Figure 3 Ta
) is the potential of the power supply Vcc, (b) is the output of the inverter 8, (C) is the potential of the A terminal 2, (d) is the output signal of the NAND circuit 21, (e) is the AND The output signal of circuit 22 is shown.

Pulses are generated as shown in FIG. 3('b) from the time the inverter 8 rises to a predetermined potential for operation until the charging is completed.

Now, if we open terminal 2 so that the potential of A terminal 2 becomes Vcc (“H”) when the power is turned on, the inverter 90
The input side becomes "H" and the output side becomes "L".

In the NAND circuit 21, the input signal is “H” (inverter 8
When the output is "H") and "L" (by the inverter 9), the output becomes "H". Next, inverter 8
Even if the output of NAND circuit 21 changes to “L”, the output of
” remains unchanged (see Figure 3 (d)).

In the NAND circuit 22, the input signal is the output of the inverter 8.
Since the input that does not pass through inverter 9 is "H", the output starts at "L", and then the output of inverter 8 becomes "L".
When the voltage drops to 0, the output becomes 'H' (see Fig. 3 (el)).

The output of the NAND circuit 21 becomes "H", and the AND circuit 2
4, one input terminal receives "H" from the S terminal 4, so the output of the AND circuit 24 is "H".
”. When the output of the NAND circuit 22 becomes “L”, the AND circuit 23 calculates “H” from the R terminal 3, the output of the AND circuit 23 becomes “L”, and at the fall, the flip-flop Next, when the output of the NAND circuit 22 changes from "L" to "H", the output of the AND circuit 23 changes to "H". At this time, both the set and reset terminals of the flip-flop 1 become "H". Since the potential is present, the flip-flop 1 enters the "accepting state" and waits for the next input from the R terminal 3 and S terminal 4. In this way, the flip-flop 1 is placed in the "reset" state and then remains stable in the accepting state.

Next, when the commercial power supply fails, the potential of the A terminal 2 becomes "L" as Vcc becomes zero. Even when the power is restored, A terminal 2
Consider the case where the potential of is operated as grounded "L". Since the input side of the inverter 9 is "L" and the output side is "H", when the output of the inverter 8 becomes "H", the NAND circuit 2
The output of NAND circuit 22 remains “L” while the output of NAND circuit 22 remains “H”.
”. Next, when the output of the inverter 8 changes to “L”, the output of the NAND circuit 21 changes to “H” (see Fig. 3 (di)). Also, the NAND circuit 22 remains at “H”. (See Figure 3(e)) Since the output of the NAND circuit 21 is applied to the AND circuit 24, when the output is "L", the output of the AND circuit 24 becomes "L", and at the falling edge, the flip-flop 1 is set.Next, when the input "L" of the AND circuit 24 changes to "H", the output becomes "H" and the flip-flop l enters the receiving state.

In this way, depending on the state of A terminal 2, flip-flop 1
is set or reset at power-on.

[Effects of the Invention] Thus, according to the present invention, a circuit in which the set/reset state is determined by a signal to the state determining signal terminal of a flip-flop can be simplified by combining an AND circuit and a NAND circuit.

Since it is easy to integrate them into an integrated circuit, the overall size can be reduced and signal propagation time can be shortened.

Furthermore, because of the simple configuration, when a failure occurs, it is easy to find the location and take immediate action.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the invention, and Fig. 3 is a diagram showing the configuration of the embodiment of the present invention.
FIG. 4 is a diagram showing a conventional set/reset circuit, and FIG. 5 is an operation waveform diagram of FIG. 4. 1--Flip-flop 2--State determination signal application terminal 3--Reset terminal R 4--Set terminal S 5--Power supply voltage terminal Vcc 8.9--Inverter 12-Resistance element 13- - Capacitor 20 - Electromagnetic relay 21.22 - NAND circuit 23.24 - AND circuit Patent applicant Fujitsu Ltd. Agent Patent attorney Eisuke Suzuki Operating waveform diagram Figure 3 (d) Output of inverter 7 f) Line □ Operation waveform diagram in Figure 4

Claims (1)

[Claims] A voltage obtained by integrating the power supply voltage (5) and a flip-flop (
A logical operation is performed on the signal of the state determination signal terminal (2) of 1), and the output signal is sent to the reset terminal (3) and the set terminal (4).
) in a flip-flop set/reset circuit that performs other logical operations on the signal from the flip-flop (1) and applies it to the set/reset terminal of the flip-flop (1). A voltage obtained by integrating the power supply voltage (5) is applied to one terminal of each of the NAND circuits (21) and (22), and a flip-flop (1 ) is connected to the input/output terminal of the inverter (9) for the state determination signal terminal (2), and one terminal of each of the AND circuits (23) and (24) is connected to the reset terminal (3) and set terminal (4). , the other terminal is connected to the output terminal of each NAND circuit (21) (22), and each output terminal is separately connected to a set terminal and a reset terminal of the flip-flop (1). set/reset circuit.