JPS6387860U - - Google Patents
Info
- Publication number
- JPS6387860U JPS6387860U JP18305186U JP18305186U JPS6387860U JP S6387860 U JPS6387860 U JP S6387860U JP 18305186 U JP18305186 U JP 18305186U JP 18305186 U JP18305186 U JP 18305186U JP S6387860 U JPS6387860 U JP S6387860U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating sheet
- wiring
- integrated circuit
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007747 plating Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Description
第１図は本考案の一実施例の配線基板の縦断面
図、第２図は従来例の配線基板の縦断面図である
。
１……絶縁シート、２……第１層目導体、３…
…第２層目導体、４……搭載ペレツト、５……ボ
ンデイングワイヤ、６……マウント剤、３１……
面状配線、３２……密配線。
FIG. 1 is a vertical sectional view of a wiring board according to an embodiment of the present invention, and FIG. 2 is a vertical sectional view of a conventional wiring board. 1... Insulating sheet, 2... First layer conductor, 3...
...Second layer conductor, 4... Mounting pellet, 5... Bonding wire, 6... Mounting agent, 31...
Planar wiring, 32...Dense wiring.
Claims (1)
りそれぞれ第１層および第２層の各導体パターン
を形成した混成集積回路用配線基板において、前
記第２層の導体パターンが部分的面状配線あるい
は密配線で覆い前記絶縁シートの露出面積を少く
することにより、前記第１層の導体パターン面の
凹凸をなくしたことを特徴とする混成集積回路用
配線基板。 In a wiring board for a hybrid integrated circuit in which conductive patterns of a first layer and a second layer are respectively formed on the front and back surfaces of an insulating sheet by plating or the like, the conductive patterns of the second layer are partially planar wiring or dense wiring. A wiring board for a hybrid integrated circuit, characterized in that unevenness on the surface of the conductive pattern of the first layer is eliminated by covering the insulating sheet with a thin film to reduce the exposed area of the insulating sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18305186U JPS6387860U (en) | 1986-11-27 | 1986-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18305186U JPS6387860U (en) | 1986-11-27 | 1986-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6387860U true JPS6387860U (en) | 1988-06-08 |
Family
ID=31129427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18305186U Pending JPS6387860U (en) | 1986-11-27 | 1986-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6387860U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016122758A (en) * | 2014-12-25 | 2016-07-07 | イビデン株式会社 | Multilayer wiring board |
-
1986
- 1986-11-27 JP JP18305186U patent/JPS6387860U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016122758A (en) * | 2014-12-25 | 2016-07-07 | イビデン株式会社 | Multilayer wiring board |