JPS6387808A - Chirp signal generating circuit - Google Patents

Abstract

PURPOSE:To widen the band of a chirp signal into N multiple by providing a 1/N counter applying 1/N frequency division to a clock signal, a real part delay circuit group and an imaginary part delay circuit group or the like so as to divide the real and imaginary part signal waveform of a chirp signal into 1/N thereby increasing the sample frequency up to N multiple. CONSTITUTION:A clock signal generator 1 generating a clock signal, a 1/N counter 2 applying 1/N frequency division to the clock signal, storage devices 4, 5 storing N kinds of real part series and imaginary part series corresponding to each other, real part delay circuit group and imaginary delay circuit group 6, 7 retarding the series by one sample each according to the sequence in the partial series and a band pass filter 21 eliminating the harmonic modulation component included in an output signal of a synthesizer to output a required chirp signal or the like are provided. Since the real part signal waveform and the imaginary signal waveform of the chirp signal are divided by 1/N respectively, the operating speed of the storage devices 4, 5 is brought into 1/N and it is possible to increase the sample frequency into N multiple, resulting that the band of the chirp signal is widened by N times.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is applicable to various radar transceivers such as chirp modulators for synthetic aperture radar, and FDM-T using chirp Z conversion.
The present invention relates to a chirp signal (frequency sweep signal) generating circuit that is widely used in fields such as DM communications and frequency analyzers such as spectrum analyzers.

(Prior art) Chirp signals (frequency sweep signals) are currently used in fields such as transmitters and receivers of various radars including synthetic aperture radar, and frequency analyzers such as spectrum analyzers. The chirp signal to be used is required to have extremely high precision, high stability, and good characteristics over a wide band.

Currently, chirp signal generation methods widely used include methods using surface acoustic wave (SAW) delay line filters and
There are methods to vary the oscillation frequency of CO, but the former involves SA
It is difficult to obtain a chirp signal with good characteristics due to signal deterioration due to insertion loss of the W element, variations in frequency characteristics, etc., and in the latter case, problems such as nonlinearity of the output frequency of the vCO.

In order to deal with this problem and satisfy the above-mentioned requirements, a digital chirp signal generation method has been proposed, as shown in section 5, and has been put into practical use to some extent.

In FIG. 5, 1 is a clock signal generator, 3 is an address counter, and 22 and 23 are R's in which the real part signal waveform and imaginary part signal waveform of the chirp signal are respectively written in digital form.
OM, 10.11 is a latch circuit, 12.13 is a D/A converter, 16 is a carrier wave generator, 17 is a π/2 phase shifter, 18
．． 19 is a mixer, and 20 is a synthesizer.

The operation of this conventional chirp signal generating circuit is roughly as follows. That is, one real part ROM 22 and one imaginary part RO are accessed by the address counter 3.
The output digital signal of M23 is sent to D/A converter 12,
3, the signal is converted into a baseband real part sweep signal and an imaginary part sweep signal, respectively.

Then, in the mixer 18, the intermediate frequency band carrier wave (that is, the output of the carrier wave generator) is single-sideband modulated by the output (real part sweep signal) of the D/A converter 12, and in the mixer 19, π
/2 shifted carrier wave is single-sideband modulated by the output (imaginary part sweep signal) of the D/A converter 13, and the outputs of both mixers are combined in the combiner 20 to obtain a chirp signal in the intermediate frequency band. It has become. According to this method, a chirp signal with high accuracy, high stability, and good characteristics can be obtained.

(Problems to be Solved by the Invention) When a chirp signal is generated digitally, the band of the chirp signal is limited to one-half or less of the sampling frequency as indicated by Nyquist's sampling theorem.

Therefore, in order to widen the band of the chirp signal, it is sufficient to increase the sampling frequency, and each circuit element is required to operate at higher speed.

Due to recent advances in device technology, D/A converters that operate at considerably high speeds have appeared.
As for ROM, we cannot expect a ROM with much faster access and larger capacity than the current one.

In other words, in the conventional Char-1 signal generation circuit described above, R
The access time and storage capacity of the OM become obstacles, and the bandwidth of the chirp signal that can be generated is limited to several tens of M it z. Therefore, its use is limited and it lacks versatility.

The present invention was made in view of these problems, and an object of the present invention is to provide a chirp signal generation circuit that can generate a chirp signal with high precision and a wide band.

(Means for Solving the Problems) In order to achieve the above object, the chirp signal generating circuit of the present invention has the following configuration.

That is, the chirp signal generation circuit of the present invention includes: a clock signal generator that generates a clock signal with a predetermined sampling frequency; a 1/N counter that divides the clock signal by N; and a real part of a frequency sweep signal (chirp signal). Regarding the signal waveform and the imaginary part signal waveform, N types of real part series and N types of imaginary part part series, which are sampled every N sample periods with a time shift of 1 sample time for each in advance, are stored in association with each other. a storage device; the storage device is accessed by counting the clock signal frequency-divided by the 1/N counter, and each of the N types of real subsequences and N types of imaginary part subsequences are stored in parallel; Address counter to be output;
a real part delay circuit group and an imaginary part delay for delaying each signal of the N types of real part sequences and the N types of imaginary part parts sequences, which are outputted in parallel by the storage device, by one sample according to the order in the partial sequences; a circuit group; a real part adder that adds each output of the real part delay circuit group; and an imaginary part adder that adds each output of the imaginary part delay circuit group; and converts the output of the real part adder into analog. an imaginary part D/A converter that converts the outputs of the real part D/A converter and the imaginary part adder into analog signals; and the respective outputs of the real part D/A converter and the imaginary part D/A converter. A real low-pass filter and an imaginary low-pass filter that remove signals outside the desired band from the signal; and a carrier generator that generates a carrier wave of a predetermined frequency that is to be swept at a constant rate of change (chirve rate). a π/2 phase shifter that shifts the frequency of the single-shell transmission by π/2; a real part mixer that modulates the carrier output of the carrier generator with the output of the real part low-pass filter; an imaginary part mixer that modulates the output of the phase shifter with the output of the imaginary part low-pass filter; and a synthesizer that combines the outputs of the real part mixer and the imaginary part mixer to form a single sideband modulation signal. A chirp signal generation circuit comprising: a bandpass filter that removes harmonic modulation components contained in the output signal of the synthesizer and outputs a desired chirp signal.

(Function) Next, the function of the chirp signal generation circuit of the present invention configured as described above will be explained.

The clock signal generator generates a clock signal at a predetermined sampling frequency. The 1/N counter is at the front.

The clock signal is frequency-divided by N and output to the address counter. On the other hand, in the storage device accessed by the address counter, the real part signal waveform and the imaginary part signal waveform of the frequency sweep signal (chirp signal) are stored in advance at N sampling periods, with the time shifted by 1 sample time each. The real subsequences of the species and the imaginary subsequences of the N species are stored in correspondence with each other. A ROM is used as this storage device from the viewpoint of access time.

Further, from the viewpoint of storage capacity, the storage device may use 2N independent ROMs, or the storage area may be allocated to one or a required number of ROMs smaller than 2N.

The address counter accesses the storage device by counting the clock signal frequency-divided by the 1/N counter, and reads each of the N types of real subsequences and N types of imaginary part subsequences in parallel. Output to real part delay circuit group and imaginary part delay circuit group.

The real part delay circuit group and the imaginary part delay circuit group convert the signals of the N types of real part sequences and the N types of imaginary part partial sequences outputted in parallel by the storage device into one signal according to the order in the partial sequences. Delay by sample. The real part adder and the imaginary part adder add respective outputs of the corresponding real part delay circuit group and the imaginary part delay circuit group. The real part D/A converter and the imaginary part D/A converter analogize the outputs of the corresponding real part adder and the imaginary part adder.

The real part low-pass filter and the imaginary part low-pass filter have the real part D/
A desired out-of-band signal is removed from each output signal of the A converter and the imaginary part D/A converter. Further, the carrier wave generator generates a carrier wave of a predetermined frequency that is to be swept at a constant rate of change (chirp rate). The π/2 phase shifter is
The frequency of the carrier wave is phase-shifted by π/2.

The real part mixer modulates the carrier wave output of the carrier wave generator with the output of the real part low-pass filter.

On the other hand, the imaginary part mixer modulates the output of the phase shifter with the output of the imaginary part low-pass filter.

Then, the combiner combines the respective outputs of the real part mixer and the imaginary part mixer to form a single sideband modulated signal. Finally, a bandpass filter removes harmonic modulation components contained in the output signal of the synthesizer and outputs a desired chirp signal.

As described above, according to the chirb signal generation circuit of the present invention, the real part signal waveform and the imaginary part signal waveform of the frequency sweep signal are each divided into N parts, so that the operating speed of the storage device can be reduced to 1/N. Therefore, it is possible to increase the sampling frequency by N times, and as a result, the band of the chirp signal can be expanded by N times. Further, there is an effect that it is possible to generate a chirp signal with a high chirp rate.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure shows a chirb signal generation circuit according to an embodiment of the present invention. In FIG. /N counter), 3 is an address counter, 4.5 is N ROMs (# 1
~ #N), 6.7 is a delay circuit group, 8゜9 is an adder, 10.11 is a latch circuit, 12.13 is a D
/A converter, 14.15 is a low-pass filter, 16 is an intermediate frequency carrier generator, 17 is a π/2 phase shifter, 18.19 is a mixer for single sideband modulation, and 20 is a combiner. , 21 are bandpass filters.

In such a configuration, the clock signal generator 1 generates a clock signal with a predetermined sampling frequency and divides it into 1/
It is applied to the N counter 2 and the latch circuits 10 and 11.

The 1/N counter 2 divides the clock signal by N and supplies it to the address counter 3.

The address counter 3 counts the clock signal frequency-divided by the i/N counter 2 to count the N real part ROMs (#1 to #N) of the ROM group 4 and the N imaginary part ROMs of the ROM group 5.
(#1 to #N) are accessed in a time-division manner, and the contents are output in parallel to each ROM in ROM groups 4 and 5.

Kokote, N real part ROMs (#1 to #N) of ROM group 4
N types of waveform data (real part partial series) obtained by shifting the real part signal waveform of a frequency sweep signal (chirb signal) by one sample time and sampling it every N sample periods are stored in advance in correspondence with each other. be. That is, N types of waveform data are stored in real part ROM #1 . The real part ROM #2, . . . , real part ROM #N are stored in order.

Similarly, 4:
m ROM group '17) N imaginary part ROMs (#1 to #N)
It is stored in advance.

Delay circuit groups 6 and 7 are connected to each RO of ROM groups 4 and 5.
The waveform data outputted by M in parallel is delayed by one sample time according to its sample order.

Adder 8 adds the outputs of delay circuit group 6 to form a digital real part signal, and sends it to latch circuit 10 .

Further, the adder 9 adds the outputs of the delay circuit group 7 to form a digital imaginary part signal, and sends it to the latch circuit 11.

Since the latch circuit 10 latches the digital real part signal according to the clock signal and sends it to the D/A converter 12, the digital real part signal is converted into a baseband analog real part signal by the D/A converter 12. Ru. This analog real part signal is input to the mixer 18 after being subjected to processing for removing signals outside the desired band in the low-pass filter 14 . FIG. 3 shows the waveform of the output (baseband real part signal) of the low-pass filter 14.

The latch circuit 11 latches the digital imaginary part signal according to the clock signal and sends it to the D/A converter 13, so that the digital real part signal is converted into an analog real part signal by the D/A converter 13.

This analog real part signal is input to the mixer 19 after being subjected to processing for removing signals outside the desired band in the low-pass filter 15 . Fourth
The figure shows the waveform of the low-pass filter output (baseband imaginary part signal).

The mixer 18 modulates the intermediate frequency band carrier directly inputted from the carrier wave generator 16 with the output of the low-pass filter 14, that is, the analog real part signal, and supplies it to one input of the synthesizer 20. Further, the mixer 19 passes the carrier wave whose phase has been shifted by π/2 input from the π/2 phase shifter 17 to a low-pass filter 15.
, the analog imaginary part signal, and feeds it to the other input of the combiner 20.

The combiner 20 combines the outputs of the mixers 18 and 19,
A single sideband modulated signal is formed and sent to bandpass filter 21.

The bandpass filter 21 removes the harmonic modulation component of the carrier included in the output signal of the combiner 2o, and outputs a desired chirped signal.

Next, FIG. 2 shows another embodiment of the present invention.

In this second embodiment, as is clear from FIGS. 3 and 4, the capacity of the storage device is reduced by focusing on the fact that the waveform of the baseband sweep signal is symmetrical. . That is, the chirp signal generation circuit according to the second embodiment includes an up/down address counter 24 instead of the address counter 3, and a decoder 25;
Selector groups 30 and 31 are added.

The decoder 25 decodes the output of the up/down address counter 24 and switches between up counting and down counting.

The ROM groups 26 and 27 each contain waveform data of one half of the real part signal waveform and the imaginary part signal waveform of the frequency sweep signal.
It is divided into partial series and written in the same manner as in the embodiment. The delay circuit groups 28 and 29 are each provided with delay circuit groups for up-counting and for down-counting, and selector groups 30 and 31 select one of the outputs.

(Effects of the Invention) As detailed above, according to the chirp signal generation circuit of the present invention, the following effects can be expected.

(1) By dividing the real part signal waveform and imaginary part signal waveform of the frequency sweep signal by N, the operating speed of the storage device is reduced to 1/N.
Therefore, it is possible to increase the sampling frequency up to N times, and as a result, it is possible to widen the band of the chirp signal by N times. Furthermore, it is possible to generate a chirp signal with a high chirp rate.

(2) By setting the sampling frequency to at least twice the band, it is possible to generate a highly accurate chirb signal.

(3) It is also possible to improve accuracy and reduce quantization noise by dividing the 2N types of waveform data of the real part signal waveform and imaginary part signal waveform divided into N into upper bits and lower bits and writing them to the storage device. be.

(4) Accurate chirp signal generation is possible by using a stable lock signal generator and carrier wave generator.

(5) Since it is a digital chirp signal generation circuit, it is highly flexible in terms of design, and the system can be miniaturized with low power consumption.

The chirp signal generation circuit according to the present invention has the above-mentioned characteristics, and can be used in various radar transceivers such as chirp modulators of synthetic aperture radar, and FDM using chirp Z conversion.
- It is possible to provide a highly versatile chirp signal generation circuit that can be widely applied to fields such as TDM communications, frequency analyzers, and measuring instruments such as spectrum analyzers and sweepers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a chirp signal generation circuit according to one embodiment of the present invention, FIG. 2 is a block diagram of a chirp signal generation circuit according to another embodiment of the present invention, and FIGS. 3 and 4 are respectively , a baseband real part signal waveform, a baseband imaginary part signal waveform, and FIG. 5 is a block diagram of a conventional chirp signal generation circuit. 1... Clock signal generator, 2...
1. /N counter, 3...Address counter, 4.5...ROM group, 6.7...
Delay circuit group, 8.9... Adder, 10.11.
...Latch circuit, 12.13...D/A
Converter, 14.15...Low pass filter, 16
...Carrier wave generator, 17...π/2 phase shifter, 18.19...Mixer, 20...
... combiner, 21 ... bandpass filter, 24.
...Up-down address counter, 25...
...Decoder, 26.27...ROM group,
28.29...Delay circuit group, 30.31...
...Selector group.

Claims (1)

[Claims] A clock signal generator that generates a clock signal of a predetermined sampling frequency; A 1/N counter that divides the clock signal by N; A real part signal waveform and an imaginary part signal waveform of a frequency sweep signal (chirp signal) are each N sampled every N sample period by shifting the time by 1 sample time
a storage device that stores each of the real part subsequences of the species and the imaginary part subsequences of the N kinds in association with each other; accessing the storage device by counting the clock signal frequency-divided by the 1/N counter; an address counter that outputs each of the N types of real part sequences and the N types of imaginary part partial sequences in parallel;
A real part delay circuit group and an imaginary part that delay each signal of the N types of real part subsequences and the N types of imaginary part subsequences, which are outputted in parallel by the storage device, by one sample time according to the order in the subsequences. a delay circuit group; a real part adder that adds each output of the real part delay circuit group; and an imaginary part adder that adds each output of the imaginary part delay circuit group; and converts the output of the real part adder into analog. a real part D/A converter for converting the outputs of the real part D/A converter and an imaginary part D/A converter for converting the outputs of the imaginary part adder into analog; outputs of the real part D/A converter and the imaginary part D/A converter; real and imaginary low-pass filters that remove out-of-band signals from the signal; constant rate of change (
a carrier wave generator that generates a carrier wave of a predetermined frequency that is to be swept at a chirp rate);
a π/2 phase shifter for shifting the phase by /2; a real part mixer for modulating the carrier output of the carrier generator with the output of the real part low-pass filter; an imaginary part mixer that modulates the output of the band pass filter; a combiner that combines the outputs of the real part mixer and the imaginary part mixer to form a single sideband modulated signal; a bandpass filter that removes modulation components of the wave and outputs a desired chirp signal;
A chirp signal generation circuit comprising: