JPS6382168A - Magnification system for picture data - Google Patents

Abstract

PURPOSE:To attain magnification by means of real time processing by controlling an address of a line memory based on magnification information from a magnification control memory at data read (write) from (to) the line memory at magnification (reduction). CONSTITUTION:The address of line memories 5, 6 is controlled based on magnification information from a magnification control memory 8 at the data read from the line memories 5, 6 at magnification. In case of the reduction, the address of the line memories 5, 6 is controlled based on the magnification information from the magnification control memory 8 at the data write to the line memories 5, 6. That is, the data is corrected at read from the line memories 5, 6 at magnification and the data is corrected at write to the line memory in case of reduction, the data is read/written alternately at each scanning line from/to 1st and 2nd line memories 5, 6, and when the one is in the read mode, the other is in the write mode. This is controlled by using a magnification/ reduction signal (i) and an even/odd number line signal (p).

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a scaling method for image data, and more specifically,
The present invention relates to an image data scaling method that can be applied to digital copying machines, facsimiles, image scanners, image editing systems, etc., which scales digitized image data through digital logic processing.

(Prior art) Conventional scaling methods for image data in digital image processing devices, etc. include optical scaling, binary image thinning, insertion-based scaling, and scaling using an interpolation function (table method). calculation) etc. are adopted. However, among these variable magnification methods, the optical variable magnification method has mechanical structural reasons,
That is, it is difficult to vary the magnification over a wide range due to the size of the device and optical reasons, such as the brightness of the light source and the blur of the image. Further, scaling methods based on thinning and insertion of binary images have drawbacks such as large distortion of image data and poor scaling accuracy. Furthermore, although the scaling method using an interpolation function can handle several types of fixed scaling, it is difficult to handle a wide range of scaling with arbitrary scaling factors.

(Objective) The present invention has been made in view of the drawbacks of the above-mentioned prior art.
The purpose is to electrically change the magnification of digital image data at any magnification using a simple hardware configuration.
It is an object of the present invention to provide a method for changing the magnification of image data that enables scaling over a wide range with high accuracy and by real-time processing synchronized with an input device or an output device.

(Structure) In order to achieve the above object, the present invention provides an image data scaling system including a line memory having a capacity for at least one main scanning line and a scaling control memory storing scaling control information. When enlarging and reducing image data in the main scanning direction, the address of the line memory is controlled based on the scaling information from the scaling control memory when reading data from the line memory during expansion, and then the scaling is performed. When data is written to the line memory, the address of the line memory is controlled based on scaling information from the scaling control memory.

Further, the present invention provides an image processing system that includes a line memory having a capacity for at least one main scanning line, a scaling control memory in which scaling control information is stored, and a data correction section that corrects data during scaling operation. In the data scaling method, when enlarging image data, a read address from the line memory is controlled based on scaling information from the scaling control memory, and at the same time, read data from the line memory is sent to the data correction section. and when reducing image data, the output data from the data correction section is written into the line memory, and this write address is controlled based on scaling information from the scaling control memory. This is what I did.

Furthermore, the present invention includes a line memory having a capacity for one main scanning line and a scaling control memory in which scaling control information is stored; In the image data scaling method, the address of the line memory is controlled when reading data from the line memory during enlargement, and when writing data to the line memory during reduction, based on scaling information from the image data. The present invention is characterized in that two line memories are provided, and the operation modes of these line memories are alternately switched for each main scan, so that when one is in a read mode, the other is in a write mode.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

The present invention relates to a method for two-dimensionally varying the magnification of digitized image data by digital small logic processing. Image data divided into pixel units in the main scanning direction and the sub-scanning direction are arranged in time series in pixel units within one main scan. Furthermore, in the sub-scanning direction, image data is input as first main-scanning data, second main-scanning data, third main-scanning data, etc. arranged in time series in units of main-scanning lines, The number of pixels in the main scanning direction is scaled at a desired magnification and output as new image data. At this time, the input and output have a certain synchronous relationship, and this is so-called real-time processing.

Here, concepts such as pixels, image data, main scanning, sub-scanning, etc. will be explained with reference to FIGS. 1 and 2. In FIG. 1, one image consists of pixels Pij (i = 0.1, 2 .
----n,j =0.1,2. --n), and the set Po, P+ of pHll ~ Pa1l.

~P1. set P+, set Pto~I)2, set PZ
, "-"'- are image data within one main scan, respectively. Hereinafter, for convenience, each main scanning line is shown in FIG. 1 in order in the sub-scanning direction <0, 1, 2, --m--
-n will be added and will be referred to as the 0th line, the 1st line, and the 2nd line---1-1.

FIG. 2 is a time chart of signals corresponding to FIG. 1, where LSYNC is a main scanning synchronization signal (or line synchronization signal or simply called synchronization signal), and P is whether the main scanning line is an even-numbered line or an odd-numbered line. A signal indicating whether the line is a line (P-I, '' for an even line), and a is an image data signal read from FIG.

PetPI and P2 in the image data signal a are Pa in FIG.
, P+, Pg, and more specifically, the signal a is a signal divided into pixel units within each of Pet p, , Pg.

Next, an embodiment of the image data scaling method according to the present invention will be described with reference to the block diagram of FIG. In the figure, 1 is a first selector, 2 is a data correction section, 3 is a third selector,
4 is a second selector, 5 is a first line memory, 6 is a second line memory, 7 is a fourth selector, 8 is a scaling control memory, and 9 is a memory controller. Further, signal a in FIG. 3 is input image data and has density information of 6 bits and 64 gradations. The signal d is output image data and also has density information of 6 bits and 64 gradations.

The signal i is a signal indicating whether the magnification is enlargement or reduction, and when it is enlarged (including the same size), i = 'H'', and when it is reduced, i = 'L''.

The signal j contains information necessary for performing the scaling process, and is set in the scaling control memory 8 by a central processing unit (CPU, not shown). This set of scaling information by the CPU is set in advance prior to the scaling operation of image data.

In the signal, β is a signal for scaling control which is supplied to the data correction section 2 and the memory controller 9 during scaling operation based on the set signal j.

Signals m and n are sent to the first and second line memories 5 and 5, respectively.
6 control signals, which are address signals, read, and write control signals.

The signal P is a signal indicating whether the main scanning line is an even number or an odd number, as in FIG. The signal CLK is a clock signal for each pixel.

Also, the signals c, e, f, g,
h are the first selector 1, data correction section 2, second selector 4, fourth selector 7, first line memory 5, and second line memory 5, respectively.
These are the outputs of the line memory 6, and they are image data. Of course, all of these also have density information of 6 bits and 64 gradations.

Although the setting of magnification information in advance into the magnification control memory 8 will be described later, an outline of the operation of the configuration shown in FIG. 3 during the magnification change operation will be explained with reference to FIG. 4. As shown in FIG. 4, this operation is roughly divided into four operating modes: even-numbered lines and odd-numbered lines during enlargement, and even-numbered lines and odd-numbered lines during reduction. In the figure, the RD mode and W in the columns of the first and second line memories 5.6
T mode represents read mode and write mode, respectively.

For example, for even-numbered lines during enlargement, the first line memory 5
is in the RD mode, the second line memory 6 is in the WT mode, and the input signal a to FIG.
→ f → second line memory 6 on the path of second line memory 6
will be written to. In parallel with this operation, the read data from the first line memory 5 is changed from the first line memory 5 → g → fourth selector 7 - first selector 1 - b → data correction unit 2 -
h It is output through the path of C-third selector 3→d.

In the next scan, since it is an odd number line, the RD and WT modes of the first and second line memories 5.6 are reversed, and the input signal a is changed from a to second selector 4→f to first line memory. 5, while parallel to this operation,
The read data of the second line memory 6 is as follows: second line memory 6-h→fourth selector 7-e→first selector lb→
It is output through the path of data correction section 2→C→third selector 3→d. At this time, the data read from the second line memory 6 is the data written to the second line memory 6 during the previous even-numbered line. Similarly, the data written in the first line memory 5 in the current line is read out at the next even numbered 17:00, and is output as a signal d after passing through each path.

The above is the operation during enlargement, but the person on duty will similarly understand the operation during reduction from FIGS. 3 and 4.

In other words, the above operation can be expressed as follows. That is, (1) When enlarging, data is corrected when reading from the line memory, and when reducing, data is corrected when writing to the line memory.

(2) The first and second line memories perform read and write operations alternately for each scanning line, and when one is in the read mode, the other is in the write mode.

(3) Expansion/reduction signal i and even/odd line signal p
Accordingly, the above (11, +21) is controlled.

The outline of the operation of the configuration shown in FIG. 3 has been explained above, focusing on the flow of image data. Since the above description hardly mentions where and how the scaling is performed, the following explanation will focus on scaling and will focus on the configuration and operation of each block in FIG. 3 in detail.

FIG. 5 is a time chart schematically showing the input signal a of FIG. 3 corresponding to the vicinity of the position on the main scanning line. In this chart T.

indicates a pixel unit, and corresponds to one cycle of the signal CLK in FIG. 3. The vertical axis corresponds to the density level of 6 bits - 64 gradations.

Now, as shown in Fig. 5, the input image data has a pixel pitch indicated by ○ marks T, and a density level of A,, A2+A3+"-.
-・Ah. Consider enlarging the image shown in FIG. 5 in the main scanning direction, with a pixel pitch of T. For the sake of simplicity, let us take, for example, 250% enlargement as shown in FIG.

That is, in Fig. 6, mark O and A2, Az, A
4・-m---- is A2, A3, Aa in Figure 5
-"-, and has been expanded by 2.5 times in the scanning direction.

On the other hand, the Δ mark is the pitch T1, and B21+B tt
+B21 B21...- is the density level at each point. At this time, B21. B2□, B2s, Bx□・-
・- is A2. This is variable-magnification image data for A3, A4---'-, and the positional relationship between A and B, that is, the O mark and the Δ mark, and the density level between A and B have a certain relationship.

For example, in Fig. 6, if A has a period of 2.5T and B has a period of T1, and A2 and 13g+ match, then the following A
, B are uniquely determined.

Further, the density level of B is calculated, for example, by the so-called "neighboring pixel distance linear distribution method", which is determined based on the levels of two adjacent A's and the distance to A's.

In the example of FIG. 6, for example, B2□ is the front and rear A2. From A, it is found by .

FIG. 7 is a reduced example of FIG. 5, and shows an example where the magnification is 70%. In Figure 7, the pitch of A is as marked O (0, 7
T+, and the pitch of B after scaling is T1, as shown by the Δ mark, the same as A before scaling (FIG. 5). In this case too,
As in the case of enlargement, the positional relationship between the O mark and the Δ mark and the A
The concentrations of and B are determined by a certain relationship.

For example, in Figure 7, the level of B2 is r, +r.

It is determined by

As described above, if the scaling factor is given, it is possible to determine the positional relationship between data A before scaling and data B after scaling, and from that positional relationship and data A before scaling. It is possible to determine the density level of data B after scaling.

To explain this in relation to FIG. 3, it is the magnification control memory 8 that stores information on the positional relationship between A and B, and sends out this information as necessary.
22. The data correction section 2 determines the level of B by calculations such as and B2.

Furthermore, as is clear from FIGS. 6 and 7, depending on the magnification ratio and pixel position, there is a Δ
There are various cases, such as cases where there is no mark at all, cases where there is only one mark, cases where there are only two marks, etc. Of course, this relationship is also a positional relationship, and is determined by a given magnification ratio.

In this way, whether there are no Δ marks or how many there are is the third question.
This is an extremely important matter for the operation of the figure, and is given to the memory controller 9 as a signal β, and used for address control of the first, second and second line memories 5.6.

Next, a specific example of the positional relationship on the 1y axis before and after zooming will be described.

Xfi corresponding to the scaling factor α (%) indicates the position of the data after scaling relative to the data before scaling. In other words, it indicates a new sampling point for scaling when the data signal sampling pitch before scaling is 1. Here, the constant corresponds to the phase difference between new and old sampling or the initial value, and is set to =O for NIL.

That is, the position of the first data is made to match before and after scaling. Here, α α
Given the scaling factor α, 100/α, and hence Xl, can be easily determined in the CPU by calculation or a read-only memory (ROM) table.

Furthermore, the magnification ratio α (%) is, for example, 50% to 1000%.
In the case where it is set in 1% increments within the range, it can be expressed as.

That is, α indicates the number of sampling points after scaling with respect to 100 sampling points before scaling, XI has information on the number relationship and positional relationship of the sampling points before and after scaling, and For parts with 100 or more previous sampling points, it is sufficient to consider similar repetition every 100 points.

Therefore, in the above case, the number of n is most often α-1000%, and n=1000.

Next, the properties of X11 will be explained in more detail. X
ゎ is the integer part■. , decimal part, 0 according to I7, x, = r i + J.

Here ■. is the number of sampling points before and after scaling,
Further, J9 indicates position information of sampling points before and after scaling.

For example, at the time of enlargement (72100%), ΔT, -1.
-1.1 (However, △In-+-0) △■7 indicates whether or not there is a sampling point before scaling between sampling points n-1 and n after scaling, △■7- 0 indicates absence, and 1 indicates presence.

For example, in FIG. 6, there is A between B2□ and 823.
Since there is no, Δl1l=0, and since A3 exists between l3zs and B31, it corresponds to Δl7-1.

On the other hand, J,, for example, B2□ and A2 in FIG.
It has information regarding the positional relationship r1 (therefore rz) with A.

Even when reduced (α<100%), △1. =1. ．． T,,-+ (However, ΔI,,-
+=1), △Il, represents the presence or absence of sampling points before and after scaling, but in the case of reduction, 100/α, where t<100/α≦2 (50%≦α<100%), . increases, so the value of △Ill also increases △
I, -1 or 2, sampling point n-1 after scaling
There is one sampling point before scaling between and n, or 2
If △rll-i, there is one, △1. If = 2, there are two, which indicates.

For example, in FIG. 7, there is one A3 between B2 and B, so it corresponds to Δi,=i, and there are two sampling points, A4 and As, between B3 and B. Because there is △
I, corresponds to l=2.

On the other hand, regarding J, the positional relationship is shown even when reduced, and for example, in FIG. 7, it has information regarding "1 (therefore rz).

△lI is information related to the number of sampling points during both enlargement and reduction, but in order to simplify the hardware, especially during reduction, △ln = 2 is decomposed into two, and △ Ifi, ==0, △Inz-1.

Through this transformation, both enlargement and reduction are possible. If △I, l = 0, there is no Yes, if △l1l=1, It can be treated as

△I, ,=O or 1 for the first and second in FIG.
The above modification leads to hardware simplification in order to control the increment of addresses in the line memories 5 and 6.

From the above, using n-α pieces for expansion and n=100 pieces for reduction, △I, l (=0 or 1),
Data on the number of sampling points for scaling in 1% increments from α-50% to 1000% is obtained.

Next, the decimal part Jll of X, l=Iゎ+J, will be explained. From its definition, J7 means Jn = rI/ (r+ +j,) in FIGS. 6 and 7.

Here, in order to simplify the hardware, Jll is divided into four ranks according to its value, and the four ranks are distinguished by two bits of , , Kg, and ? 0 In addition, in correspondence to each rank, the density B2 of the sampling point after scaling is changed to the sampling points At on both sides before scaling,
Correspond to As as shown in the table below.

Jll rank +Kg B*0 ≦J
ll<0.25 1 0 0 Axo, 25≦JIl
<0.5 2 0 1 At(3/4)+As(1/
4) 0.5≦Jll<0.75 3 1 OA, (
1/2)+A3(1/2)0.75≦Jll<1
4 1 1 7h (1/4) + ^3 (3/4) With the above, the scaling information of Xn = I + J, l is expressed by 3-bit digital logic data of △I, l, +, Kz be done.

Note that the calculation of the value of B in the above table is performed by the data correction section 2 shown in FIG.

Each △1. Each time, Kl and Ki are attached, respectively, and 3 bits yields α (when enlarging) or 100 (when reducing) scaling data strings, but since the data is repeated every α or 100 pieces, n=α+1 or n-100+1
In this case, it is necessary to restart from n-1, and to indicate this, 1 bit is allocated and designated as K4. That is, K4 is n=1 to α-1 (when expanded) or n=l to 9
9 (when reduced) Kg -0, n-α-1 or n-1
4=1 only when 00.

The above four bits of 4 for Δ[-, KI, Kg, and 4 are the contents of the scaling data j given to the scaling control memory 8 from the outside in FIG.

Although the principle of scaling and the content of scaling data have been clarified through the explanations so far, each block of the configuration shown in FIG. 3 will be explained in detail below.

FIG. 8 is a circuit diagram showing the internal logic of the variable magnification control memory 8 of FIG. In the figure, 10 to 13 are latches,
14 is random access memory (RAM), 15-1
7 is a gate, 1B is a selector, 19 is an address counter, and 20 to 25 are gates.

The RAM 14 is a memory in which scaling data given as a signal j from the outside is stored, and the number of pieces of data is cx-1.
000% (n=α=1000), and its capacity is 4×100 bits. Therefore, 40
For RAM with 00 bits or more, 1% from 50% to 1000%
This is sufficient to store scaled data in increments. For example, 200
%, only 4×200 bits are effectively used.

In FIG. 8, the signal DLT is a clock signal for taking in the variable magnification data j, and the signal DLT is also sent out in synchronization with the sending out of the signal j from the outside.

In addition to the 4-bit modified data, the signal j also has 1-bit data. This is the first data of the variable magnification data, that is, data indicating the timing of n-1, and the address of the RAM 14 is set to address O by this signal. More specifically, this bit data is logical -#1" only when n=1, and is 0 for other n. When it is #1", the address counter 19 for the RAM 14 Reset.

Of the variable magnification data J taken into the latch 10, this start bit clears the address counter 19 via the gate 20.degree.22 as a signal j2.

Signal DST indicates that the mode is in which variable magnification data J is received and stored in RAM 14. When storage is complete, ■
Y lower becomes level #H".

The signal DWT is a signal for writing into the RAM 14, and the clock signal CLK is a clock signal used when reading variable-magnification data from the RAM 14, that is, when actually performing a variable-magnification operation.

Selector 18 selects signal DLT or clock signal CL.
K is selected and address counter 19 is incremented.

That is, when storing the signal j in the RAM 14, the address counter 19 is cleared by the signal j, and then counted up by the signal DLT. Signal j, along with the address sidewalk.

j3 is input and written into RAM 14 via latch 10.11. When the amount corresponding to n-α or n”100 is written, the signal becomes 11 completed-H#,
Writing to RAM 14 is completed. This write operation will be explained using the time chart of FIG. Also, the first
FIG. 0 is a time chart illustrating the operation of FIG. 8 in a mode in which variable-magnification data is read from the RAM 14 for variable-magnification operation.

In FIG. 10, during reading, address counter 19 is incremented by signal CLK from selector 1814.

The signal CLK is also a pixel clock for image data to be scaled.

At the time of reading, the RAM 14 enters the read mode when DST='H.'DWT also becomes 'H', and the output of the latch 11 becomes a high impedance state. Therefore, the output signal from the RAM 14 appears as the signal j.

The addresses advance one after another, and the signal ADR-α-1 (n=α
FIG. 10 shows the timing around when the signal ADH reaches 0 (corresponding to 0) and steps again from the signal ADH=0. The contents of signal j, (α-4) and (α-3)-1 are the address α-, respectively.
4. This is the meaning of the variable magnification data corresponding to α-3------.

In particular, in signal ADR-α-1, j in signal j3
4-"1#. This signal j4 is the end bit of the variable magnification data, and this signal j4 clears the address counter 19 via the gates 21 and 22. When the address counter 19 is cleared, , the signal ADH becomes O,
The ADH is incremented again as ADH=0.1.2-.-.

The signal l is output from the latch 12 as one bit in the signal j3, and this signal l corresponds to the bit ΔIn in the scaled data j. Although ΔI and l were originally sampling number information, it is easier to understand the signal β if it is considered as a count control signal for scaling. That is, the counting of addresses in the line memory for scaling is controlled on/off based on this signal l.

Of the outputs of the latch 13, the signal Kz, 3 corresponds to 2 bits, , , , and 3, respectively, indicating the rank of the sampling position data in the scaled data j. That is, if only the logic is considered, ignoring the time difference between writing and reading and the difference in signal form.

The signal is a signal created from the signal l and CLK, and the data correction unit 2 is synchronized with the count-on/off control signal l.
This is a signal for controlling the flow of data in (Fig. 3).

FIG. 11 shows the signal CLK, 12. K+, Kt
, Kz is a timing chart showing the timing.

FIG. 12 is a circuit diagram of the internal logic of the data correction section 2 of FIG. 3. In the figure, 26 is a latch, 27 is a selector, 2
8, 29, and 30 are adders, and 31 is a selector.

The image data b is shifted into a signal by the latch 26 at the timing of , and is separated into b1-b and b7-b1°. For example, S is A in FIG. 6, and b7 is A3. Here, the signals input to the selectors 27 and 31 are s, =b, respectively.

b□-1/2 b, l-.

b3=1/4 t)ll-+ bb -ba 10 bs =1/2 b +1/4 b
= 3/4 bI,.

Also, bt -1/2 bll ba -1/4 b, l b,, -b, tensu,. =1/2 bI1/4 b=3/
4 b, l.

Furthermore, since the truth table of the selector 27.31 is as shown in FIG. 13, the image data b, t, b11 . c is as follows.

That is, input data bI scaling data, , 2, ,
Corrected data C is obtained correspondingly.

Note that image data b, therefore b1 to b11, is 1 in the signal.
However, the selection conditions 2 and 2 are obtained at the timing of the clock signal CLK.

FIG. 14 shows the first and second line memories 5, 6 in FIG.
FIG. 15 is a time chart illustrating the operation of the circuit shown in FIG. 14. In the figure, 32.33 is the gate, 5
, 6 are first and second line memories, 34.35 is a latch, 9 is a memory controller, 36.37, 38.42
is a gate, 39.40 is a counter, and 41 is a selector.

With reference to FIGS. 14 and 15, counter 39.4
0 are address counters for the first and second line memories 5.6, respectively, and count on/off control signals l
Based on the selector 41, the signal 1. , It! occurs, and the progress of counters 39 and 40 is controlled. Selector 41 is j! , =n(ttz ='H') also lOJ
(J, -“H”), and the selection condition is the signal l.

p, therefore signal 1. Depends on. That is, as shown in FIG. 4, the selection conditions differ depending on the variable magnification mode (1) and the even/odd number (p) of the scanning lines.

For example, in the enlargement mode, the counter on the line memory side in the read mode is controlled by the signal 1, and the counter on the one line memory side is always in the count-up mode with the terminal EN="H". Furthermore, the write and read modes are alternately reversed for each scanning line.

In addition, in the reduction mode, the counter on the line memory side in the read mode is always counting up at EN-#H#, and the other line memory side is in the write mode, and the count is controlled on and off by the signal l. .

The truth table surrounding the selector 41 is shown in the table below.

Also, below the signal W is a write control signal to the line memory (actually RAM), and according to the signal P, the first and second
Write operations are performed alternately in line memories 5 and 6. That is, the second line memory 6 is in the write mode for the even numbered line p-0", and vice versa when the second line memory 6 is in the read mode for the even numbered line p-#1".

FIG. 15 is an example of i, -"l', especially i-"1# (-enlargement mode), p=0 (-even line).

Signal i is a signal corresponding to △11 in scaling data j,
l-1" corresponds to ΔIE#1", and at this time, address counters 39 and 40 are counting on. On the contrary, l-
“0#” corresponds to Δr,=“o”, and at this time, the address counters 39 and 40 are count-off.

Therefore, the outputs of counters 39 and 40, that is, the first
and address signals ml, n of the second line memory 5.6
, advances as shown in FIG.

Then, the signal f1 is read out from the first line memory 5. (mz), (mI-), etc. in the signal f1 mean data corresponding to addresses mll, m, □. The signal f1 is shaped by the latch 34 at the timing of the signal CLK and becomes the signal g.

On the other hand, the signal f2 is written to the second line memory 6. This signal f2 is the input image data f, and the gate 33
The signal is inputted to the second line memory 6 via. At this time,
h=f,=f are also output from the output of the latch 35,
Even if the data signal on the write mode side is output in this way, the e=g side is selected by the selector 7 in FIG. 3, so h in this case has no meaning. However, when the line is an odd number, e=h, and g becomes meaningless.

FIG. 16 shows that data g (or h) read from the first line memory 5 (or second line memory 6) in FIGS. If sent to
3 is a time chart illustrating the operation of the data correction section 2. FIG. In particular, in correspondence with the example in Fig. 15, b-g=a''I is set.Here, a-1 is selector 1, bma is not selected, and b-g is selected, but if you trace this g back, Since the result is the signal a from one line earlier, it is set as a −1.

Also, the reason for adding Ax, A3, and A4 in correspondence to (ml.), (m, 1), and (m, -) is that the example near At, As, and A4 in Figure 6 matches well with this case. Because it does.

Signal K corresponds to signals J and CLK in FIG.

is as shown in FIG. 16 (generated by latch 13 and gates 24 and 25 in FIG. 8). This signal causes the output b1 (therefore Bt,
Bs, Bb) are as shown in FIG.

On the other hand, the signal *, Kx is the signal CL as shown in FIG.
Changes at the timing of K. Therefore, the correction data output c (=d) changes at the timing of the signal CLK as shown in the same figure, and is exactly B21°B 0+ B *
As noted as s+ B 31 B 2t, the timing and concentration level correspond to the relationship between A and B in FIG. 6.

FIG. 17 is a diagram for supplementary explanation of the principle and operation at the time of enlargement mentioned above.
(enlargement). In the figure, n −1, 2, −・
・Corresponding to 250, the value of X, 1 = 100/α x n,
Furthermore, the address (ADH) of the RAM 14 (FIG. 8) and the states of other signals are shown corresponding to n.

100/α-0,4, so l Q Q / a
As shown in the figure, X n is a sequence of 250 numbers from 0.4 to 100. 2'-△1 from the integer part of 100/α×n
．． -1. -17-9 is as shown in the figure. In addition, the decimal part KN 'l Ks ' is as shown in the figure, and furthermore,
I4 indicating the end bit is n-1 to 249 and is j-'0'
, n-250 and j-"1'.

These pieces of information are written into the RAM 14 as scaling data.

On the other hand, during the actual zooming operation, the contents of the RAM 14 are read out, as shown in FIG.

C+Jt indicates the state of each part at the time of reading n=1 to 250.
This is shown in correspondence with . In particular, the values of b (, b, and c shown in FIGS. 6 and 16 correspond to n-5 to 12).
It corresponds to the figure. Further, as explained in FIG. 8, j is a signal indicating the opening point from n=1, and in this embodiment, j is treated as a signal for clearing the address of RAMI 4 when writing to RAM 14. . Jt itself is R
It is not written to AM14, so this I2 has no meaning when read.

FIG. 18 and FIG. 19 are diagrams for supplementary explanation of the principle and operation at the time of reduction, and show the case of α-71% as an example.

In Fig. 18, 100/αX 1 corresponds to n=1 to 71.
1 and ΔI9, and in FIG. 19, ΔI9.

After transforming (decomposing into △I, , -2-△r, = 0 and 1), β'-81. (Deformed) The state of each part is shown in comparison with FIG. 17.

In particular, the values of bl, b, and c corresponding to n=5 to 10 are the seventh
This corresponds to the example in the figure. Here, J's C"Ba, B4.
Bt, etc. do not appear in FIG. 7 either, and have no particular meaning during actual zooming operations.

In other words! ' - These C values that occur when "O" are stored in the first (or second) line memory 5
(or 6), but since J'="0", it becomes z-"o' in FIG. 8, and therefore becomes J, (or 2g)-"0# in FIG. 14, and the address counter 39 ( or 40) address does not increment.

That is, returning to FIG. 19, the value of C at β'-"0# is written to the first (or second) line memory 5 (or 6), but the same value is written in the next J'-"1'. The value of C corresponding to β'-11' is written to the address. In this way, C at J'-'01 is dummy data, the value itself has no meaning, and as is clear from FIG. 7, it is a sampling point that is not realized.

FIG. 20 is a time chart showing the states of each part corresponding to n=5 to 10 in FIG. 19. In FIG. 0, f, = fw
In c, Bo, B+ as shown.

-...-'Bt is generated, but when reading, dummy data such as Bo and Ba disappear as shown in g in Figure 20, and Bt is generated.
+, Bt, Bs, Bs' ---.

The embodiments of the principle, operation, and configuration of variable magnification according to the present invention have been described above. Next, a typical example of the application of the present invention will be explained with reference to FIGS. 21 and 22.

FIG. 21 is a schematic diagram of the image reading device, 43 is a contact glass, 44 is a document, 45.46 is a light source, 47, 48
．． 49 is a reflecting mirror, 50 is an imaging lens, 51 is a COD
(charge-coupled device) reading section including a line sensor, 52
is an image processing section.

In this image reading device, the main scan is electronically scanned by a CCD line sensor in a direction perpendicular to the plane of the paper in the figure, and the sub-scan is carried out by a light source 45, 46 and a reflecting mirror 41, 48, 49 as shown in the figure. Scan by moving in the direction of the arrow.

The image data read by the reading unit 51 is processed by the image processing unit 52.
After the image is processed, it is output externally.

Here, the magnification changing operation in the main scanning direction is performed according to the above-described invention, and the magnification changing operation in the sub-scanning direction is performed by controlling the sub-scanning speed.

FIG. 22 is a functional block diagram of a portion of FIG. 21 that particularly relates to read data. In the figure, 44 is the manuscript;
45 and 46 are light sources, 51 is a reading unit, 51a is a CCD line sensor, 51b is an amplifier, 51c is an A/D converter,
52 is an image processing unit, 52a is a shading correction, 52
b is magnification, 52C is MTF (modulation transfer function) correction, 5
2d indicates binarization. In this configuration the light source 45.46
The original 44 is illuminated. The image of the original 44 is read by a CCD line sensor 51a, and an amplifier 51b, A/D
The data is converted into 6-bit, 64-gradation digital data via a converter 51C. Thereafter, inside the image processing section 52, shading correction 52a is first performed, and then magnification changing operation 52b is performed. After further MTF correction 52c, the image is converted into 2(a) 52d and outputted to the outside as binary image data.

FIG. 23 is a block diagram showing another application example of the present invention.
3 is an image memory, 54 is a variable magnification mechanism, and 55 is an output device. In this application example, when the image data stored in the image memory 53 is read out and printed by the output device 55 such as a laser beam printer, the modification according to the present invention is installed between the image memory 53 and the output device 55. A magnification mechanism 54 is provided to perform real-time magnification change at a speed that follows the speed of the output device.

(Effects) As described above, according to the present invention, when enlarging and reducing image data in the main scanning direction, data is read from the line memory during enlargement based on the scaling information from the scaling control memory. When data is written to the line memory, the address of the line memory can be controlled based on the scaling information from the scaling control memory. Also, when enlarging image data, successive data from the line memory is input to the data correction unit based on the scaling information from the scaling control memory, and when reducing image data, the output data from the data correction unit is input to the data correction unit. It is possible to write to the line memory and to control this write address based on the scaling information from the scaling control memory. Furthermore, two line memories are provided, and these line memories alternately switch their operation modes for each main scan, so that when one is in the continuous output mode, the other is in the write mode. With this configuration, the present invention can electrically change the size of digital image data using a simple hardware configuration. Furthermore, it is possible to provide a method for changing the size of image data that has the effect of making it possible to change the size by real-time processing synchronized with an input device or an output device.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram explaining pixels, image data, main scanning, sub-scanning, etc., FIG. 2 is a time chart of signals corresponding to FIG. 1, and FIG. A block diagram showing one embodiment, FIG. 4 is an explanatory diagram explaining an overview of the operation of the configuration in FIG. 3, and FIG. 5 is an input signal a of FIG. 3.
Fig. 6 is a time chart similar to Fig. 5 but showing an enlarged example, Fig. 7 is a time chart showing a reduced example of Fig. 5, and Fig. 8 is a time chart showing a reduced example of Fig. 3. Circuit diagram showing the internal logic of the variable magnification control memory, No. 9
The figure is a time chart explaining the write operation, FIG. 10 is a time chart explaining the operation of FIG. 8 in the mode of reading variable magnification data from RAM, and FIG.
K.1. To,. 12 is a circuit diagram showing the internal logic of the data correction section in FIG. 3, FIG. 13 is a truth table of the selector, and FIG.
A circuit diagram showing the internal logic of the first and second line memories and the memory controller in the figure, FIG. 15 is a time chart explaining the operation of the circuit in FIG. 14, and FIG. 16 is an explanation of the operation in the data correction section. Time chart, No. 17
The figure is an explanatory diagram for supplementary explanation of the principle and operation at the time of enlargement, Figures 18 and 19 are explanatory diagrams for supplementary explanation of the principle and operation at the time of reduction, and Figure 20 is an explanatory diagram for supplementary explanation of the principle and operation at the time of reduction.
Time chart showing the status of each part corresponding to No. 10, No. 2
FIG. 1 is a schematic diagram showing an image reading device as an application example of the present invention, FIG. 22 is a functional block diagram of the portion related to read data in FIG. 21, and FIG. 23 is a block diagram showing another application example of the invention. be. 1, 3. 4. 7... Selector, 2... Data correction section, 5.6... Line memory, 8... Magnification control memory, 9... Memory controller, 14.
...RAM. Figure Kei' υ3Y1 2----- m Figure 2 Procedural Amendment (Voluntary) Change of Name Image Data of Invention Patent Application No. 61-226196, January 7, 1985 Case of the Commissioner of Patents Relationship with the case of the person making the double method amendment Applicant

Claims (4)

[Claims] (1) In an image data scaling method that includes a line memory with a capacity for at least one main scanning line and a scaling control memory in which scaling control information is stored, image data is enlarged and reduced in the main scanning direction. When reading data from the line memory during enlargement, the address of the line memory is controlled based on scaling information from the scaling control memory, and when writing data to the line memory during reduction, the address of the line memory is controlled based on the scaling information from the scaling control memory. A scaling method for image data, characterized in that an address of the line memory is controlled based on scaling information from a scaling control memory. (2) An image data converter equipped with a line memory having a capacity for at least one main scanning line, a scaling control memory in which scaling control information is stored, and a data correction section that corrects data during scaling operation. In the double method,
When enlarging image data, the readout address from the line memory is controlled based on the scaling information from the scaling control memory, and at the same time, the readout data from the line memory is input to the data correction section, and the image data is When reducing image data, output data from the data correction section is written into the line memory, and this write address is controlled based on scaling information from the scaling control memory. method. (3) The image data scaling method according to claim (2), wherein the operation of the data correction section is performed based on scaling information from the scaling control memory. (4) A line memory having a capacity for at least one main scanning line and a scaling control memory in which scaling control information is stored; In an image data scaling method that controls the address of the line memory when reading data from the memory and when writing data to the line memory during reduction, two line memories are provided, and these line memories An image data scaling method characterized in that the operating modes are alternately switched for each main scan, so that when one is in a read mode, the other is in a write mode.