JPS6375790A - Digital-analog converter - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a graphic processing device suitable for use in a color display device using a cathode ray tube (CRT), and more particularly, the present invention relates to a graphic processing device that is equipped with a color reference memory and has an image memory. The present invention relates to a digital-to-analog conversion device that generates color output analog data according to address specification.

[Conventional technology]

A graphic processing device of a CRT display device includes an image memory and a digital-to-analog conversion device. A digital-to-analog converter mainly consists of a color reference memory that stores data representing colors to be displayed on a CRT display device (hereinafter referred to as color data), and a digital converter that converts data read from the color reference memory into color data. Analog conversion circuit and color reference memory address signal (pixel data)
It consists of a pixel data input circuit that takes in pixel data.

Different types of color data are stored at different addresses in the color reference memory, and by specifying this address, the color data stored at the specified address is read out. Further, in the image memory, an address is assigned to each pixel of the CRT display device, and each address contains an address (
This is pixel data) is stored.

When scanning is performed on a CRT display device, addresses in the image memory for (pixels) are sequentially specified at the scanning positions and pixel data is read out. These pixel data are taken in from the pixel data input circuit in a digital-to-analog conversion device, where the color data for the scan position is read out from the color reference memory using the pixel data, and converted into color output analog data in the digital-to-analog conversion circuit. Supplied to a CRT display device. This causes colors to be displayed on the screen of the CRT display device.

Such a digital-to-analog conversion device has conventionally been used, for example, in r-Electronic Design JS
ep 5, 1985 pp.

131-140, the clock signal provided on one semiconductor substrate and providing timing for capturing pixel data is provided from outside the semiconductor substrate. Then, a plurality of pixel data are taken in at the same time, and for this purpose, this clock signal is divided by a frequency dividing circuit to generate a load timing signal for taking in pixel data.

[Problem that the invention seeks to solve]

By the way, the clock signal supplied to such a digital-to-analog conversion device needs to have a very high frequency. This is because the scan timing of pixels on the screen of the CRT display device and the timing at which the pixel data input circuit takes in pixel data must be synchronized. To increase the resolution of the reproduced figure, for example 1000 pixels x 1000
In order to generate color output analog data for a pixelated CI'LT display device, the frequency of the clock signal must be 100 MHz.

For this reason, a very high-speed clock generation circuit is required, and a frequency dividing circuit that forms a timing signal for capturing pixel data is also required to be very high-speed.

For this reason, these clock generation circuits and frequency dividing circuits are
There was a problem in that it had to be constructed with L, making it expensive.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, and to provide a digital system that can use a low frequency clock signal and generate color output analog data that enables high-resolution graphic display.・Analog conversion M
It is to provide lit. .

[Means for solving problems]

In order to achieve the above object, the present invention provides a plurality of systems each consisting of a pixel data input circuit and a color reference memory, and simultaneously captures a predetermined number of pixel data in each system to simultaneously obtain color output data. Select color output data from each in order and arrange them in pixel order on the 081 screen,
Generate desired color output analog data.

[Effect]

Now, if the frequency of the color output data supplied to the digital-to-analog conversion circuit is φ, this frequency φ is also equal to the number of pixels scanned per second on the screen of the CRT display device, and the above-mentioned prior art equal to the frequency of the clock signal at .

Furthermore, if the number of the above-mentioned systems is 2 and the number of pixel data taken into each system at once is M (where M is a positive integer), then the timing frequency for taking pixel data into each system is west.

On the other hand, the two systems of color output data are alternately selected and output to the CRT.
The color output data is arranged in the order of pixels on the screen of the display device, and the frequency of the selection signal of this color output data is φ/2. Therefore, the frequency of the clock signal can be set to φ/2, and a clock signal with a much lower frequency than in the prior art can be used.

Generally, the number of the above systems is N (however, N is an integer of 2 or more)
Then, the frequency of the clock signal is .

〔Example〕

First, a graphic processing device using a digital/analog device according to the present invention will be schematically explained with reference to FIG.

In the figure, a digital/analog converter 102 is provided on one semiconductor substrate and has two systems each consisting of a pixel data input circuit and a color reference memory. The frequency of the color output analog data 124 supplied to the device 103 is assumed to be φ.

Video timing generator Zoo generates a clock signal 120 at frequency V2. The digital-to-analog converter 102 forms a frequency load timing signal 121 from this clock signal 120 and sends it to the image memory 101. Upon receiving this timing signal 121, the image memory 101 generates pixel data (hereinafter referred to as even pixel data) 122 corresponding to even-numbered pixels on the screen of the CRT display device 103 as well as pixel data corresponding to odd-numbered pixels. (hereinafter referred to as odd pixel data) 123 and the frequency φ/ at the same time in a separate system.
Read at timing 4.

Note that these even pixel data 122 and odd pixel data 123 are l or 2 or more pixel data, respectively, and these are stored in the image memo I as parallel bit data.
Output from JIOI. In the embodiment described later with reference to FIG. 1, it is assumed that the pixel data is 4-bit data, and the even pixel data 122 and the odd pixel data 123 are both composed of two pieces of pixel data. , even pixel data 122, and odd pixel data 123 are all 8-bit parallel data.

These even pixel data 122 and odd pixel data 12
3 is taken in by the digital-to-analog converter 302, and color output data corresponding to pixel data for each system is read out from the color reference memory, and then output to the CRT display device 10.
The color output analog data 124 is generated by arranging and synthesizing the pixels so as to correspond to the pixel arrangement order on the screen of No. 3.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital-to-analog converter according to the present invention, in which 1 is a branch circuit, 2 is a branch circuit;
, 3 is a shift register circuit, 4゜5 is a color reference memory, 6
9 are latch circuits, 10 is a phase inversion circuit, 11 is a multiplexer, and 12 is a digital-to-analog conversion circuit.

In the figure, a shift register circuit 2, a color reference memory 4
, latch circuits 6 and 8 form one system, and shift register circuit 3, color reference memory 5, and latch circuits 7 and 9 also form another system. The shift register circuits 2 and 3 each consist of a plurality of shift registers, and the image memo +) 101
It constitutes a pixel data input circuit that takes in even pixel data 122 and odd pixel data 123 sent from the circuit (FIG. 3). A plurality of different color data are stored in the color reference menus 4 and 5. Here, it is assumed that the ca'r display device 103 (FIG. 3) expresses 16 gradations of color, and therefore, the color reference memories 4 and 5 each have 16 tones of color.
Seed color data is stored, and each color data has 4 bits. In the color reference memory 4 and the color reference memory 5, the same color data is stored at the same address.

Next, the operation of this embodiment will be explained using the timing chart of FIG.

A clock signal 120 with a frequency φ/2 sent from a video timing generator 100100 (figure) is transmitted to a frequency dividing circuit 1
Load timing signal 1 with frequency V4 divided by 2 by
21 and sent to the image scale memo IJ 101 (FIG. 3) and the shift register circuit 2.3. The image memory 101 stores even pixel data 122 . Odd pixel data 123
Read out. The shift register circuit 2 converts the parallel even pixel data of frequency φ7' 4058 bits (4 bits/pixel x 2 pixels) sent from the image memory 101 into the load timing signal 12 of frequency V4.
1 and a clock signal 120 with a frequency of 1,
shift.

1 on the screen of the CRT display device 103 (Fig. 3).
Pixel data for the th, 2nd, 3rd, 4th, etc. pixels are ≠X, +2. +3, 4.
...and the odd pixel data 123 is 2 pixel data ÷ 1. Even pixel data 122 consists of two pixel data numbers 2 and 3.

The shift register circuit 2 includes, for example, two 4-bit shift registers. Pixel data φ2. When even pixel data 122 consisting of 4 is supplied, these pixel data 2 .
4 are respectively loaded into separate 4-bit shift registers on the rising edge of load timing signal 121. The pixel data na 2 stored in one of the 4-bit shift registers is directly supplied to the color reference memory 4 as 4-bit parallel output pixel data 221, and the 4-bit parallel color data at the address specified by the pixel data na 2 is supplied as is. is read out as color output data 223. In the shift register circuit 2, at the next rising edge of the clock signal 120, the pixel data 4 stored in the 4-bit shift register is shifted to the other 4-bit shift register and sent to the color reference memory 4 as output pixel data 221. It will be done. Therefore, from the color reference memory 4, the pixel data number 4 at the address specified by the pixel data number 4 is
Bit parallel color data is read out as color output data 223.

The same applies to the shift register circuit 3. First, pixel data number 1 of odd pixel data 123 is sent to the color reference memory 5 as output pixel data 222, and clock signal 1 is sent to the color reference memory 5.
On the next rising edge of 20, the pixel data data 222 is sent to the color reference memory 5 as output pixel data 222. As a result, from the color reference memory 5, pixel data divided by 1.
4-bit parallel color output data 224 for +3 is obtained in that order.

In addition, in FIG. 2, pixel data +1. Su2゜na3.
1. The color output data for 4 is the same code. 2.
3. It is represented by 4. Color output data na2. Color output data 4.1 is obtained at the same timing, and then color output data 4. 2 are obtained at the same timing.

Color output data 223 is latched by latch circuit 6 at the rising edge of clock signal 120, and color output data 224 is similarly latched by latch circuit 7.

The color output data 226 output from the latch circuit 7 is latched by the latch circuit 9 at the same rising edge of the clock signal 120 as the latch circuit 7, but the color output data 225 output from the latch circuit 6 is The latch circuit 8 latches the signal 120 at the rising edge of the inverted clock signal 220 obtained by inverting the phase of the signal 120 by the phase inverting circuit 10 . Therefore, latch times! The latch timing of @8 is delayed by one cycle of the clock signal 120 than the latch timing of the latch circuit 9, and the color output data 227 output from the latch circuit 8 is 1/1/2 slower than the color output data 228 output from the latch circuit 8. There will be a delay of two cycles.

Multiplexer 11 is controlled by clock signal 120 and outputs color output data 228 when clock signal 120 is high and outputs color output data 22 when clock signal 120 is low.
Select 7. Therefore, multiplexers 11 to 4
Bit-parallel color output data is 1, 2. ÷3. ÷
172 cycles of the clock signal 120 are obtained in the order of 4.

In this way, the multiplexer 11 outputs color output data 229 with a frequency φ that is twice the frequency V2 of the clock signal.
is obtained. This color output data 229 is converted into color output analog data 124 by the digital/analog conversion circuit 12 and supplied to the CRTfi display device 103 (FIG. 3).

As described above, in this embodiment, the clock (i) having a frequency that is half the frequency of the color output analog data supplied to the CR1 display device is supplied from outside the semiconductor substrate, and the pixel data input The timing signal for is also obtained by dividing this clock signal, so
The clock signal generation circuit and the frequency division circuit for forming the timing signal can operate at low speeds, and these can be used in expensive ECs.
There is no need to use Li, and the frequency dividing circuit can also be provided on the same semiconductor substrate.

In the above embodiment, two systems each consisting of an input circuit and a color reference memory were provided, but this is generally N.
(where N is an integer of 2 or more), and in this case, the frequency of the clock signal supplied from outside the semiconductor substrate can be set to φc. Furthermore, M pieces of pixel data of each system output from the image memory 101 (
However, if it is made up of pixel data corresponding to pixels (M is an integer greater than or equal to 1) (therefore, if each system's pixel data is made up of pixel data corresponding to pixels or bits, then it is kM bi-nod parallel data. An M frequency divider circuit is used as a frequency divider circuit (corresponding to frequency divider circuit 1 in Fig. 1) that forms a load timing signal from a clock signal, and the frequency of the load timing signal is (φc). It will be 7M.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to operate using a clock signal with a lower frequency than the frequency of color output analog data corresponding to the resolution of a display device, and the clock signal generation circuit and the clock There is no need to use a high-speed but expensive CL in the circuit configuration of a frequency divider circuit that forms a load timing signal for inputting pixel data from a signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital-to-analog converter according to the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a graphic processing using this embodiment. FIG. 2 is a block diagram showing the device. l... Frequency divider circuit 2.3... Shift register circuit 4.5... Color reference memory 6-9... Latch circuit 1
0...Phase inversion circuit 11...Multiplexer 12...Digital/analog conversion circuit -' Agent Patent attorney Masao Ogawa IT Figure socket 3 Concave chamber 2 Mouth

Claims (1)

[Claims] 1. N systems each consisting of a pixel data input circuit that captures pixel data, a color reference memory that sends out color output data corresponding to the captured pixel data (N is an integer of 2 or more), and a clock signal. a frequency divider circuit that generates a load timing signal that divides the frequency of the pixel data by N to set the timing of taking in the pixel data in the pixel data input circuit; a multiplexer that sequentially selects the N systems of color output data; has a digital/analog circuit that converts the output data of the color output analog data into color output analog data, and while the frequency of the color output analog data is φ, the frequency of the clock signal can be set to φ/N. A digital-to-analog converter characterized in that it is configured as follows.