JPS6366791A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain a similar noise resistance to a conventional folded bit line structure and a similar integration to an open bit line structure by maintaining a sense amplifying sensitivity by connecting a global bit line and a sense amplifier having respectively the same length to the two input terminals of the sense amplifier. CONSTITUTION:Memory cells 1c, 1d selected by a word line W2 are respectively connected to the sense amplifiers 12b, 12a, detected and amplified. In such a case, to the one input terminal of the sense amplifier 12a, the global bit line 3a and a segment bit line 2a are connected and to the other input terminal, the global bit line 3b and a segment bit line 2b are respectively connected. To the one input terminal of the sense amplifier 12b, the global bit lines 3c, 3e, 3g and a segment bit line 2c are connected and to the other input terminal, the global bit lines 3d, 3f, 3h and the segment bit line are respectively connected. Thereby, the capacity of the two bit lines inputted to the sense amplifier is balanced and the intensity of a collected coupling noise is equal, so that the noise resistance is not deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in semiconductor memory devices, and particularly to improvements in bit line structures for higher integration.

[Prior Art] Figure 3 shows, for example, the 1986 International Solid State Circuit Conference (
15 is a circuit diagram showing a bit line connection structure of a highly integrated dynamic semiconductor memory device proposed in Lecture No. FAM19.5 of I5SCC86); FIG.

In FIG. 3, la and lb are memory cells, 2a,
2b, 2c, 2d are first layer bit lines (hereinafter referred to as "segment bit lines") connected to memory cells, 3a
, 3b, 3c, and 3d are second-layer bit lines (hereinafter referred to as "global bit lines") that connect the sense amplifier and the segment bit line. 4.5, 6.7.8, 9.10.1
1 is a switching element, 12a, 12b are sense amplifiers, 13°14, . 15.16.17.18 are word lines,
19 and 20 are segment select signals, and 51 is a dummy cell.

On the other hand, FIG. 4 is a plan view of a conventional memory cell having a normal folded bit line structure. In the figure, 21 is a 1-bit memory cell, 22 is a bit line, and 23 and 24 are word lines. In the configuration of FIG. 4, it is necessary to pass two word lines through the region of one bit of the memory cell, which limits the reduction in the planar area of the memory cell.

On the other hand, the configuration shown in FIG. 3 achieves high integration by forming cells at each intersection of a word line and a bit line without sacrificing the advantages of the folded bit line structure. In FIG. 3, the memory cells are divided into two blocks by switching elements 5 and 7. In FIG. Memory cells are arranged at each intersection of a segment bit line and a word line.

When the memory cells of the left block are selected by the word line 13, the storage information of the memory cells la and lb is read out to the segment bit lines 2a and 2b. At this time, switching elements 4.6 and 10.11 are turned off, and switching elements 5. 7. 8. 9 becomes conductive, the memory cell 1a connects to the sense amplifier 12a, and the memory cell 1b connects to the sense amplifier 12a.
are connected to the sense amplifier 12b, respectively. Therefore, information in memory cells la and lb is amplified by sense amplifiers 12a and 12b, respectively, and read and rewritten. When selecting the left block of memory cells, switching element 4゜6.10.1
1 is made conductive, and switching element 5. 7. 8.
9 is turned off, the information in the two selected memory cells is similarly amplified by the sense amplifiers on both sides.

The sense amplifier 12a has a function of amplifying the potential difference generated between the two input terminals 25 and 26. On the other hand, even if coupling noise such as a clock signal in the chip is placed on the bit line, since the bit lines 3e and 3f are close to each other, the coupling noise picked up by the bit lines 3e and 3f will be in phase, and the sense amplifier 12a does not interfere with the operation of the In other words, the circuit shown in FIG. 3 has the characteristics of high integration similar to the oven bit line structure, in which memory cells can be formed at the intersections of bit lines and word lines, and the folded bit line structure, which is resistant to noise. The aim is to have both.

[Problems to be Solved by the Invention] However, the input terminal 25 of the sense amplifier 12a has two lines, the groupal bit line 3e and the segment bit line 2a.
Since the structure is such that two bit lines are connected and only the groupal bit line 3f is connected to the input terminal 26, the coupling noise picked up by the segment bit line 2a is not canceled out. Therefore, the configuration described above is inferior in noise resistance compared to a conventional circuit with a normal folded bit line structure, and the load capacitance attached to the two terminals of the sense amplifier becomes unbalanced, so the sense amplifier sensitivity There is a problem of deterioration.

This invention was made to solve the above-mentioned problems, and while maintaining the same degree of integration as the oven bit line configuration, it reduces the bit line imbalance as in the conventional example, and improves the sense An object of the present invention is to provide a semiconductor memory device with improved amplifier sensitivity and noise resistance.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a global bit line to which a segment bit line including a selected memory cell is connected to two input terminals of a sense amplifier, and a global bit line to which a segment bit line including a selected memory cell is connected to two input terminals of a sense amplifier. A switching element is provided to connect a segment bit line containing memory cells to a connected global bit line.

[Function] The semiconductor memory device according to the present invention has two sense amplifiers.
Since the global bit line and the sense amplifier having the same length are connected to each of the two input terminals, the two input loads of the sense amplifier can be balanced. Therefore, noise immunity similar to traditional folded bit line structure,
It is possible to achieve the same degree of integration as an oven bit line structure while maintaining sense amplifier sensitivity.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, la, lb, lc, ld, 1e, if
, Ig, lh are memory cells, 2a, 2b.

2C, 2d, 2e, 2f, 2g, 2h are segment bit lines, 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3
h is a global bit line, φ1. φ2, ψ1. ψ2 is the control signal, 30.31 is due to φ1, 32.33 is due to φ2
By, 34. 35°36.37 is due to ψ1,
3g, 39. 40°41 are switching elements Wl, W2 ., respectively controlled by ψ2. W3. W
4 is a word line, and 12a and 12b are sense amplifiers.

In FIG. 1, the memory cells are divided into four blocks A, B, C, and D. Each block actually has a plurality of word lines, but only one is shown in the figure. A memory cell is formed at each intersection of a word line and a segment bit line, as in the case of the open bit line configuration.

Next, the operation will be explained. Prior to selecting a memory cell, control signal φ1. φ2. ψ1. With ψ2 set to "H" level, all segment bit lines 2a to 2h and global bit lines 3a to 3h are connected, and their potentials are all equalized or precharged to a constant potential.

Next, for example, when selecting a memory cell in block B, ψ1-“H”, ψ2-“L”.

φ1-“L”, φ2-“H”, word line W2 “H”
" level. At this time, the memory cells IC and ld selected by the word line W2 are connected to the sense amplifier 12b and the sense amplifier 12g, respectively, and are sensed and amplified.

At this time, one input terminal of the sense amplifier 12a has
The global bit line 3a and the segment bit line 2a are
The other input terminal is connected to the global bit line 3b and the segment bit line 2b, respectively. Also,
A global bit line 3c is connected to one input terminal of the sense amplifier 12b.

3e and 3g are connected to the segment bit line 2c, and the other input terminal is connected to the global bit line 3d.

3f and 3h are connected to segment bit line 2b. Therefore, the capacitances of the two bit lines input to the sense amplifier are balanced. Further, since the magnitude of coupling noise picked up by the two bit lines is also the same, noise resistance does not deteriorate.

When selecting cells in another block of the memory cell array, the signal ψ1. ψ2. φ1. By setting φ2 as shown in the table below, the same operation as described above can be performed.

FIG. 2 is a diagram showing an example of the layers of each bit line in the configuration of FIG. 1. For example, aluminum (Aα) is used for the global bit lines 3a to 3h,
Third layer polysilicon is used for segment bit lines 2b, 2c, 2f, and 2g, and fourth layer polysilicon is used for segment bit lines 2b, 2c, 2f, and 2g. Then, for example, the word line W2 is set to “
When the memory cells lc and ld are selected by raising the level to H'',
Segment bit lines 2a and 2d made of third layer polysilicon are connected to sense amplifier 12a, and segment bit lines UA2b and 2c made of fourth layer polysilicon are connected to sense amplifier 12b. Therefore, since the two segment bit lines connected to the sense amplifier are formed of the same wiring material, they have good symmetry.

In the above embodiment, the case where the segment bit line has a length of 1/4 of the global bit line is shown, but the same applies when the segment bit line has a length of 1 of the even numbered bones of the global bit line. Applicable to

Further, in the embodiment shown in FIG. 1, switch elements are made that cross only the lower global bit line, but each boundary may be replaced with a global bit line that has a switch element that crosses.

[Effects of the Invention] As described above, the present invention provides a semiconductor that can achieve the same degree of integration as the oven bit line structure while maintaining the same noise resistance and sense amplifier sensitivity as the conventional folded bit line structure. It can be a storage device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the structure of an embodiment of the present invention. FIG. 2 is a diagram showing an example of layers of each bit line in the structure of FIG. 1. FIG. 3 is a circuit diagram showing the structure of a bit line of a conventional semiconductor memory device which is interesting to the present invention. FIG. 4 is a plan view of a memory cell having a conventional normal folded bit line configuration. In the figure, 1a to 1h are memory cells, 2a to 2h are segment bit lines, 3a to 3h are global bit lines,
φ1. φ2. ψ1. ψ2 is a control signal, 30-41 are switching elements, W1-W4 are word lines, 12a, 12b
indicates a sense amplifier.

Claims (1)

[Claims] A memory cell array equally divided into a plurality of blocks in the bit line direction, a first type bit line provided for each block and having contacts with the memory cells, and a first type bit line having contacts with the memory cells. In a semiconductor memory device equipped with a type 2 bit line that does not have a second type bit line, among the boundaries between each block, an odd-numbered boundary from the end of the memory cell array has a second type bit line connected to one input terminal of the sense amplifier. A switch element that connects two types of bit lines and a first type block in the same block as this second type bit line, a second type bit line connected to the other input terminal of the sense amplifier, and a second type bit line connected to the other input terminal of the sense amplifier. A switch element that connects a second type bit line with a first type bit line in an adjacent block across a boundary, and between second type bit lines in adjacent blocks across a boundary. At even-numbered boundaries from the end of the memory cell array among the boundaries between each block, only the second type bit lines in adjacent blocks across the boundary are connected to each other. A semiconductor memory device characterized by: