JPS6365528A - Coprocessor - Google Patents

Abstract

PURPOSE:To receive an instruction and an operand from a CPU one by one even in execution of an internal processing currently, and to contrive to improve the processing capability of the CPU, by storing the instruction and the operand in a stack memory of FIFO style capable of stacking them. CONSTITUTION:The stack memory 2 stores a firmware start address 20, and an operand load number 21 at time of inputting the instruction, and an operand data on an external data line 11, at time of reading the operand, in a FIFO format, after adding data identification signals 23 on them, respectively. And the instruction and the operand for a coprocessor form the CPU are stored immediately in the stack memory 2, in the data format of an internal firmware start address B and an operand data. In this way, it is possible to execute the next instruction of the coprocessor, or other possible to execute the next instruction of the coprocessor, or other instructions by the CPU without a waiting time, thereby, the processing capability of the CPU can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a co-processor connected to a central control unit (hereinafter abbreviated as CPU), and particularly relates to a co-processor connected to a central control unit (hereinafter abbreviated as CPU).
The present invention relates to a co-processor having a stack memory capable of storing instructions and operands for the processor.

[Conventional technology]

Traditionally, this type of co-processor has an instruction-holding processor that holds instructions for a co-processor.

It has one set of operand holding registers that can hold all the operands used in that instruction, receives an instruction from the CPU to the coprocessor, and at the same time it moves to internal processing or waits for operands, it sets a busy signal, and all internal By resetting the busy signal after processing is completed, the instruction holding register and operand holding register are prevented from being rewritten by the next co-processor instruction or unnecessary operand during execution of internal processing.

[Problem that the invention seeks to solve]

The conventional co-processor described above performs 9. by setting the pinot signal while internally executing one co-processor instruction. Control is performed so that the CPU does not issue the next co-processor instruction. In addition, co-processor instructions can generally be calculated faster than inside the CPU, so
High-speed instructions that perform internal calculations in co-processor and CP
There are instructions that are so complex that they are almost impossible to perform inside the U, and that take a long time to process even inside the coprocessor. In conventional co-processors, regardless of the length of processing time, the CPU is kept waiting when executing one co-processor instruction, so if co-processor instructions with long processing times continue,
CPU waiting time increases and CPU instructions after the co-processor instruction that is waiting are not executed.

This has the disadvantage that the processing power of the CPU decreases. In addition, since all co-processor instructions perform busy control, the number of firmware steps for this control increases, and after resetting the busy signal, the co-processor instruction and its operand data that were waiting are input to the co-processor. The co-processor will also stop operating until
The drawback is that the co-processor is not used effectively.

[Failure to solve the problem]

The co-processor of the present invention is connected to the CPU and
A coprocessor that executes a coprocessor-dedicated operation on behalf of the coprocessor decodes a coprocessor instruction sent from the CPU via an external data line, and the instruction is an instruction that outputs the execution result to an external main storage device, etc. an instruction decode circuit that determines whether or not the instruction exists and outputs the co-grossessor internal firmware start address and the load number of operands for the instruction; and firmware that the instruction decode circuit outputs when an instruction is input. A stack memory capable of reading and writing simultaneously stores the start address and the number of operands to be loaded, and also the operand data on the external data line directly with respective identification signals when reading the operands in a FIFO format, and a queue control unit that monitors instructions and operands, identifies the instructions and operands, and controls updating and writing of pointers in the stack memory; and a stack that outputs a difference between a write pointer and a read pointer for the stack memory of the queue control unit. A data amount calculation circuit inputs a control line from the firmware, an identification signal output from the stack memory, and an output from the stack memory, and inputs the firmware start address from the stack memory to the firmware address line. and an instruction control unit that outputs land data to an internal data line, instructs to update the read pointer of the stack memory, and reports completion of internal firmware processing of an instruction that outputs a result to an external main storage device, etc.; Each output of the stack data amount calculation circuit, the instruction decoding circuit, and the instruction control unit is inputted, and a busy signal is sent to the CPU when the stack memory is full or when an instruction is issued to output the result externally. The device includes a busy control section that stops the pinot signal when the stack memory becomes empty or when the result can be output to the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 10 is an external address line that notifies the coprocessor that the CPU has sent an instruction and a land to the coprocessor.

11 is an instruction from the CPU to the co-processor and the fourth
External data line that sends out land, 1 is external data line 11
an instruction decoding circuit that analyzes from the above co-processor instruction whether or not to output the internal firmware start address of the instruction, the number of loads on the land, and the execution result to the outside;
20, 21, and 22 are firmware start addresses inside the coprocessor output from the instruction decoding circuit 1, respectively.

This is an instruction identification signal indicating that the instruction outputs the number of operand loads and execution results to the outside. Also, great-great-rei drop 2
When inputting the command, enter the firmware start address 20 and the operand load number 21.

When reading operands, the stack memory 3 monitors the external address line 10 and stores the operand data on the external data line 11 with each data identification signal 23 in FIFO format, and reads the coprocessor instruction and its operand. A queue control unit performs identification, update of the pointer of the stack memory 2, and write control, 23 is a data identification signal used for selecting input data of the stack memory 2, etc., 24 is a write enable signal for the stack memory 2, 25 and 2
6 is a write pointer and a read pointer of the stack memory 2, respectively; 4 is a stack data amount calculation circuit that outputs the difference between the write pointer 25 and the read pointer 26; 34;
is the number of valid stack data output by the stack data amount calculation circuit 4, 5 is the number of operand data 32 of the co-processor instruction being executed and the number 34 of valid stack data controlled by the firmware, and the firmware start address 31 and the fourth A command control unit performs control for sending land data 33 into the co-processor, control for the queue control unit 3, and busy control; 301, 31, 32 and 33 are data identification signals output from the stack memory 2; Firmware start address.

These are the number of operand loads and operand data.

12 and 13 are the firmware address line and internal data line inside the co-processor, respectively, and 7 and 8 are the firmware address line 12 and the internal data line 1, respectively.
A driver that outputs the contents of stack memory 2 to 3, 35
and 36 is an output permission signal for controlling the driver 7.8;
1 is a firmware control signal from which the firmware notifies the instruction control unit 5 that internal processing has ended and data has been read;
42 is a status signal that notifies the firmware from the instruction control unit 5 of firmware start and end of operand data; 6 is a busy control unit that generates a busy signal that informs the CPU whether or not a co-processor instruction can be sent; 37 outputs the result to the outside when including t-+-FX.
3 is a queue control signal that instructs the queue control unit 3 to update the pointer from the instruction control unit 5.

FIG. 2 is a diagram showing the data format stored in the stack memory of the present invention. In FIG. B is the firmware start address when the co-processor instruction is executed by the firmware inside the co-processor.

C indicates the load number of operands used in the co-processor instruction, and D indicates operand data.

Next, the operation of this embodiment will be explained based on FIGS. 1 and 2.

The queue control unit 3 constantly monitors the external address line 10, and starts operating when a co-processor command or operand is sent from the CPU to the co-processor.

When the Co-Zorocessor command is sent, the queue control unit 3
sends a data identification signal 23 indicating a co-processor instruction to the instruction decode circuit 1 and stack memory 2 to notify that a co-processor instruction has been input. The instruction decoding circuit 1 inputs a co-processor instruction on an external data line 11, and inputs a firmware start address 20 for starting the corresponding co-processor instruction routine on the instruction execution firmware inside the co-processor and the corresponding code. - Outputs the land load number 21 to O, which indicates the number of times the CPU divides and sends out operands, which is calculated from the number of operand data required by the processor instruction. At the same time, the queue control unit 3 outputs a write permission signal 24 to the stack memory 2.

On the other hand, when the stack memory 2 receives the write permission signal 24, it uses the data identification signal 23 as input data as shown in FIG.
As shown in a), the data identification signal A indicating the co-processor instruction, the firmware start address B, and the number of operand loads C are selected, and the write pointer 2 of the queue control unit 3 is selected.
Store it at the address indicated by 5. When the write operation is completed, the queue control unit 3 increments the internal write pointer by 1 and prepares for the next write operation.

Also, if operand data is sent.

The queue control unit 3 sends a data identification signal 23 indicating operand data to the stack memory 2.

It notifies that operand data has been input and outputs a write permission signal 24. When the stack memory 2 receives the write permission signal 24, it uses the data identification signal 23 to select the data identification signal A/ indicating operand data and the external data line 11 as input data, as shown in FIG. 2(b). Operand data D is selected and stored at the address indicated by the write pointer 25 of the queue control unit 3. When the write operation is completed, the queue control unit 3 changes the internal write pointer to +
1 and prepare for the next write operation.

Co-processor instructions and operand data input into the stack memory 2 are controlled by an instruction control unit 5.

The co-processor instruction decode signal or operand data stored at the address indicated by the signal 26 indicating the read pointer output from the queue control unit 3 is constantly output from the stack memory 2, and is detected by the instruction control unit by the data identification signal 30. 5 determines which data it is. When the output of stack memory 2 is an instruction decode signal.

The instruction control unit 5 sends an output permission signal 35 to the driver 7 to output the firmware start address 31 to the firmware address line 12, and activates the firmware inside the co-processor using the status signal 42. .

The instruction control unit 5 also calculates the effective stack data number 34 indicating the difference between the write pointer 25 and the read pointer 26 calculated by the stack data amount calculation circuit 4.

Compare the operand load number 32 output from the stack memory 2, and if all the operand data to be used has been stored, the status signal 42 is used to notify the firmware inside the co-processor that the operand load is finished. report.

After outputting the firmware start address, the instruction control unit 5
Using the queue control signal 43, the queue control unit 3 increments the read pointer by 1 and outputs the next co-processor instruction or operand data.

When the internal firmware of the processor receives the status signal 42 indicating the completion of operand loading from the instruction control unit 5, it uses the firmware control signal 41 to notify the instruction control unit 5 of data read. The instruction control unit 5 sequentially outputs operand data 33 corresponding to the number of firmware loads of the co-processor instruction being executed, which is held internally, from the driver 8 to the internal data line 13 in response to an output permission signal 36. At this time, the read I/R 26 is controlled by the queue control section 3 in accordance with the queue control signal 43 from the instruction control section 5. After outputting all operands, the instruction control unit 5
stops execution until a firmware control signal 41 indicating the end of internal processing is received.

It then moves on to the fire co-processor command control.

Next, the control caused by the difference in the stack amount of the stack memory 2 will be explained.

When there is no valid data in the stack memory 2, that is, when the number of valid stack data 34 is zero.

The command control unit 5 is stopped. At this time, when a co-processor instruction is input from the CPU, the firmware start address and operand load number of the instruction are input to the stack memory 2, and the write pointer is incremented by 1. At the same time, the instruction control unit 5 outputs the firmware start address written in the stack memory 2 to the firmware address line 12.

Boots up the internal firmware. At this time, the operand load number is held in the instruction control unit 5. After that, operands are sequentially sent from the CPU to the stack memory 2.
At the same time, the write pointer is updated and the number of valid stack data 34 increases. When the number of valid stack data 34 satisfies the number of operand loads, the instruction control unit 5 notifies the internal firmware of the end of the land load, and the firmware becomes ready to use the operand data.

On the other hand, if there is valid data in the stack memory 2, the instruction control unit 5 is in a state of waiting for the internal firmware to complete processing. When the firmware control signal 41 indicating the end of processing is received from the firmware, the instruction control unit 5 outputs the start address of the next co-processor instruction, and at the same time uses the status signal 42 to activate the firmware to start executing the next instruction. At the same time, the completion of operand loading is reported. Therefore, the firmware can immediately execute the next co-processor instruction.

Next, the case when the stack memory 2 is full will be explained.

The bino control unit 6 constantly inputs the data identification signal 23 outputted by the queue control unit 3 and the valid stack data number 34 outputted by the stack data amount calculation circuit 4, and inputs the data identification signal 23 outputted by the queue control unit 3 and the valid stack data number 34 outputted by the stack data amount calculation circuit 4, and inputs the data identification signal 23 outputted by the queue control unit 3 and the valid stack data number 34 outputted by the stacked data amount calculation circuit 4. Monitoring availability. If a certain co-processor instruction is input and the number of valid stack data 34 at that time is close to the total address of stack memory 2, then add the co-processor instruction input next and the maximum number of operand loads attached to that instruction. When it is determined that the stack memory 2 will overflow, the busy control unit 6 outputs a pinot signal 40 to the CPU to prevent the primary co-processor instruction from being output from the CPU. After that, when the stack memory 2 becomes empty due to processing by the co-processor's internal firmware, the busy signal 40 is turned off, and the CPU starts processing the next co-processor.
Processor instructions can be output.

Finally, the case where a co-processor instruction for outputting a processing result to the outside is input from the CPU will be described.

At this time, the CPU must take over the processing results.
Furthermore, since there is a possibility that the processing result of the current instruction will be used as operand data for subsequent co-processor instructions, the CPU needs to be stopped until the end of this instruction.

The instruction decoding circuit 1 decodes the co-processor instruction on the external data line 11, and the decoding result is validated by the data identification signal 23 from the queue control unit 3.
Moreover, if the instruction is an instruction to output a processing result to the outside, the instruction decoding circuit 1 outputs an instruction identification signal 22 to the busy control section 6 to notify the input of the instruction to output the processing result to the outside. The busy control unit 6 outputs a busy signal 40 to the CPU to suppress the receipt of processing results and the output of the next co-processor instruction. Meanwhile, the co-processor internal firmware sequentially executes the co-processor instructions stored in the stack memory 2. Each time the instruction control section 5 receives a firmware control signal 41 indicating the end of instruction internal processing from the firmware, the instruction control section 5 increments the read pointer 26 by 1 with the queue control signal 43 for the queue control section 3.

When the execution of the instruction to output the last stored processing result to the outside is completed, the stack memory 2 becomes empty, so the number of valid stack data output by the stack data amount calculation circuit 4 is 34.
becomes zero. At this time, the instruction control unit 5 is activated by the busy control unit 6.
Upon receiving this, the busy control unit 6 turns off the busy signal 40 and allows the CPU to receive the processing result and input the next command. do.

As described above, this embodiment provides a FIFO-type stack memory and immediately stores instructions and operands from the CPU to the co-processor in the data format of an internal firmware start address and operand data in a stackable manner.

The CPU can now execute the next co-processor instruction or other instructions without the wait time required to execute the co-processor instruction, improving the processing power of the CPU.

Busy control in the firmware routine inside the co-processor is no longer necessary, and since the co-processor instruction to be executed is already held in the stack memory, the next co-processor instruction can be executed without any free time. Ability can be improved.

〔Effect of the invention〕

The present invention stores instructions and operands in a stackable FIFO.
By storing the instructions and operands in the stack memory in the above format, even when internal processing is currently being executed, instructions and operands from the CPU can be received one after another, thereby improving the processing capacity of the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a diagram of the data format stored in the stack memory in FIG. Explanation of symbols: 1... Instruction decoding circuit, 2... Stack memory, 3... Queue control unit, 4... Stack data amount calculation circuit, 5... Instruction control unit, 6... Busy Control unit, 7, 8...driver, ]o...external address line. 11... External data line, 12... Firmware address line, 13... Internal data line, 20... Firmware start address, 21... Operand load number. 22... Command identification signal, 23... Data identification signal. 24...Write permission signal, 25...Write pointer. 26... Read pointer, 31... Firmware start address, 32... Operand load number, 33...
... Opera/do data, 34... Number of valid stack data. 35.36... Output permission signal, 37... Busy control signal, 40... Busy signal, 41... Firmware control signal, 42... Status signal, 43... Queue control signal. Figure 2

Claims (1)

[Claims] 1. In a co-processor that is connected to a central control unit and executes a co-processor-dedicated operation on behalf of the central control unit, the co-processor decodes a co-processor instruction sent from the central control unit via an external data line and reads the instruction. an instruction decoding circuit that determines and outputs whether or not the instruction is an instruction that outputs an execution result to an external main storage device, etc., and also outputs a firmware start address within the co-processor and the number of loaded operands for the instruction; At the time of inputting an instruction, the firmware start address and the number of loaded operands output by the instruction decoding circuit are simultaneously read and written, and when reading an operand, the operand data directly on the external data line is stored in FIFO format with respective identification signals added. a queue controller that monitors instructions and operands from the central controller to the coprocessor, identifies instructions and operands, and controls updating and writing of pointers in the stack memory; a stack data amount calculation circuit that outputs the difference between a write pointer and a read pointer for the stack memory; a control line from firmware, an identification signal outputted by the stack memory, the number of operand loads, and an output of the stack data amount calculation circuit; and outputs the firmware start address from the stack memory to the firmware address line and the operand data to the internal data line, and outputs an instruction to update the read pointer of the stack memory and outputs the result to an external main storage device, etc. inputs each output from an instruction control unit that reports the end of internal processing of the software, the stack data amount calculation circuit, the instruction decoding circuit, and the instruction control unit, and outputs the result to the outside when the stack memory is full or a busy control unit that sends a busy signal to the central control unit when an instruction is given to the central control unit, and stops the busy signal when the stack memory becomes free or when it is possible to output a result to the outside. .