JPS6363224A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To correct the phase of a signal with phase distortion in a wide frequency range by varying the frequency of a master clock signal in a PLL circuit formed with a phase comparison part and a pulse generation part that can control a frequency. CONSTITUTION:The titled circuit is constituted of the phase comparison part 10 and the pulse generation part 50 that can control a frequency. The phase comparison part 10 consists of an FF circuit 20 and a 1st gate circuit 40, while the pulse generation part 50 consists of a counter 60, a master clock generator circuit 70, an FF circuit 80, an FF circuit 90 and a 2nd gate circuit 100. Said FF circuit 20 is comprised by vertically connecting a type D flip flop circuits FFs 1 and 2, and a Q output terminal 83 to which the FF circuit 80 outputs a signal with corrected phase distortion is connected to the data input terminal 21 of a first staged FF1 in said circuit 20. The Q output terminal 23 of the first-staged FF1 is connected to the data input terminal 25 of a second-staged FF2.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is a digital PLL (phase-locked loop).
(Phase Locked Loop) circuit.

<Conventional technology> Conventionally, PLL circuits are based on analog circuits,
A crystal synchronous oscillator system is known.

Further, as a digital PLL circuit, one using a shift register is known.

<Problems to be solved by the invention> Analog circuit type PLL circuits and crystal synchronous oscillator type PLL circuits can only be used for a specific frequency, and when the frequency is changed, the PLL itself must be readjusted. The problem is that it doesn't. Further, these PLL circuits have a large number of component parts, and there is a problem that the cost is high.

On the other hand, a digital PLL circuit using a shift register is
Since the number of circuit components is large, the critical bus becomes long, and there is a problem in that the upper limit of the frequency of the master clock is defined.

The present invention has been made in view of the problems of the prior art described above, and it is an object of the present invention to provide a digital PLL circuit having a wide applicable frequency range.

Means for Solving the Problems> A digital PLL circuit according to the present invention that achieves the above object is composed of a first flip-flop circuit and a first gate circuit in which m stages are cascaded, where m is an integer of 2 or more. A frequency control circuit comprising a phase comparator, an n-bit counter, a master clock generation circuit, a second flip-flop circuit, a third flip-flop circuit, and a second gate circuit, where n is an integer of 2 or more. and a pulse generator.

However, in the first flip-flop circuit, one of the signal to be corrected for phase distortion and the output signal of the second flip-flop circuit is given to the clock input terminal of each stage, and the other is given to the data input terminal of the first stage. This is the given circuit.

The first gate circuit inputs the output signal of each stage of the first flip-flop circuit, and when the output signal of the second flip-flop circuit has a phase lag in continuous m recovery with respect to the signal to be corrected for phase distortion. outputs a first signal of a specific logic level, and when the output signal of the second flip-flop circuit lags behind the signal to be corrected for phase distortion by more than m consecutive times or leads by more than 'am times consecutively; is also a circuit that outputs a second signal of the same specific logic level.

The master clock generation circuit is a circuit that generates a master clock signal having a period of 2-'' of the nominal period of the signal to be corrected for phase distortion.

The counter has a ripple carry output terminal, a data input terminal, and a load input terminal, the master clock signal is applied to the clock input terminal, and the first clock signal is applied to the data input terminal.
This is the circuit to which the first signal from the gate circuit is applied.

The second flip-flop circuit has a data input terminal supplied with an output signal of the n-th bit of the counter, and a clock input terminal supplied with an output signal of the n-1 bit of the counter, so that a phase distortion of the output signal is corrected. This is a circuit that outputs .

The third flip-flop circuit is a circuit whose data input terminal is supplied with the ripple carry signal of the counter and whose clock input terminal is supplied with the mask clock signal.

The second gate circuit inputs the second signal from the first gate circuit and the output signal of the third flip-flop circuit,
This circuit provides a load command signal corresponding to the output signal of the third flip-flop circuit to the load input terminal of the counter when the second signal is at a specific logic level.

<Embodiment 1> An embodiment of a digital PLL circuit according to the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a digital PLL circuit, and the digital PLL circuit is roughly divided into a phase comparator 10 and a frequency controllable pulse generator 50. Further, the phase comparator 10 includes a first flip-flop circuit 20 and a first gate circuit 40. Further, the pulse generation section 50 includes a counter 60, a master clock generation circuit 70, a second clock generation circuit 80, and a third pulse generation circuit 80.
flip-flop circuit 90 and second gate circuit 10
It is composed of 0.

In this embodiment, the first flip-flop circuit 20 has m=2
That is, two D-type flip-flop circuits FFI and FF2 are connected in series, and the data CD of the first stage FFI is
) A Q output terminal 83 is connected to the input terminal 21 from which the second flip-flop circuit 80 outputs the signal 5 whose phase distortion has been corrected. The Q output terminal 23 of the first stage FFI is connected to the data CD) input terminal 25 of the second stage FF2. First stage and second stage FFI, FF2 clock (CL
K) Input terminals 22 and 26 are commonly used for signal 2 to be phase distorted.
is connected to terminal 3, where is input.

The first gate circuit 40 includes an AND gate 41 and three NA
It is composed of ND gates 42, 43, and 44. A
The two input terminals 41a and 41b of the ND gate 41 are connected to the i output terminals 24 and 28 of the first stage and second stage of the first flip-flop circuit 20, respectively.

The output terminal 41e of the AND gate 41 is connected to the data (D2) input terminal 62 of the counter, and the first signal 41e is connected to the data (D2) input terminal 62 of the counter.
Outputs 5. The two input terminals 42a and 42b of the NANO gate 42 are connected to the Q output terminals 23 and 27 of the first stage and second stage of the first flip-flop circuit 20, respectively. In addition, the two input terminals 4 of the NAND gate 43
The first and second stage stone output terminals 24 and 28 of the first flip-flop circuit 20 are connected to 3a and 43b.

Furthermore, the output terminal 42C14 of both NAND gates 42 and 43
3C is an input terminal 44a of the NAND gate 44;

44b. The output terminal 44c of this NAND gate 44 serves as a NAND gate circuit 100.
It is connected to one input terminal 101 of the D gate and outputs the second signal 46.

In this embodiment, the counter 60 is a 4-bit counter with n=4, and has a clock (CLK) input terminal, a data (Ql to Q4) output terminal, and a ripple carry (CA)
The output terminal 71 of the master clock generation circuit 70 is connected to the clock input terminal 61 of the counter 60, which has an R) output terminal, a data CDI to D4) input terminal, and a load (LOAD) input terminal, and the output terminal 71 of the master clock generation circuit 70 is is input.

Since n=4, the master clock generating circuit 70 generates a nominal frequency signal 72 of the signal 2 to be corrected for phase distortion.

The second flip-flop circuit 80 is of D type,
The 4th bit data (D4) output terminal 64 of the counter 60 is connected to the data (D) input terminal 81, and the 3rd bit of the counter 60 is connected to the clock (CLK) input terminal 82.
A bit-th data (D3) output terminal 63 is connected. Further, the Q output terminal 83 is connected to the output terminal 4 as a digital PLL circuit, and outputs a signal 5 whose phase distortion has been corrected.

The third flip-flop circuit 90 is also of D type,
The ripple carry output terminal 65 of the counter 60 is connected to the data (D) input terminal 91, and the clock (CLK
) The output terminal 71 of the mask clock generation circuit 70 is connected to the input terminal 92.

The second gate circuit 100 is a NAND gate, and has two input terminals 101 and 102, respectively, an output terminal 44C of the NAND gate 44 of the first gate circuit 40, and a Q output terminal 93 of the third flip-flop circuit 90. is connected. Output terminal 103 of second gate circuit 100
is connected to the load input terminal 66 of the counter 60 and provides a load command signal 104 to the counter 60.

The operation of the digital PLL circuit shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.

Note that FIG. 2 mainly shows the operation timing up to the pull-in, and FIG. 3 mainly shows the operation timing after the pull-in. Also, Fig. 2.

In FIG. 3, the mark C in the count contents indicates that the load input is at a low level.

The FFI in the first flip-flop circuit 20 corrects the phase distortion applied from the second flip-flop circuit 80 to the data input terminal 21 every time the signal 2 to be corrected for phase distortion is applied to the clock input terminal 22. Latch signal 5. That is, when the phase difference between the two signals 2.5 is compared and the signal 5 corrected for zero phase distortion is ahead of the signal 2 to be corrected for phase distortion, the Q output of the FFI is at a high level (logic "1"). ”), and vice versa, low level (logic “0”).
). 0FF2 in the first flip-flop circuit 20
latches the Q output of the FFI every time the signal 2 to be corrected for phase distortion is applied to the clock input terminal 26. That is,
FF2 is the two signals 2 and 5 at the time one clock ago.
If the signal 5 whose phase distortion was corrected one clock ago is ahead of the signal 2 whose phase distortion is to be corrected, the Q output becomes high level (logic "1"). Become,
In the opposite case, it becomes a low level (logic "0°").

Therefore, the AND gate 41 of the first gate circuit 40 is
When the phase distortion-corrected signal 5 is behind the phase distortion target signal 2 two or more times in a row, a high-level (logic "L") signal 45 is output, and the counter 60's D
Raise the power of two people to a high level. On the other hand, the first gate circuit 4
0 NAND gate 44 outputs the phase distortion corrected signal 5.
is delayed in phase by two or more consecutive times from signal 2 to be corrected for phase distortion, and conversely, when signal 5 whose phase distortion has been corrected is delayed by two or more consecutive times in phase from signal 2 to be corrected for phase distortion. , the signal 46 is at high level (logic “1”) in both cases.
Output. As a result, the second gate circuit 100 opens, and a signal from the Q terminal 93 of the third flip-flop circuit 90, which will be described later, is applied to the load input terminal 66 of the counter 60.

In the third flip-flop circuit 90, the counter 60 is
A signal obtained by shifting the ripple carry signal which becomes high level by one bit when counting "15" by one bit of the master clock signal 72 is output to the Q terminal 93, and this signal is applied to the second gate circuit 100.

Since the counter 60 is a 4-bit counter, basically Q
The master crofter signal 72 frequency-divided by 2 is output to the 1 output terminal, and the frequency-divided signal 72 is similarly divided by 4 to the Q2 output terminal.
The output terminal appears and the pulse of the master clock signal 72 is output to 1.
When 6 items are input, the count becomes "15". Therefore,
Since the output signal 5 of the second flip-flop circuit 80 is obtained by latching the Q4 output of the counter 60 with the Q3 output, it is basically a signal obtained by dividing the master clock signal 72 by 16, and its period is determined by phase distortion correction. It corresponds to the nominal period of signal 2 of interest.

However, the counter 601; If data input terminals D1 to D
4, and all other bits except the D2 input terminal 62 of the second bit are kept at a constant low level. Therefore, the load input terminal 66
When the D2 input terminal 62 becomes a low level, a count "2" is set if the D2 input terminal 62 is a high level, and a count "0" is set if the D2 input terminal 62 is a low level. When the load input terminal 66 is at a high level, the count of the counter 60 is "
Repeats from 0 to 15.

From the above, ■ the first gate circuit 4 applied to the D2 input terminal 62;
If the first signal 45 from 0 is at a high level and the second signal 46 that controls the second gate circuit 100 that outputs the load command signal 104 is at a high level, the counter 60 outputs the master clock signal 72. When 15 pulses are input, the count becomes "15", and the output signal 5 of the second clip-flop circuit 80 becomes the mask clock signal 72 divided by 15. This is a case where the output signal 5 of the second clip-flop circuit 80 is delayed in phase by two or more consecutive times than the signal 2 to be corrected for phase distortion, and the frequency division of the mask clock signal 72 is changed from 16 to 15. As a result, the phase delay is increased by 7201 bits of the mask clock signal.

■ If the first signal 45 applied to the D2 input terminal 62 is at a low level and the second signal 46, which is the input of the gate 100 that outputs the load command signal 104, is at a high level, the counter 60 outputs the master crofter signal. When 17 pulses of 72 are input, the count becomes "15",
The output signal 5 of the second clip-flop circuit 80 is obtained by dividing the master clock signal 72 by 17. This is a case where the output signal 5 of the second flip-flop circuit 80 is delayed in phase by two or more consecutive times than the signal 2 to be corrected for phase distortion, and the frequency division of the mask clock signal 72 is from 16 to 17.
By delaying the frequency division, the phase lead is corrected by one bit of the mask clock signal 72.

■ When the second signal 46 is at a low level and the load command signal 104 is not given, the counter 60 counts "15j" when 16 pulses of the master crofter signal 72 are input, and the second clip-flop circuit 80
The output signal 5 is obtained by dividing the master black signal 72 by 16. This is a case where the output signal 5 of the second flip-flop circuit 80 has a phase delay and a phase lead within one time or less relative to the signal 2 to be corrected for phase distortion, and the signal 5 is in a free-running oscillation state. It is in.

■ As a result of the counter control described in ■, ■, and ■ above, the output signal 5 of the second clip-flop circuit 80 follows the signal 2 to be corrected for phase distortion within one phase delay and one phase lead. Therefore, it can be used as a PLL output signal. Note that if you increase the frequency of the mask clock signal 72, that is, if you increase n, it will take longer to pull in the signal, but after the pull-in, the phase difference between the PLL signal 5 and the signal 2 to be corrected for phase distortion will be smaller. Furthermore, if the first signal 45 of the first gate circuit 40 is not only applied to the D2 input terminal 62 of the counter 60 but also applied to the data input terminal so that the count is "3" or more, the pull-in against the phase delay can be reduced. becomes faster.

<Example 2> FIG. 4 shows a modification of the PLL circuit shown in FIG. 1.

The circuit of FIG. 4 is the same as that of FIG. 1 except for the configuration of the first gate circuit 40.

The gate circuit 40 shown in the fourth leap is composed of three IAND gates 42, 43, and 44 and one inverter 47. The combination of the three NAND gates 42, 43, and 44 is such that the output signal 5 of the second flip-flop circuit 80 whose phase distortion has been corrected is more than twice in phase than the signal 2 to be corrected for phase distortion. If there is a delay, or if there is a phase advance two or more times in a row, the second signal 46 which becomes high level is output in both cases.
Among the gates 42.43°44, the NAND gate 43 is
When the output signal 5 of the second flip-flop circuit 80 is delayed in phase by two or more consecutive times than the signal 2 to be corrected for phase distortion, a low level signal is output. Since this corresponds to an inverted signal of the first signal 45 in FIG. 1, the output signal of the NAND gate 43 is passed through the inverter 47 in FIG. 4 to obtain the first signal 45.

An embodiment in which the number of stages is three (m=3) is shown in FIG. 5. In FIG. 5, the pulse generator 50 is the same as that shown in FIG. 1, but the phase comparator IO is different.

The first flip-flop circuit 10 includes three D-type flip-flop circuits FF1. FF2 and FF3 are connected in cascade, and the second
A Q output terminal 83 of a flip-flop circuit 80 is connected thereto. Furthermore, the Q output terminal 23 of the first stage FFI is connected to the data input terminal 25 of the second stage 0FF2, and the Q output terminal 23 of the first stage FFI is connected to the data input terminal 25 of the second stage 0FF2.
The output terminals 27 are respectively connected to the data input terminals 29 of the third stage FF3. Clock input terminal 22 of each stage
26 and 30 are commonly connected to the input terminal 3 of the signal 2 to be corrected for phase distortion.

On the other hand, the first gate circuit 40 includes two three-man power NAND gates 48 and 49, one two-man power NAND gate 44, and one inverter 47.

Each input terminal 4 of one 3-man power NAN D gate 48
8a.

The Q output terminals 23, 27, 31 of each stage of the first flip-flop circuit 20 are connected to 4ab and 48c, respectively, and the signal at the output terminal 48d is low only when all the Q outputs of each stage are at high level. become the level. This indicates that the output signal 5 of the second flip-flop circuit 80 is ahead of the phase distortion correction target signal 2 by three or more times in a row. Each input terminal 49a of the other three-man power NAND gate 49
, 49b, and 49c are connected to the 100 output terminals 24, 28, and 32 of each stage of the first flip-flop circuit 20, respectively, and only when all the 100 outputs of each stage are at high level,
The signal at the output terminal 49d becomes low level. This indicates that the output signal 5 of the second flip-flop circuit 80 is delayed in phase by three consecutive times or more than the signal 2 to be corrected for phase distortion. The first signal 45 that becomes high level only when the output signal 5 of the second flip-flop circuit 80 is delayed in phase by three consecutive times or more than the signal 2 to be corrected for phase distortion is input to the D2 input of the counter 60. is applied to terminal 62. Two-man power NAND gate 44 is two three-man power NAND
D game) NAND the output signals of 48.49 and
If the output signal 5 of the flip-flop circuit 80 is ahead of the signal 2 to be corrected for phase distortion three or more consecutive times in phase, or if it is delayed in phase three or more consecutive times, the second signal 46 becomes high level in both cases. is applied to the second gate circuit 100.

Therefore, if there is a phase lag three or more times in a row, the output signal 5 of the second flip-flop circuit 80 becomes the master clock signal 7.
2 divided by 15; if the phase advances three or more times in a row, the frequency is divided by 17; otherwise, the frequency is divided by 16. As a result, the output signal 5 has a phase delay of 2 and a phase lead of 2 relative to the signal 2 to be corrected for phase distortion.
Follow up within 30 seconds.

When the number m of cascaded stages of the first flip-flop circuit 20 is increased, the followability of the PLL output signal 5 to the signal 2 to be corrected for phase distortion decreases, and the PLL output signal 5 comes to match the average phase. Therefore, depending on the characteristics required for the PLL circuit, m and n
It is sufficient to appropriately select the numerical value of .

In each of Examples 1, 2.3, the signal 2 to be phase distortion corrected is applied to the data input terminal 21 of the first flip-flop circuit 20, and the signal 2 to be corrected for phase distortion is applied to the input terminal ÷4 of the second flip-flop circuit. 80 output signals 5 may be provided. Furthermore, instead of the Q output of the second flip-flop circuit 80, the 100 output can be used.

APPLICATION EXAMPLE FIG. 6 shows an example in which the digital PLL circuit according to the present invention is used in a timing circuit for a self-synchronous decoding circuit in the data transmission field.

In FIG. 6, on the transmitting side TX, transmitting data is inputted to the encoding circuit 6a via the SD terminal, and a transmitting side clock is inputted via the SCK terminal, and an encoded signal 6
b is output to the transmission line as an optical signal by an electric/optical conversion circuit (LED) 7a. On the receiving side RX, an optical signal is received from the transmission path, and an optical-to-electrical conversion circuit (PD) 7b converts it into an electrical signal.

The decoding circuit 3 obtains an extracted signal 8a and an extracted clock 8b from this electrical signal. The extracted clock 8b is generally accompanied by phase distortion. Therefore, the extracted clock 8b is applied to the input terminal 3 of the digital PLL circuit 1, and the clock 8b whose phase distortion has been corrected is obtained from the output terminal 4. By latching the extraction signal 8a by the flip-flop circuit 9 using this clock 8b, data 9a corresponding to the transmitting side data is generated.
get.

<Effects of the Invention> According to the digital PLL circuit of the present invention, it is possible to correct the phase of a signal with phase distortion in a wide frequency range by simply changing the frequency of the master clock signal, and basically it is possible to correct the phase of a signal with phase distortion without any adjustment. I can say that.

Further, according to the present invention, since the circuit is entirely digital, a digital PLL circuit can be manufactured using Ic elements arranged in a gate array with a relatively small number of gates, and there is an advantage that manufacturing is easy and inexpensive.

Furthermore, according to the present invention, a shift register is not required;
Since the number of gates is small, the critical path is shortened, so the upper limit of the frequency of the master clock signal can be set extremely high, and the frequency range of the target signal is extremely wide.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of a digital PLL circuit according to the present invention, FIGS. 2 and 3 are timing charts of the operation of the circuit in FIG. An example circuit diagram, FIG.
FIG. 3 is an explanatory diagram of an application example of the LL circuit. In the drawing, 1 is a digital PLL circuit, 2 is an input signal, 3 is an input terminal, 4 is an output terminal, 5 is an output signal, 10 is a phase comparator, 20 is a first flip-flop circuit, 40 is a first
gate circuit, 45 is a first signal, 46 is a second signal,
50 is a pulse generator, 60 is a counter, 70 is a master clock generation circuit, 80 is a second flip-flop circuit,
90 is a third flip-flop circuit, and 100 is a second gate circuit.

Claims (1)

[Claims] A phase comparator section comprising a first flip-flop circuit and a first gate circuit in m-stage cascade connection, where m is an integer of 2 or more, and n bits, where n is an integer of 2 or more. a counter, a master clock generation circuit, a second flip-flop circuit, a third flip-flop circuit, and a frequency control pulse generation section composed of a second gate circuit; A circuit in which one of the signal to be phase distortion corrected and the output signal of the second flip-flop circuit is applied to the clock input terminal of the circuit, and the other is applied to the data input terminal of the first stage, and the first gate circuit inputs the output signal of each stage of the first flip-flop circuit, and when the output signal of the second flip-flop circuit has a phase lag of m continuous times with respect to the signal to be corrected for phase distortion, 1 signal, and the output signal of the second flip-flop circuit lags behind the signal to be corrected for phase distortion by m or more consecutive times or leads the signal to be corrected for phase distortion by m or more consecutive times. The master clock generating circuit is a circuit that generates a master clock signal having a period of 2^-^n which is the nominal period of the signal to be corrected for phase distortion, and the counter outputs a ripple carry signal. a terminal, a data input terminal and a load input terminal, the clock input terminal being supplied with the master clock signal and the data input terminal being supplied with the first clock signal.
The second flip-flop circuit is a circuit to which the first signal from the gate circuit of the counter is applied, and the second flip-flop circuit is applied to the data input terminal of the n-th bit output signal of the counter, and to the clock input terminal of the n-1 bit of the counter. The third flip-flop circuit is supplied with the bit-th output signal and outputs a phase-distorted signal, and the third flip-flop circuit has a data input terminal supplied with the ripple carry signal of the counter and a clock input terminal with the master signal. a circuit to which a clock signal is applied; the second gate circuit inputs the second signal from the first gate circuit and the output signal of the third flip-flop circuit;
A digital PLL circuit, characterized in that the circuit provides a load command signal corresponding to the output signal of the third flip-flop circuit to the load input terminal of the counter when the second signal is at a specific logic level.