JPS6362826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides self-clocking information composed of a rectangular wave pulse train with signal inversion intervals at predetermined intervals from a (1,0) digital data signal and a control signal added thereto. The present invention relates to a modulation method for obtaining a signal (hereinafter referred to as SCI), and particularly relates to a modulation method that allows easy discrimination between data signals and control signals during demodulation.

In computers and data processing devices, when information stored in a storage element is stored on a storage medium such as a magnetic tape, the information is first gated by a timing clock (or readout clock) and transferred from the storage element. Information is extracted. The information string extracted in this way is a digital data signal of "1" or "0", and normally the timing clock and this digital data signal are recorded on separate magnetic tape tracks and reproduced. Since this method requires two tracks, one for digital data and one for timing clock, in order to increase the effective data capacity of magnetic tape, etc., the timing clock and digital data signals are combined and modulated using various modulation methods. to create an SCI signal and use this
A method is used in which an SCI signal is recorded and reproduced on a magnetic tape, and the original digital data signal is demodulated from the reproduced SCI signal.

FIG. 1 is a current waveform diagram when recording SCI signals using various modulation methods. In the figure, T is the time area corresponding to the area of magnetic tape in which each data bit is recorded. In the FM modulation system shown in FIG. 1a, the signal is inverted at the center when the data bit is "1" and at the boundary between the data bits. In the MFM (Modified FM) modulation method shown in FIG. 1B, the signal is inverted at the center when the data bit is "1" and at the boundary between the data bits that continue to be "0". Then,
There are two signal inversion intervals: 0.5T and T for the FM modulation method, and T, 1.5T, and 2.0T for the MFM modulation method.
There are three ways. That is, the above FM or MFM
According to the modulation method, regardless of the data sequence,
The signal inversion interval will be specified at a predetermined interval.

In this way, when creating an SCI signal by modulating a data signal so that the signal inversion interval is a predetermined interval, consider adding a control signal.
The control signal may be, for example, a frame synchronization signal when the digital data signal is a pulse code modulation signal of an audio signal. The frame synchronization signal is the following signal. That is, recently, audio signals are sampled, this sampling signal is subjected to pulse code modulation PCM, and recorded on magnetic tape (MFM modulation recording or FM modulation recording).
However, in the case of a multi-track/fixed magnetic head type PCM recording/reproducing device, a predetermined number of digital data D (sampled signals are converted into PCM modulators) as shown in Figure 2. If necessary, an error detection/correction code P is added to the frame signal, and this frame signal is recorded on a plurality of tracks. Therefore, a control signal for synchronizing frame signals is a frame synchronization signal.

Since the frame synchronization signal FR is different in nature from data obtained by sampling an audio signal, it is necessary to distinguish between the two in some way.

For example, it is possible to use a specific fixed pattern for this frame synchronization signal, but in this case there is a possibility that the frame synchronization signal pattern and the data pattern coincide by chance, so the probability of occurrence of such a situation is In order to keep the number of bits small, it is necessary to increase the number of bits of the frame synchronization signal. Therefore,
There are drawbacks such as the information becomes redundant and a demodulation circuit is required to detect such a specific pattern during demodulation.

Therefore, in the present invention, the signal inversion interval based on the frame synchronization signal is made different from the signal inversion interval based on data.

The case of the MFM modulation method will be explained below.

In FIG. 3, section 8 is the same as section 8 in FIG. 1, and is a section corresponding to data. Section 9
~13 is the section corresponding to the frame synchronization signal, and the first bit CF and the last bit CF are “1”.
Similarly, an SCI in which the signal is inverted at the center of the bit, but the middle 3-bit CT is not inverted at all.
The structure is such that a frame synchronization signal is recorded on a magnetic tape or the like as a signal. That is, the signal inversion interval of the frame synchronization signal is 8T ₀ in the illustrated embodiment.
becomes. By using such a modulation method, it is possible to obtain an SCI signal corresponding to a control signal in a form that is clearly distinguished from data.

The above explanation was for the case where there was only one type of control signal different from data, that is, a frame synchronization signal.
In the case of two or more types of control signals, it is conceivable to change the signal inversion interval for each control signal as 6T ₀ , 7T ₀ , 8T ₀ , etc. However, the more types of signal inversion intervals, the more complex the configuration of the demodulation circuit becomes. becomes. Furthermore, when SCI signals are recorded on a magnetic tape, it is not preferable to make the signal inversion intervals close to 6T ₀ , 7T ₀ , and 8T ₀ in consideration of the effects of peak shifts and the like that occur during reproduction. Therefore, in the present invention, the control signal is
The narrow sense control signal is divided into a specific signal that specifies the type of control signal, and the narrow sense control signal is made to correspond to a signal inversion interval of 8T ₀ as described above, and for example, there are three types of control signals. In this case, sections 14, 15, and 16 are made to correspond to a specific signal, and the type of control signal is determined by which section is set to "1" (the other sections are set to "0"). It is a distinction. The specific signals in sections 14 to 16 are modulated using the same modulation method as digital data (therefore, in the case of FIG. 3, the MFM modulation method). In the above explanation, section 1 corresponds to three types of control signals.
One of 4, 15, and 16 was set as "1",
If the specific signal is given as a binary value code, it is possible to distinguish between 2 ³ =8 types of control signals using the three sections 14, 15, and 16.

Although various modulation circuits can be used to generate SCI signals, one embodiment will be described below with reference to the drawings. First, a circuit for modulating normal data into an SCI signal will be explained, and then a circuit for modulating a control signal into an SCI signal will be explained.

Terminal T ₁ contains data DA ₁ in NRZ format, and T ₂
The read clock CK ₁ of this data DA ₁ is
(see FIGS. 6a and 6b). A clock _CK2 , which is a frequency-divided version of the clock _CK1 , is applied to the terminal _T3 . The delay element of the divider circuit allows the clock to
It is assumed that the rising or falling edges of clock CK ₁ and clock CK ₂ do not match, and that they are not synchronized (see FIGS. 5a and 5b). Clock CK ₁ , CK ₂
is input to the circuit 10 , the clocks CK ₃ and CK ₄ as shown in FIG. 5e and f are obtained from the circuit 10 . That is, the circuit 10 is a circuit that creates clocks CK ₃ and CK ₄ that have the same period and phases that are shifted by half a period. This circuit 10 includes D-FF (D flip-flop) 1, 2, inverters 3, 4, 5,
It is composed of AND gates 6 and 7. D-
The Q output of FF1 (see Figure 5C) is the clock _CK1.
is latched at the rising edge of clock CK ₂ , and the Q output of D-FF2 (see Figure 5 d) is D-
The Q output of FF1 is latched at the falling edge of clock _CK2 . And Q of D-FF1 and 2
By combining the outputs as shown in FIG. 4, clocks CK ₃ and CK ₄ can be obtained. Figure 6a
-d, it can be seen that the clock CK ₃ corresponds to the boundary of the data bit section, and the clock CK ₄ corresponds to the center of the data bit.

Now, the data DA ₁ input to terminal T ₁ is D-
Applied to FF11 and latched by clock _CK4 . Therefore, the Q output is as shown in FIG. 6e. And gate 14 has D-FF11
A signal obtained by inverting the Q output of 1 by an inverter 12, a signal obtained by inverting data DA ₁ by an inverter 13, and a clock CK ₃ are input. Therefore, when the data DA ₁ and the Q output of the D-FF 11 are both at the "0" level, the clock CK ₃ passes through the AND gate 14, that is, the data DA ₁ is at the "0" level continuously for two or more cycles of the clock CK ₁ . When this happens, the AND gate 14 outputs the clock _CK3 . Therefore, when the data DA ₁ has consecutive "0" bits, the AND gate 14 outputs a clock signal indicating the boundary of the data bit section.
X ₅ and X ₆ are output.

Furthermore, since the data DA ₁ and the clock CK ₄ are input to the AND gate 15, the data DA ₁
When is at the "1" level, clock _CK4 passes. Therefore, from the AND gate 15, the clocks Y ₁ , Y ₃ , Y ₄ indicating the center of the “1” bit of the data DA ₁ are output.
is output.

Therefore, the OR gate 16 outputs a clock as shown in FIG. 6(f). If this clock is divided by flip-flop 17, its Q output will be
An MFM modulated SCI signal (see Figure 6g) can be obtained.

Now, next we will change the control signal to SCI with a signal inversion interval of 8T ₀ .
A circuit for modulating a signal will be explained with reference to FIG. In FIG. 7, circuits with the same functions as those in FIG. 4 are given the same figure numbers and their explanations will be omitted. The switch circuit 20 is a circuit for specifying the signal inversion interval of the control signal. When the signal inversion interval is set to 8T ₀ , the switches S ₁ and S ₅ are opened, and the switches S ₂ and
Close S ₃ and S ₄ and create the logic 1, 0, 0, 0, 1. The logic 1, 0, 0, 0, 1 specified by the switch circuit 20 is preset in the parallel-in/serial-out type shift register 21 by the load signal _CK5 . And the load signal
CK ₅ is 11T ₀ in synchronization with the falling edge of clock CK ₁ .
When the period becomes “0” level, the clock CK ₁
The logic 1, 0,
0, 0, 1 are read out (see Figure 8a, b, d). This read signal (see Figure 8d) is
When the gate signal CK ₆ (see FIG. 8c) which rises with a period T ₀ delay from the load signal CK ₅ is at the "1" level, it passes through the AND gate 22 and the OR gate 23 and is input to the D-FF 11. At this time,
Since the signal obtained by inverting the gate signal CK ₆ by the inverter 25 is input to the AND gate 24, the data
DA ₁ is never input to the D-FF 11 via the AND gate 24 and the OR gate 23. Now,
The signal input to the D-FF 11 is modulated in substantially the same way as when modulating the data DA ₁ described above, but during the period of modulating the control signal, the “0” output of the inverter 25 is input to the AND gate 14. is applied, the clock _CK3 will not pass through the AND gate 14 even if "0" bits continue. That is, when the control signal (see FIG. 8d) is at the "1" level, the clock _CK4 only passes through the AND gate 15. Thus, the SCI signal with a signal inversion interval of 8T ₀ is modulated with respect to the control signal.
Note that when data DA ₁ is modulated, since the output of the inverter 25 is "1", a modulated SCI signal can be obtained in exactly the same manner as in the case described above. Furthermore, if there are multiple types of control signals, it is clear from the above description that a signal specifying the type may be input to the data side terminal _T1 subsequent to the control signal.

Incidentally, in order to demodulate the signal modulated in this way, the method described in Japanese Patent Application No. 54-29661, which is the original application of this patent application, may be used, but this method is not directly related to the gist of the present invention. Therefore, the explanation will be omitted.

According to the present invention described above, since the control signal is modulated so that the signal inversion interval is different from the signal inversion interval of data, for example, a method of imparting a specific pattern to the control signal may be used. There is no need to increase the number of redundant bits, and during demodulation,
The distinction between data and control signals is also reliable. In addition, when there are multiple types of control signals, instead of varying the signal inversion intervals of the control signals corresponding to the multiple types, it is preferable to use a constant signal inversion interval (for example, 8T ₀ ).
Subsequently, a specific signal that identifies the type of control signal is modulated using the same method as the data modulation method, so when demodulating the signal, only one circuit is required to identify the signal inversion interval of the control signal. (In the previous example, only the identification circuit for the signal inversion interval 8T ₀ is required), which simplifies the configuration of the demodulation circuit.

[Brief explanation of drawings]

Figure 1 is a waveform diagram of SCI signals by various modulation methods, Figure 2 is a diagram showing the relationship between data and frame synchronization signals, Figure 3 is a waveform diagram of a control signal modulated by the method of the present invention, and Figure 4 is a diagram showing the relationship between data and frame synchronization signals. A diagram showing the data modulation circuit, Figures 5 and 6 are its operation waveform diagrams, and Figure 7 shows the data modulation circuit.
Figure 8 shows a data and control signal modulation circuit.
The figure shows its operating waveform diagram. 10 ... Clock generation circuit, 11, 17... Flip-flop circuit, 20... Switch circuit for specifying signal inversion interval, 21... Shift register.

Claims (1)

[Claims] 1 (1, 0) digital data signal is modulated so that the signal inversion interval is a plurality of predetermined intervals,
and modulating the control signal so that the signal inversion interval is a predetermined interval different from the predetermined intervals of the plurality of types, and modulating a specific signal specifying the type of the control signal using the same method as the modulation method for the digital data signal. A digital signal modulation method characterized by: