JPS635637A - Multiplex transmitter and receiver - Google Patents

Abstract

PURPOSE:To allow one station to transmit and receive data with n-stations by providing a light receiving element, an O/E converting circuit, an S/P converting circuit, an output buffer, a reception timing control circuit and a system control circuit. CONSTITUTION:An E/O converting circuit 7 amplifiers a serial signal. By driving an LED 8, said signal is converted into an optical signal, which enters an optical fiber from an optical connector and is transmitted to the other station. The inverse of an SRN, and the inverse of an SDE are inputted to a transmission timing control circuit 4, and the outputs of the inverses of an ISP, an FSP and an SEN are provided. A reception circuit controlling the timing of a P/S converting circuit 3 has a photodiode PD 10, the O/E converting circuit 11 that amplifies and binarizes the optical current, a serial/parallel (S/P) converting circuit 12 converting serial data obtained tn such a way into parallel data and an output buffer 13 outputting the parallel data.

Description

DETAILED DESCRIPTION OF THE INVENTION (2) Technical Field The present invention relates to improvements in optical multiplex transmission equipment used in optical data links.

An optical data link connects two transmitting and receiving stations via an optical fiber, converts a digital signal into an optical signal, and transmits and receives the signal.

It has a transmitting circuit and a receiving circuit. The transmitter circuit is provided with a digital signal in parallel, so it consists of a parallel/serial converter circuit that converts this into a serial signal, an optical transmitter circuit that converts the serial data into an appropriate code and amplifies it, and an LED 1 or LD. .

The receiving circuit includes a PD and APDl that convert optical signals into current.
It consists of an optical receiving circuit that amplifies, binarizes, and shapes these signals, and a serial/parallel converter circuit that converts these signals from serial signals to parallel signals.

The present invention relates to improvement of an optical receiving device among optical transmitting/receiving devices, and a transmitting device will be explained together with the receiving device.

This is because the constitutive action can only be understood if both are explained.

Transmission distance also depends on the type of optical fiber.

Plastic fibers and plastic clad quartz glass core fibers are used. The plastic fiber has PMMA as its core material and can transmit approximately 30 m.

In the case of an optical fiber with a quartz glass core and a plastic cladding, a transmission distance of about 1 km can be achieved.

In any case, it is intended for short distance transmission. For this reason, the light source is often an LED and the light receiving element is an FD, and there is a demand that the light source must be inexpensive.

(a) Prior Art The closest prior art is an optical data link that has already been manufactured and sold by the applicant.

These are Sumilink S, MFII, and MF12 (trade name).

These are full-duplex parallel signal transmission type optical data links that can simultaneously transmit and receive 16-bit parallel signals.

MFll uses plastic fiber and a red light source.
Perform short-distance transmission.

The MF21 uses a quartz-core, plastic-clad fiber and a near-infrared light source to perform medium-distance transmission.

Other than this, there is no difference between the two, and the circuit configuration is the same.

This optical data link connects only two stations A and B. Both have a transmitting circuit and a receiving circuit. Two optical fibers are used in parallel. Data input and output are 1
There are 6 channels.

It can send and receive 16-bit data.

Circuits such as input clamp, parallel/serial conversion, timing control, serial/parallel conversion, and output buffer are integrated into a single CMOS IC. The oscillator that generates clock pulses and the E10 conversion circuit are integrated into one hybrid IC. The O/E conversion circuit is also a single hybrid IC. LED
and PD are housed in one optical connector.

(1) Problems with the Prior Art Such an optical data link has an extremely simple configuration.

However, even though the transmission and reception are one-to-one, there is a drawback that only 16-bit signals can be sent.

Sometimes it is required that one station be able to select and transmit to one of multiple stations. This was not possible with the optical data link described above.

Furthermore, you may want to send a signal of 16 bits or more. When the amount of data to be transmitted increases, the 16-bit transmission/reception capacity may not be sufficient.

In this way, MFll and MF'21 have 16 bits and 1
The disadvantage is that it is not always able to fully meet the demands of diverse users due to the limitation of 1 communication.

00 Purpose It is a first object of the present invention to provide an optical data link that allows data to be transmitted and received between 1 to n stations.

A second object of the present invention is to provide an optical data link that can expand the amount of data that can be transmitted and received.

(4) Configuration The optical transceiver module 1 in the optical data link of the present invention will be explained with reference to FIG.

There are signal input pins Did, Dil to Di15 for inputting 16 channels of input signals in parallel, and these are connected to input clamp 2. Input clamp 2 latches these data, but samples them all at once about every 39 μm.

The parallel signal is converted into a serial signal by a parallel/serial (P/S) conversion circuit 3.

The serial signal is amplified by the E10 conversion circuit 7, and the LED
8, it is converted into an optical signal. This optical signal enters the optical fiber from the optical connector and is transmitted to the other party's station.

SRN to the transmission timing control circuit 4.

Lung input is connected, and ISP, FSP, and SEN outputs are provided. This is the system control circuit 5 that controls the timing of the P/S conversion circuit 3.
, MRS inputs are given.

The oscillation circuit 6 oscillates pulses as necessary.

The receiving circuit includes a photodiode PD1Q, an O/E conversion circuit 11 that amplifies and binarizes this photocurrent, and a serial/parallel (S/P) circuit that converts the serial data obtained in this way into parallel data. Conversion circuit 12 and output buffer 13 for outputting parallel data
Contains such as.

From the output buffer 13, 16 channels of signal output bins D00, . . . , D015 are outputted to the outside. The parallel data is output from the output buffer 13 all at once. The previous output data is held in the output buffer as is until new data is received and updated.

○When the CL terminal 19 is set to "L", the output data is cleared.

Both input and output are at low level or no level. The power supply voltage is rated at 5■. Loreherha, t
m voltage Vcc is about 0.3 times (0.3Vcc) or less. The high level is about 0.7 times vcc (0.7V
cc) That's all.

For simplicity, the high level is expressed as Hlo-level is expressed as L. In the case of data input and output, H is sometimes expressed as 1 and L as 0. Many terminal names are a list of the initial letters of the English words that represent the function, but those with a horizontal line drawn above the letters indicate that the terminal is at a low level and becomes active. In other words, the special function of that terminal is performed when it is grounded.

OCL means a terminal that performs 0output C1ear at L (o-level).

The error detection circuit 15 detects a reception error and outputs a negative pulse to the ERP when an error occurs. When data cannot be received, ERP becomes L.

Reception timing control path f 4 c. Controls the timing of the operation of the S/P conversion circuit 12.

Further, the operation of the S/P conversion circuit 12 outputs a signal to the outside. OTC, RRN input and REN.

It has an RDE output. These are used for extended communication.

The address detection circuit 16 is provided for address communication. 4-bit address setting input terminal AO
, AI, A2, A3, and A specifying the number of address bits.
SO1AS1 manpower.

O12 is an output terminal that outputs a pulse synchronized with the parallel output signals Do0 to Do15.

The power supply filter 17 is for cutting noise from the power supply voltage applied from VCC and obtaining a stable power supply voltage.

The CDI lamp 18 indicates the presence or absence of an optical signal. This lamp lights up when receiving a light signal. Carrier Detection India
It is icator. A green LED is used, but the color can be any color.

The input and output connections will be explained.

It goes without saying that input HXL corresponds to output H and L. The output is an open collector transistor. Therefore, when the output is L, the transistor is O
When the N1 output is H, the transistor is turned off.

Since it is an oven collector transistor output, TTL
, Of course it can be connected to CMOS, but relay,
Can directly drive lamps, etc.

Inputs are TTL, 0MO3, and no-voltage contact input. Since the input is raised to the H level by a high resistance, a voltage-free contact can be used as the input.

The input signal is the open/closed state of a switch that has one end grounded. It is at L level when the switch is closed.

When the switch is open, it is at H level.

These inputs and outputs are merely examples.

It goes without saying that other input and output configurations are possible.

The converted serial signal is transmitted through optical fiber. In addition to these 16-bit signals, a parity bit and a stop bit are added to form one data frame. Data frames are transmitted and received.゛1 data frame time is 39 as already mentioned
It is μ type.

FIG. 2 is a diagram showing an example of a data frame.

Each bit is not the 0.1 signal itself, but is DMI encoded.

DMI code (Differential Mark)
Inversion) changes the level for each bit, but when the signal is L, the level is further changed in the middle of one bit. When the signal is H, it is in the middle and the value does not change.

In Fig. 2, the input bit number Di15 is shown above the waveform.
Di14,... was shown. The numbers below are examples of input values for that bit. For the value "0", the value changes in the middle. TH is the time when the voltage is high, and TL is the time when the voltage is low.

In this example, T)l=71. =: lμ I feel anxious.

For the value "1", the value does not change in the middle. The time per bit is written as TB. This is 2μ%.

The reason for DMI encoding will be explained.

The original digital signal to be sent and received is NRZ (NonRe
Also called "turn Zeno". This may continue to be 0, or may continue to be 1. If you send and receive data in this state, the receiving side will not be able to extract the timing. Therefore, some kind of encoding is performed.

DMI code is one of them. This is the beginning of the bit and the level always changes, so timing extraction is easy.

Also, from νζ, looking at the level change in the middle of the period,
It is possible to easily determine whether the value is 0 or 1.

The data bits become serial signals in order from Di15 to DiO. After this is the parity bit. The parity bit indicates whether there is an even number of H or L or an odd number of H or L in the data bit signal.

A stop bit is added after the parity bit. In total, the frame length is approximately 39μ.

In the receiving circuit, a parity check and a stop bit check are performed. This makes it possible to detect the occurrence of an error. When an error occurs, the ERP terminal (usually H
A negative pulse is output from the level). The data received at this time is canceled and the previous data is retained.

a) Types of communication modes The configuration of the optical transceiver module of the present invention has been briefly explained above. However, the meaning of these structures becomes clear only when their operations are explained.

Three communication modes are possible.

I'l:1 communication mode ■Address communication mode ■Extended communication mode Of these, ■ is for transmitting and receiving 16-bit data between two stations x and y, and has the same operation as the optical data link described as the conventional technology. do.

■ can also be called 1:n communication. There are n stations on the other side. The partner station is distinguished by an address. It is called address communication because the destination of data is distinguished by address.

(2) is 1:1 communication, but the data is expanded to multiple times 16 bits.

■ and ■ are new operations.

diameter) 1:1 communication mode I Two identical optical transceiver modules are connected via an optical fiber. - side is X1 and the other side is Y.

X LED and Y PD% X PD and Y LED are connected by an optical fiber.

Set the transmission enable terminal ■ to L level. It is always ready to send.

Since no addresses are used, Ao, A3, ASOlASI
Do not connect anything to . Not connecting anything means H level. Both MSO and MSI are at H level.

In this way, MS0, MSl, Ao, A3, ASo1As
1:1 communication is specified because all 1 ports are at H level.

Transmission from X to Y is represented by arrow A. X's I)t.

When parallel data is input to ~Di15, signals from Di15 to DiO become a serial signal, which is then transmitted with a parity bit and a stop pitch h added thereto.

SDE, MRS, OTC, O(J,, RRN HaHl/ Herte.

Although it is called 1:1 message and one word mode, there are two cases: (a) automatic repeat communication (b) external transmission synchronous communication (by SRH).

The one in Figure 3 has SRN = L, so it becomes automatic repeat communication. In (b), the signal is set to -H, and a synchronization signal is applied from the outside to set SRN = L, and the signal is transmitted only at this time.

FIGS. 6 and 7 show waveforms of the transmitter and receiver in automatic repeat communication. Four waveforms are shown in Figure 6, which are ISP output, SD high power SEN output, and FSP output.
This is the output.

The ISP output has the effect of latching the data of the parallel input terminals Di15 to DiO at the falling edge of the output pulse. At falling edge 30.31 of ISP, the parallel input is latched into input clamp 2.

This becomes serial data in the P/S conversion circuit 3.

SD high output does not mean that there is an output bin,
This is serial transmission data, and can be thought of as a blinking signal for a light emitting diode. In other words, it is the output of the E/○ conversion circuit 7. Since the LED is directly connected, the SD high output does not appear externally.

However, when the data is H, LEr) is turned off, and when the data is L, it is turned on. Of course, the reverse is also possible.

P/S conversion is started immediately, and the data frame starts from the pulse falling edge 32, which becomes serial data in order from Dil5. The reason why this is a falling edge is because the last data frame of the previous data frame is a stop bit and is at H level.

In this example, from Dil5, H, HlL, L, H
It is lined up with l... Since this arrangement depends on the input signal, various combinations are possible.

When the data value is H, the level remains unchanged for 1 bit time (2μ5ec). When the data value is set, the level changes at the center. The level always changes for each bit.

Following the 16-bit data value, parity bit 3
3 is issued. If the number of L or H in the data value is an odd number, it becomes L level, and if the number of L or H is even number, it becomes H level. It is called a parity bit because it indicates the parity of the data value. Of the 17 bits consisting of a data value and a parity bit, the number of L level is always an even number.

Of the 17 bits consisting of the data value and parity bit, H
The number of levels is always an odd number. Depending on the H level,
The level of the signal (of the DMI code) changes. Therefore, for these 17 bits, the level for the first H and the level for the last H are the same.

Here, the first H is Dil5, which is at L level. The last H is Dil, which is also at L level.

Therefore, it is possible to ensure that the stop bit 34 is always at the H level.

The stop bit 34 is a 5μ long pulse.

This can be distinguished from the previous parity bit 33 and the value of Dil5 of the immediately following data frame.

It is limited to an upward pulse of 5μ crown. Since the pulse width for data H is 2μ and the pulse width for data L is 1μ, the stop bit 34 can be clearly distinguished.

The SEN output is configured to output a negative polarity pulse 36 in synchronization with the sending cycle of serial transmission data. In other words, the L level pulse indicates that the 16-bit data and parity bit data have been transmitted. This occurs 3 microns after the rise of stop bit 34 and lasts 1.5 microns. stop bit 34 is 3
This is because it can be recognized if it is a μ expression.

The FSP output becomes L level while transmitting serial transmission data. Returns to high level after outputting the parity bit. Data bits and parity bits are transmitted between falling edge 37 and rising edge 38. The delay time from the rising edge of the stop bit 34 to the rising edge 38 is 0.5 microns.

In this way, the transmission of one data frame is completed.

Since SRN is grounded (L level), as soon as the transmission of one data frame is completed and the next data frame can be transmitted, the ISP output generates a negative polarity pulse again. The end of data frame transmission is known from the SEN output, and an internal circuit applies a negative pulse to the ISP output. This pulse 31 causes the next parallel signal to be latched.

The latched Di15, ..., DiO signals are turned to P
/S conversion and is transmitted as the data value of the next data frame from the pulse trailing edge 35. The FSP output falls at the same time (39).

The operation of the receiving section in the 1:1 communication mode will be explained with reference to FIG.

The RD large input is the serial received data after being received by the PD and subjected to waveform shaping, and the SD ratio output is naturally the same.

However, it takes time to convert the SD ratio output to the LED signal and from the PD received signal to the RD multiplied signal.
Specific output and RD large input, time delayed. This delay is due to electrical circuit delays. Since the optical signal passing through the optical fiber travels at the speed of light, there is almost no time delay.

The RD large input is immediately S/P converted and output to parallel digital data outputs Do15, 'Do14, . . . DoO. Exactly the same content as the RD large input appears on the RDE output.

It consists of an RD large input, a data input from a falling edge 40 that becomes Do15 to a pulse rising edge 41 that becomes DoO, a parity bit 42, a stop bit 43, etc.

The REN output is always at L level. This is used in enhanced communication mode, but has no role in 1:1 communication.

Do15, ... Do converted to parallel digital data
The O signal is held in the S/P conversion circuit, and after receiving the parity bit 42 and checking for errors, it is simultaneously output to the output buffer 13. Synchronizing with this output timing, the OSP output falls 44, and the output timing can be taken out to the outside.

The output buffer 13 continues to hold the same value until the next output timing.

The ERP output generates a negative polarity pulse when an error is detected when receiving serial data. When the carrier cannot be received, it becomes L level. If reception is possible normally, the signal is at H level. In this example, ERP remains at H level, indicating that there is no error.

The RDE output outputs serial received data as is. This is naturally equal to the RD large input.

There is no meaning in the case of 1:1 communication.

When in address communication or extended communication mode, connect to the next module and send serial reception data to it.

In the case of 1:1 communication, the receiving section receives data frames one after another, so it simply converts them into S/P.
It is only necessary to output parallel data to the output buffer 13 in synchronization with the falling edge 44 of the oSP output. At the same time S/P
The conversion circuit is cleared and the output buffer 13 holds the parallel data for one data frame.

In the end, the timing required for the receiver is 44 at the falling edge of oSP.
That means only.

This is provided by monitoring the serial data of the data frame and detecting the stop bit 43. 3 microns after the rise of the stop bit 43, it is known that this is the stop bit, and as a result, the OSP output falls. At the same time, data values are output from the S/P conversion circuit to the output buffer and appear in Do15, . . . , DoO.

The above is a description of the timing of automatic repeat communication when 5RN=L.

Next, the timing of transmission was determined by applying a synchronization signal from the outside. Timing charts of SRN external transmission synchronous communication will be explained with reference to FIGS. 8 and 9.

This is the same in both the 1:1 communication mode and the address communication mode. In the case of 1:1 communication, the difference from the connection shown in FIG. 3 is that the SRN terminal is not grounded and a synchronization signal is applied from outside.

Rather, it is simpler than the automatic repeat communication shown in FIGS. 6 and 7.

If SRN input is H, input data input Di15~D
iO is not latched to input clamp 2. Of course P/S
Not converted. Neither transmission nor reception occurs.

Assume that the SRN input is given as a negative polarity pulse 49 from the outside. As a result, the transmission timing control circuit 4 outputs the input data Di15 to
The input of DiO is clamped and P/S conversion is performed at the same time. This timing is the rising edge 50 of the ISP output.

Since data is latched at the falling edge 50 and P/S conversion starts, the data values of Di15 to DiO are outputted as DMI codes from the SD ratio output falling edge 51.

It is SD ratio output serial transmission data and can also be regarded as an optical signal. The period from falling edge 51 to rising edge 52 is the transmission time of 16-bit data. parity bit 53,
A stop bit 54 follows.

The end 55 of stop bit 54 is not clear.

The transmission of a data frame is started by a pulse 49 of the SRN and ends only once. SD ratio output, H1 stop bit is also H when there is no signal, so stop bit 5
The end of 4 is not clear.

Since the SD ratio output is set to H when there is no signal, the light emitting element is assumed to be turned off at this time. The reason why H is expressed as off and L is expressed as on is to ensure that the LED is off when there is no signal, thereby preventing waste of power and extending the life of the LED.

The SEN output provides a negative polarity pulse 56 at the end of the transmit cycle, ie, after the stop bit. This pulse occurs 3μ after the rising edge of the stop bit.

Even if this pulse occurs, a negative pulse of the ISP output will not occur again. This is because the SRN input is at H level. Transmission is stopped until a negative pulse is input to SRH again.

The FSP output is at L level from fall 57 to rise 58, during which time serial data and parity are sent out.

The timing chart of the receiving section is shown in FIG. 9. The RD large input optical signal is amplified, binarized, and shaped, and the SD ratio output is the same. The falling edge 59 to the falling edge 60 are data bits, 61 is a parity bit, and a stop bit 62 follows. After this, the RD large input becomes H level 63.

The OSP output emits a negative polarity pulse 64 with a pulse width of 0.5 microns 3 microns after the rise of the stop bit 62. This causes parallel outputs Do15 to D in the receiving circuit.
This is synchronized with the timing at which oO is output from the S/P conversion circuit 12 to the output buffer 13.

At pulse 64, data is output. From then on, the same data is held by the output buffer.

The ERD output becomes H level when data can be received, and becomes L level when data cannot be received. Also, when there is an error, a negative polarity pulse is emitted.

At the moment when the RD large input pulse falls 59, the ERP output becomes H level. 24 while receiving and after receiving
It remains at H level with respect to the μ type. From the rising edge 65 to the falling edge 66, it is at H level.

This is because there are no errors.

The RDE output outputs exactly the same as the RD large input to the outside.

(ri) Address communication mode ■ 1: Communication mode between n stations. FIG. 4 shows an example of connection of three stations.

Let one station be X. Like the previous example, this is a single optical transceiver module.

The other station is designated as Y, but since it consists of three modules, they are designated as Yl, Y2, and Y3.

Optical communication is performed between X and Yl, and an optical fiber is provided.

However, only electrical signals are exchanged between Yl and y2, and between Y2 and Y3.

X and Yl have a circuit configuration as shown in FIG.

In other words, it has an LED PD and transmitting and receiving circuits.

However, Y2 and Y3 are reception-only modules. Therefore, it only has data output terminals DoO-DO15L.

There is no input terminal. Do not exchange optical signals. P.D.
l There is no LED. Therefore, there is no PD amplifier circuit or binarization circuit. There is also no LED drive circuit.

In order to distinguish them, X and Yl are called optical transceiver modules U, and Y2 and Y3 are called reception expansion modules ER.

The optical transceiver module U is a large LSI with 58 pins. The circuit configuration is as shown in FIG.

Since the reception expansion module receives electrical signals, P
A D107E conversion circuit is not required. In the circuit shown in Figure 1, there is no transmitter, PD, or O/E conversion circuit.

It has only an S/P conversion circuit 12, an output buffer 13, a reception timing control circuit 14, an error detection circuit 15, a 7F response detection circuit 16, a system control circuit 5, a power supply filter 17, and the like.

Furthermore, the transmission/reception extension module used in the extended communication mode is expressed as EU.

Of the Y stations, only Yl can transmit to the X station. This is the third
This is the same as the case of 1:1 communication explained in the figure. 5 in Yl
Since RN- and L are (grounded), the values of parallel digital manual power DiC) to Di15 are automatically changed in the direction of arrow B.
It is sent repeatedly to the X station. The data received at the X station is output to parallel digital data outputs Do0 to Do15.

What is distinctive is the communication in direction A from station X to stations 71 to 73.

The number of Y stations is 4 or less and 16 or less (5 to 1
Divided into 6 parts. It cannot be more than 17.

Since there are n stations and Y stations, these must be distinguished. For this reason, address setting terminals AO to A3 are provided. 4
Since it is a bit, addresses can be specified for up to 16 modules.

If 1 < n < 4, AO of address setting terminals
Use only 1A1. This gives the address of the module.

In addition, to indicate whether 2 bits or 4 bits are used to specify an address,
There is 1AS1 terminal. If no address is used, both are H.

When using a 2-bit address, set ASl to L. A
SO may remain at H.

When using 4-bit addresses, ASOt LIC is used. ASl is H.

L is prohibited for both ASO and ASI.

In this example, since n=3 and is less than 2 bits, 2-bit addressing is performed. For this reason, Yl, Y
2 and Y3 are both AS1,=L.

Furthermore, different addresses are given to Yl, Y2, and Y3.

YI AO=L A1=L Y2 AO=HA1=L y3 AO=L Al =H. This in turn gives the address 0.1.2.

Regarding the other terminals, the RDE output of Yl, the RD large input of Y2, the RDE output of Y2, and the RD large input of Y3 are only connected.

MSo=H, MS1=H1SDE1MR310TC,O
CL, RRN=H. This is the same as in the case of 1:1 communication.

For the X station, among the 16 bits of data input, Dil and Di
Use O as address input. This is 2 bits or less Y
This is the case when you have a station. If 5<n<16, Di3~D
Use iO as address input.

Therefore, in the former case, the data is 14 bits, and in the latter case,
The data is reduced to 12 bits.

X, acting as a transmitting station, puts the other party's address in the last 2 or 4 bits of the data it wants to send and transmits it.

It propagates through the optical fiber in the A direction and enters the Yl module. The data frame is temporarily stored here, but at the same time, serial data enters from the RDE into the next stage'/2 RD large input. This signal is further transmitted from the RDE output of Y2,
Enter the RD large input of Y3.

In the end, the same serial data is input to all of Yl, Y2, and Y3 at the same time. The signals are sequentially entered into the S/P conversion circuit and held.

After that, Dil and DiO enter. This will give you the address.

Each module compares this address with its own address. There is only one matching module. Only this module Yj outputs data Do15 to DoO to the output buffer circuit 13. Other modules cancel this data.

In this way, digital data is transmitted from the X station only to Yj.

The address communication mode is not much different from the 1:1 communication mode, and the timing charts are the same as the automatic repeat communication shown in FIGS. 6 and 7 and the external transmission synchronous communication shown in FIGS. 8 and 9.

(g) Extended communication mode ■ 1:1 communication, but used when you want to send and receive data of 16 bits or more. Connect m modules to ffl. m units are required for X station and m units are required for Y station.

The number of modules is 2m. The maximum amount of data that can be transmitted and received is 16m bits.

FIG. 5 shows module connections in the extended communication mode.

In the X station, xl, X2, and X3 are connected vertically.

Station Y also has Yl, Y2, and Y3 connected vertically.

xl and Yl are transmitting/receiving modules having LEDlPD as already described. But x2, x3, Y2Y3
does not have LEDlPD. Optical transmitter/receiver circuit (0/E1E
10) No part. As already mentioned, this is the transmission/reception expansion module EU.

In Figure 1, the transmitter/receiver expansion module is connected to input clamp 2.
, P/S conversion circuit 3, transmission timing control circuit 4, system control circuit 5, oscillation circuit 6, S/P
It includes a conversion circuit 12, an output buffer 13, a reception timing control circuit 14, a power filter 17, and an address detection circuit 16.

Both the X station and the Y station have the same mutual connection.

The most important ones are mode setting terminals MS0 and MS1. The X station has a leading module x1 and an intermediate module x2.
, there is a final module x3.

There may be any number of intermediate modules. In the end, there are three types of modules. beginning, middle, and end. A 2-bit mode setting is required to distinguish between the three types.

Assume that m modules are connected vertically.

Set the mode as follows.

(a) First module (1st) MSo=HMS1=L (b) Middle module (2nd, ..., m-1st)
MSO=L MS1=L (C) Final module (mth) MSo=L MSt=H Figure 5 is an example of m = 3, but MS1 of xl and Yl
Power ground, x2.720MS1, MSO power ground, X3, Y
MSQ 3 is grounded.

The connection of the terminals for transmitting the X station will be explained.

SEN is designed to generate a negative pulse in synchronization with the sending cycle of serial transmission data.

Indicates that the data for this module has already been sent.

As mentioned in the 1:1 address communication, SRN is a transmission enable terminal and transmits one data frame when receiving a negative polarity pulse. This is an important terminal.

SEN, SRN, xl, x2, and x3 are cyclically connected.

The SEN and SRN terminals are terminals that provide the possibility of transmission.

In fact, the terminals that transmit the data to be transmitted are the SDK input and the SD output. The connection for this is simple.

These are the configurations of the transmitting units X1 to x3.

Y1 to Y3 also have the same configuration.

Next, the configuration of the receiving sections Y1 to Y3 will be explained.

This is a terminal that transmits transmission data.

However, unlike the address communication mode, the same 16-bit data is not sent to all modules. This makes no sense. Different data must be sent to each module.

Since the RD large input and RDE output send the data as is to the next module, it is not possible to select received data for each module using only this.

After the module holds the received data in the S/P conversion circuit 12, the REN output is set to L level. As a result, 11 of the next module becomes L level, so that the next serial reception data is held in the S/P conversion circuit of the next module.

When 16 bits of data are distributed to all modules, -SP outputs simultaneously output negative polarity pulses, and at the same time, serial data is output as parallel data. This is held in the output buffer 13 and remains unchanged until the next cycle.

In order to operate like this, the signal itself to be sent and received is 1:
1 communication and address communication mode.

These were simply data frames being sent and received.

In the extended communication mode, the - series of signals consists of (,) a start frame (b), m data frames (C), and a stop frame. There are m data frames, which is 16m.
This is natural since bit signals are communicated.

However, in addition to this, a start frame and a stop frame are added before and after the data frame.

Stop frames are different from stop bits.

This is to notify that a series of 16-bit transmission and reception has been completed. The stop frame converts the serial data into parallel data in the receiving section, and outputs the parallel data all at once. Due to the stop frame, the transmitter
The module that can be sent is the first module.

The stop frame is a frame consisting of HLH.

The intermediate L level pulse W provides important timing.

AF the start frame, DF the data frame.

The stop frame is abbreviated as TF. There are three data frames, so write them as DFI, DF2, and DF3.

Start frame AF, stop frame TF.

Attached is Luca, module x1, x2, x3 or Yl,
Y2 and Y3 are no longer equivalent.

The leading module sends out a start frame AF and a data frame D1. The intermediate module sends only data frame D2. The last module sends out a data frame D3 and a stop frame TF.

When written in a general form with m modules, the frame to be sent is xI AF-)-DPI Xm DFm-1-TF. This is possible because modules are distinguished by MSO and MSI.

(b) Transmission operation in extended communication mode In extended communication mode, the timing chart of the transmitting section and receiving section of the first module, middle module, and last module is as follows.
This will be explained with reference to FIGS. 0 to 12.

Transmission direction A will be explained.

Assume that 3×16 bit parallel data is input to xl, x2, and x3. It is simultaneously input to pins DiO to Di15.

FIG. 10 is a timing chart of the leading module. This enhancement stage shows the operation of the transmitter.

The SRN input is a transmission enable terminal. When this becomes L level, one data frame can be sent. Since it is the first module, it can send not only data frames but also start frames AF.

The SRN input is connected to the SEN output of the last module, and by applying a negative polarity pulse 70, the first module X1 becomes ready to start transmitting.

The transmission start pulse 70 to the next pulse 71 provides one cycle of transmission. (AF+DF+TF) is entered here.

How does the transmission start pulse 70 occur? This will be explained in the explanation of the operation of the last module. SD ratio represents the signal sent out.

After 0.3 to 0.8 microns from the fall of the transmission start pulse 70, the start frame AF of the leading module begins to be transmitted.

The start frame AF is a frame with two H pulses 74.75. During this time, it is at L level. D.M.I.
code, and for data 0.1, such a long L
Since there is no level and the H pulse 74 is in the middle, it is easy to identify that this is the start frame.

A certain time after the rise of H pulse 75, the ISP output produces a negative pulse 72. This is parallel human power Di at the falling edge.
This means that the data from 15 to DiO is latched and P/S conversion is started.

The serial data transmission of the first module begins at the falling edge 76. A data frame DFI is sent out.

The transmission of the data frame DPI continues until the parity bit 77 and the stop bit 78 are reached.

The rising edge q of the stop bit provides important timing.

3μ after the rising edge q, the SEN output generates a negative pulse. Since this pulse 83 becomes the input/output of the transmission enable SRN of the next-stage intermediate module x2, the intermediate module can transmit its own data.

However, the data of the first module that remains latched must not be sent out again. This is why there is FSP. The module can send data only when FSP is at L level.

F'SP becomes low level in synchronization with the negative polarity pulse 72 of the ISP output, and 0.5 from the rising edge q of the stop bit.
Stand up after μ. Only between falling 84 and rising 85,
The first module sends data.

The leading module stops functioning at rising edge 85.

The next stage intermediate module X2 uses the negative pulse 8 of the SEN output.
Start by 3.

The sending operation of the intermediate module x2 will be explained with reference to the upper part of FIG.

The negative pulse 83 on SEN is the same as the negative pulse 100 on the SRN input of the intermediate module.

Since SRN has become L level, transmission is possible.

After 0.5-1.5 microns the ISP output produces a negative pulse 101. Parallel data is latched at the falling edge of negative pulse 101. The latched data is converted into serial data in the order of Di15 to DiO and becomes an SD ratio output.

The data of the X2 module is the second data frame D
Configure F'2.

DF2 is from the falling edge 102 to 103.

The rising edge q of the stop bit 106 generates a signal to the next module.

3μ after q, the SEN output becomes negative polarity pulse 107
will occur. This becomes the transmit enable input for the last module.

There is an FSP in order to limit data transmission from the intermediate module between the falling edge 102 and the rising edge q.

It becomes L level at 108 and becomes H level at 109.

The intermediate module is allowed to send data only during periods 108-109.

The falling edge 108 of FSP corresponds to the negative pulse 101 of the ISP output.
The rising edge 109 of FSP is 0.5 μm from the rising edge q of the stop bit. Therefore, the intermediate module can send out its 16-bit signal only once.

SD ratio output of middle module, SDE of first module
Since it is in the input, the SD ratio output DF2 is the SDK input DF2 of the first module (fall 86 to 86')
Through this, the SD ratio output appears. This is the SD in Figure 10.
The specific output is DF'2.

Now, the negative pulse 107 of the SEN output tells the SRN input of the last module that it can be transmitted.

This will be explained using the timing chart of the transmitter shown in FIG.

The SRN input of the last module x3 is negative polarity pulse 1
Receive 26. This is the same as pulse 107.

After 0.5-1.5 pSec, the ISP output produces a negative polarity pulse 127. Parallel input data is latched, and P/S conversion starts sequentially from Di15.

The serially converted data frame DF3 has a falling edge of 1
From 28, stop frame! It lasts for the first 129t.

The FSP output rises 0.5μ after the rise q of the stop bit 130. When FSP is at the L level, this module can send data.

The FSP output becomes L level at 133, but this is due to the ISP
It is synchronized with the negative pulse 127 of the output. .

DF3 is sent out from the falling edge 133 to the rising edge 134.

The stop frames are frames 129 to 131, which have a short negative pulse W in the middle, and the rest are at H level.

Since the H level is long, it can be distinguished from data frames and start frames.

However, since there is a negative pulse W, it is possible to distinguish between no signal and a stop frame.

In addition to this, the negative pulse W has another function.

This is a function that notifies the leading module that one cycle consisting of (AF-)-DF-)-TF) has ended.

5μ after negative pulse W, SEN output becomes negative pulse 13
2. This gives a negative pulse 70.71 to the SRN input of the leading module. This is connected to the SRN input shown in the upper part of FIG.

How does negative pulse 70.71 occur? It becomes clear here.

DF3 of the final module enters the SDK input of the intermediate module from the SD ratio output. This is the data frame DF3 starting from the falling edge 110 of the SDK input in the upper stage of FIG.

Inside the intermediate module, the SDE input is connected to the SD ratio output, so this continues from the falling edge 103 to 104 (becomes the SD ratio output DF3. Stop frame 130
-131 corresponds to periods 104-105.

SD ratio output of middle module, S of first module x1
Connected to DE input. Therefore, DF3 is the 10th
At the SDE input in the figure, it is transmitted to xl as DF3 starting from the falling edge 86'. This is SD inside the first module.
The specific output becomes this DF'3.

In stop frames 130 and 131, the SD ratio output of the leading module is 80.81.

In this way, data input to the module can be sequentially sent out as serial data starting from the first module.

(Off) Reception operation Y1, Y2, Y in extended communication mode
At step 3, 3×16 bit data is received.

The operation timing of the receiving section in the lower row of FIGS. 10 to 12 is followed.

RD large input, optical signal propagated through optical fiber, O
/E conversion, amplification, and binarization.

The SD specific output is exactly the same. However, there is a delay due to the operation of the electronic circuit.

Start frame AF, data frame DFI to DF3
, there is a stop frame TF.

The falling edge 91 to 92 is DFL. The period from falling 92 to 93 is DF2. 93 to 94 are DF3. 94 to 95 are stop frames TF.

The RDE output of the upper module is the RDE output of the lower module.
Since the large D inputs are connected, the large RD inputs of the first module and the large RD inputs of all lower modules appear simultaneously.

The RD large input is the same.

In other words, the RD1RDE of all modules simultaneously transmits the same waveform.

In this way, the operation of the receiving section is simpler than that of the transmitting section.

Assume that the RRN input becomes L level 87 in the first module. This means that it can be received, but
In the enhanced communication mode, the operation of the RRN input is somewhat complicated.

If MSO is at L level, that module starts receiving when the RRN input goes to L level. This applies to the intermediate module (MSQ=L%MS1=L) and the final module (MSO=L1MSI=1()).

Since the first module is MSo=H and MS1=L,
This does not apply. The first module can detect the start frame.

After detecting the start frame, latch the data of the first data frame.

After this, when a stop frame is detected, if RRN is at L level, the latched received data is output.

For the lead module, the RRN input is not needed to receive serial data. When the start frame AF is detected, the leading module receives the first data frame following it.

It is certain that DFl will be sent following the start frame AF, and the first module is determined to receive DPI, so by detecting AF, the first module will detect the falling edge 91 to 92. Latch the data bits in the data frame DFI up to. No RRN input is required to latch data.

After 2.9μ from the rising edge q of the stop bit of DF1, the REN output becomes L level. This becomes the RRN input of the intermediate module. REN output is DF'2, D
It is at L level while F3 and TF are being transmitted.

RE after 4.2μ from the end of stop frame TF
The N output becomes H level.

A negative pulse 99 is output to the oSP output 1 μx after the negative pulse W of TF. This provides timing for outputting parallel data from the S/R conversion circuit to Do0 to Do15. Parallel data is output from the three modules almost simultaneously.

The operation of the intermediate module will be explained with reference to the time chart of the receiving section in FIG. RRN input is falling 1
From 12 to 113, the level is L. This corresponds to 97.9g in FIG.

The value of the data bits of the second data frame DF2 from falling edge 116 to 118 is the S/P of the intermediate module.
Enter the conversion circuit.

2.9 μX after the rising edge q of stop bit 117,
The REN output, which was at H level 121, falls to L level (122).

For the receiving section of the intermediate module, the RRN input is at L level and the REN output is at L level. In such a case, the intermediate module does not receive the next data frame DF3 even though RRN is at L level.

It is a feature of the intermediate module that REN=L takes precedence over RRN=L and reception is prohibited.

When a data frame exists in the first module and the last module, REN=L and RRN=L cannot coexist. The final module performs a simple operation of receiving if RRN=L.

In the first module, RRN is used to receive data.
= L condition is not required.

In the case of intermediate modules, one module must receive one data frame. R
The RN input is the same as the output of the front and rear modules.

The change of the REN output from H to L occurs only in the module that received the data frame.

The module that received the data frame then
The value of RRN input REN output does not change until the next receive cycle.

For this reason, in the intermediate module, the reception condition is given by (i) RRN=L (ii) RE N :H. After receiving one data frame, the condition (11) does not hold.REN:=L
Therefore, reception is prohibited.

The falling edge 122 of the intermediate module's REN output is equal to the rising edge 136 of the final module's RRN input.

In the time chart of the receiving section in Fig. 12, at falling 12
2, the final module is ready to receive. Then, the final data frame DF3 (from falling edge 138 to rising edge 139) is received and subjected to S/P conversion.

After 2.9 μ east from the rising edge q of the stop bit, RE
N output falls. From falling edge 140 to rising edge 141, this is at L level. This is the top module R
Since it is the same as the RN input, at this time the R of the first module
The RN input is at L level.

The RD large input is the same for all modules. Among these, from the negative pulse W of the stop frame, the data DPI is output in parallel from Dol to Do in the first module at 1μ east.
15 and simultaneously produces a negative pulse 99 on the OSP output.

This becomes the negative pulse 124 on the OTC input of the intermediate module. The data DF'2 held in the intermediate module is outputted to the parallel outputs Dol to Do15 with a delay of 0.3 to 0.5 μ from the fall of this pulse, and at the same time, a negative pulse 125 is generated at the oSP output.

This becomes the negative pulse 142 at the OTG input of the final module. This fall occurs 1.3 to 1.5 microns after the fall of the negative pulse W of the stop frame.

After 0.3 to 0.5 μ from the fall of 142, the data DF3 held in the final module is output, and at the same time a negative pulse 143 is generated at the O3P output.

The OSP output is not connected to the head module.

This is because there is no need for that. The receiving section cyclically connects REN and RRN, but O12 and OTC are not cyclically connected.

In this way, sequential νζ parallel digital data is output from the first module with a delay of 0.3 to 0.5μ. Since there is a slight delay, it is also possible to output all the parallel data at the same time.

The transmitter outputs data in order from the first module,
In the receiving section, data is input in order from the first module. Therefore, the input value Dik of the second bit of the first module of the transmitting section is exactly equal to the output value Dok of the second bit of the jth module of the receiving section.

(3 Effects (1) In addition to 1:1 communication, 1:n address communication is possible.

(2) By expanding 1:1 communication, it is possible to transmit and receive digital signals with a number of bits that is an integral multiple of one module.

(3) It is possible to easily select the usage method according to the purpose of equipment, devices, and facilities in which a large number of control signal lines are wired and connected.

(4) Wiring for FA, OA, single panel control, etc. can be made smaller in diameter, lighter in weight, and easier to work with.

(5) Optical fibers can be used as transmission lines, so
It can become a transmission device that is resistant to electromagnetic noise.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an optical transceiver module used in the optical multiplex transmission apparatus of the present invention. Figure 2 shows DMI encoded serial data bits,
FIG. 3 is a waveform diagram showing a data frame consisting of a parity bit and a stop bit. FIG. 3 is a module terminal configuration diagram when optical transceiver modules are connected 1=1. FIG. 4 is a module terminal connection configuration diagram in address communication mode in which optical transceiver modules are connected in a 1:n manner. FIG. 5 is a module terminal connection configuration diagram of an extended communication mode in which 16 m-bit digital data is transmitted and received using an X station and a Y station to which m optical transmitting/receiving modules are connected. FIG. 6 is a waveform diagram of the transmitter when performing automatic repeat communication in 1:1 communication or address communication mode. FIG. 7 is a waveform diagram of the receiving section when performing automatic repeat communication in 1:1 communication or address communication mode. Figure 8 shows S in 1:1 communication or address communication mode.
FIG. 4 is a waveform diagram of a transmitter when performing RN external transmission synchronous communication. FIG. 9 shows 1:1 communication or address communication mode lc,
FIG. 4 is a waveform diagram of a receiving unit when performing SRN external transmission synchronous communication. FIG. 10 is a waveform diagram of the transmitter and receiver of the leading module in extended communication mode. FIG. 11 is a waveform diagram of the transmitter and receiver of the intermediate module in the extended communication mode. FIG. 12 is a waveform diagram of the transmitter and receiver of the last module in extended communication mode. 1......Optical transceiver module 2...
・・・・・・・・・Input clamp 3・・・・・・・・・
...P/S conversion circuit 4...
・Transmission timing control circuit 5...
...System control circuit 6...
...Oscillation circuit 7...E
10 Conversion circuit 8... LED 9... Optical connector section 10...
......PD ll......O/E conversion circuit 12...
......S/P conversion circuit 13...
・・・・・・Output buffer 14・・・・・・・・・・・・
・Reception timing control circuit 15...
...Error detection circuit 16...
・Address detection circuit 17・・・・・・・・・Power filter 18・・・・・・・・・CDI lamp inventor Toshihiro Toda

Claims (2)

[Claims] (1) A light-receiving element that converts parallel digital data into serial data and receives a DMI-encoded optical signal and converts it into a current, and a DM that amplifies and binarizes the current of the light-receiving element.
O demodulates the I code and converts it into a serial data voltage signal
/E conversion circuit 11 and S/P conversion circuit 1 that temporarily holds a serial data signal and converts it into parallel data.
2, an output buffer 13 that holds S/P-converted parallel data, parallel digital data output terminals Do0 to Do15 that output the parallel data held in the output buffer 13 to the outside, and an S/P conversion circuit 12. A reception timing control circuit 14 that controls the timing of inputting serial data and the timing of transmitting S/P-converted parallel data to the output buffer 13, and a system control circuit 5 having MS0 and MS1 inputs and specifying the reception state. and an @OSP@ output terminal for transmitting the timing at which parallel data is output to the output buffer 13 to the outside, and the reception timing control circuit 14 has an @RDE@ terminal for outputting the received serial data to the outside as is. and the @RRN@ input terminal to inform the outside that the module is ready to receive data, thereby giving the timing for inputting serial data to the S/P conversion circuit 12, and the connected module to receive the data. The leading optical receiver consists of an @REN@ output terminal for notifying that it is in a possible state, and an @OTC@ input terminal for receiving timing for outputting S/P-converted parallel data to the output buffer 13. Module, @RD@ input which inputs serial data from outside without a light receiving element and O/E conversion circuit, and @RD
@ An S/P conversion circuit 12 that temporarily holds the serial data signal input from the input and converts it into parallel data, an output buffer 13 that holds the S/P converted parallel data, and the output buffer 13 holds the serial data signal. A parallel digital data output terminal Do that outputs parallel data to the outside.
0 to Do15, a reception timing control circuit 14 that controls the timing of inputting serial data to the S/P conversion circuit 12 and the timing of transmitting S/P converted parallel data to the output buffer, MS0,
A system control circuit 5 has an MS1 input and is used to specify the reception state, and a parallel data output buffer 1.
@O to notify the outside of the timing output to 3
The reception timing control circuit 14 has an @RDE@ terminal that outputs the received serial data to the outside as it is, and an output terminal that informs the outside that the module is ready for reception. @RRN@ input terminal for giving the timing for inputting serial data to the S/P conversion circuit 12 by S It consists of an intermediate receiving module consisting of an @OTC@ input that provides timing for outputting /P-converted parallel data to the output buffer 13, and a last receiving module having the same configuration as the intermediate receiving module. , one leading optical receiving module, 0 or more intermediate receiving modules, and one last module are combined in order, and the @RDE@ output, @REN@ output, and @OSP@ output of the previous stage receiving module is sent to the next stage. Connect all the modules in order by connecting to the @RD@ input, @RRN@ input, and @OTC@ input of the receiving module, and @REN of the last module.
By connecting the @output to the @RRN@input of the first optical receiver module and changing the combinations of H and L levels of the system setting terminals MS0 and MS1, it is possible to Set something and the data to be transmitted is D equal to the number of receiving modules
It consists of MI encoded data frames DFI, DF2,..., a start frame AF that is attached to the beginning of the data frame and can be distinguished from a data frame, and a stop frame TF that is attached to the end of the data frame and can be distinguished from a data frame. , when the first optical receiver module receives the optical signal and converts it into a serial voltage signal, @R
Exactly the same serial data is simultaneously transmitted to all receiving modules through the DE@ output and @RD@ input, and the first optical receiving module detects the start frame AF, receives the first data frame DF1 following it, and receives the first data frame DF1. It is held in the S/P conversion circuit and changes the @REN@ output to inform the following intermediate module that the next data frame can be received, and the first intermediate module receives the second data frame. Receive DF2 and its S/
The same operation is repeated for all intermediate modules.The last module also receives the last data frame and holds it in the S/P conversion circuit.Then, the first optical receiving module detects a stop frame. When I did,
The parallel data held in the S/P conversion circuit is output to ■ data outputs Do0 to Do15, and at the same time @OSP@
By changing the output, the @OTC@ input of the next intermediate module is changed, and this intermediate module becomes S/P.
By outputting the parallel data held in the conversion circuit to the parallel data outputs Do0 to Do15 and repeating the same operation up to the last module, all the parallel data contained in all data frames DF1, DF2, ... A multiplex transmission receiving device characterized by outputting data almost simultaneously. (2) The multiplex transmission receiving apparatus according to claim (1), further comprising an @OCL@ input terminal for clearing data latched in the output buffer 13.