JPS6356036A - Method and apparatus for frame synchronization - Google Patents

Abstract

PURPOSE:To facilitate the detection of a frame pattern by extracting a head 1 bit of each subframe, expanding the extracted N-bit into K-series (K is a factor of N), and inserting while dispersing the frame synchronizing bit comprising (N/K)-bit to each series, respectively. CONSTITUTION:One bit is selected from each subframe being 1/N division of one frame and of M-bit constitution, the selected N-bit is expanded into K-set of series (K is a factor of N), and a frame synchronizing pattern comprising N/K-bit is inserted to one series sequentially. Then a cyclic code comprising 1-word N/K-bit of (K-1)-set of series generated from a generation polynomial is inserted sequentially to one of the remaining (K-1)-set series. For example, let N be 14 and K be 2, then a frame pattern in inserted sequentially to a head bit of the subframe of each odd order number while being dispersed by one bit each, and the cyclic code is inserted to the head bit of the subframe of each even order number while being dispersed by one bit each.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization system used in digital transmission systems such as backbone transmission systems, public networks, subscriber government systems, etc.

[Takumi rice technology]

Transmission technology using original fibers as a transmission medium has made remarkable progress, and the amount of transmitted information is now several hundred Mb.
Transmission speeds ranging from ps to several Gbps are becoming possible.

Time-division multiplexing is a possible method for effectively using large-capacity digital transmission systems, but it requires high-speed processing. There used to be. One such method is a bit-based time division multiplexing method, and FIG. 6 shows a general frame configuration diagram of this multiplexing method. In the same figure, one 17-frame iK drop is made,
The frame is divided into channels in units of bits, and one channel is assigned to the frame channel.
is frame channel, #1~1? -fil: 'l, -1 channels in units of blocks. Regarding this technology, "1.2 Gbps original loop fiLANOJil ["], which was developed and published by Fumio Akashi et al., was published in the summer 1985 IEICE Information 7 System Section, National Conference Lecture Proceedings Volume 2,
P, 741C is described. In this method, when performing bit multiplexing, a unique frame pattern is inserted one bit at a time into a frame channel ψ1) in units of several frames, and in synchronization detection, data is separated in units of channels and then from any channel. The frame channel is detected and synchronization is detected based on whether the separated signal string matches the inserted unique frame pattern.

Another method is to divide the frame into subframes and distribute the frame pattern to each subframe, and Figure M7 is a general frame configuration diagram of that method. In the figure, an l frame is divided into L subframes, and each subframe is divided into 1 bit units.
The frame is composed of (IXL) bits, and the frame pattern is inserted one bit at the beginning of each subframe (1 bit) in VC sequence. Fi(j=1.2
. . , L) indicates a frame bit inserted into the first bit of each subframe, and 11-$L indicates a subframe in units of 1 bit. Regarding this technology, see "Design and Characteristics of 400M Terminal Relay AA Ton" published in Research and Practical Application Report Vol. 32, No. 3, VC Hyakku Fanhaku et al., 1981, p. 597. -608. In this method, (PIF2F3...k゛L-2F
'L) is the frame pattern, and in synchronization detection, from the separated signal sequence (F'1F2F3...
. . PL-1k'L) is used for synchronization detection. It is not necessary to insert the frame pattern into all of the frame bits Fl-F'L. For example, if the frame pattern is inserted into the 7 frame bits PIF3F5... *F4F6・・・・・・
It is also possible to transmit information such as a transmission path monitor or a service monitor using .

[Problem that the invention seeks to solve]

In the bit multiplexing system as shown in FIG. 6, one bit out of the bits is used in one frame as a frame channel. In order to reduce the size and simplify the circuit, VC cannot increase the length δ of K constituting one frame by more than 1, so the signal amount of the frame pattern in the transmission data is 1/K. It's getting bigger.

This overhead is expected to increase as the transmission capacity i' increases and the speed increases.Furthermore, when considering system reliability and serviceability, channels for transmitting information such as transmission path monitors and service monitors are also required. , this trend will increase significantly.

In addition, in the method shown in Fig. 7, in which the frame is divided into subframes and the frame pattern is distributed to each subframe, a fixed frame pattern is used (FIP2F3...FL -IFL) is detected from the separated signal sequences to perform synchronization detection and ensure frame synchronization and subframe synchronization. frame pick) pl～1
Subframe I in the pl frame that is transmitted by inserting information such as transmission path monitoring monitor and Chivis monitor into L! By increasing L and the number of subframe bits (11fr), information transmission with less overhead for transmission data i can be achieved without increasing the complexity of the circuit.

If synchronization is lost while powering, the frame pattern will be used (PIF2F3...Ft, -t
In order to detect a signal string that matches the LXIXI frame (Fx, ) from the separated signal strings, hunting between l frames is required in the worst case. ), and if the number of subframes and subframe configuration bits il become large, the average time it takes to detect the 7-frame pattern CFI P2 F3...PL-IFL) after - degree synchronization is lost. was getting bigger. The present invention solves these problems by reducing the overhead of the amount of frame pattern signals relative to the amount of transmitted data without increasing the circuit size or complexity, making it easy to detect frame patterns, and reducing the average time required to recover synchronization. By reducing this, it is possible to provide a synchronization detection circuit suitable for high-speed, large-capacity transmission systems (RC).

[Means to solve the problem]

According to the present invention, one bit of each subframe is selected from a frame divided into N subframes, each subframe having an M bit configuration, and the selected N bits are converted into a sequence (K is (factors of ), and in that one series N/K
A frame synchronization pattern consisting of bits is sequentially inserted,
Frame synchronization characterized in that one of the remaining K-1 sequences is sequentially inserted with a cyclic code of K-1 sequences consisting of l word N/K bits generated from a generator polynomial. method is obtained.

According to the present invention, one bit of each subframe of a frame is divided into N subframes and each subframe has an M bit configuration, and the selected N bits are converted into a series (K is N ), and sequentially insert into one series a frame synchronization pattern forming a cyclic code consisting of l word N/K bits generated from the generator polynomial,
The remaining K -1 sequences are a pit sequence in which N/K bits' generated by the frame synchronization pattern are rotated out of a cyclic code consisting of one word N/K generated from the generator polynomial. A frame synchronization method is obtained in which a cyclic code that exists exclusively with the NZK glaze code polynomial used as a coefficient is sequentially inserted.

According to the present invention, a first parallel-to-serial converter converts M pieces of parallel transmission information into one-column information, and a second parallel-serial converter converts K pieces (K is a factor of N) of parallel transmission information into serial information. a frame pattern generator that generates a frame synchronization pattern, and a cyclic code generator that generates a cyclic code of l words and N bits generated from a predetermined generator polynomial; The outputs of the pattern generator and the cyclic code generator are respectively connected to the second parallel-to-serial converter, and furthermore, the output of the second parallel-to-serial converter is connected to the M pieces of the 10th parallel-to-serial converter. A frame synchronization device is obtained, which is characterized in that the input terminal is connected in a tilted position.

The present invention [j] is connected to a first serial-to-parallel converter that extracts a received signal every M bits, and to at least one series of outputs of the first serial-to-parallel converter, and converts this one series into A second serial-parallel converter that expands into a series, and N extracted from at least l series among the outputs of the second @parallel converter.
means for calculating a remainder between a code polynomial whose coefficient is /K bits (N is a multiple of K) and a predetermined friend generation polynomial;
A frame characterized in that it includes means for performing synchronization detection using the result of the remainder and N/K bit strings of N/K bit sequences extracted from this data string, which are connected to the output of the second serial-to-parallel converter. A synchronizing device can be obtained. [Function] Reducing the circuit scale for synchronization detection.

It is desirable to simplify the frame structure on the transmission path by dividing it into tepframe units, extracting the first bit of each subframe, and then dividing the extracted N bits into a series (
K is a factor of N), and the l series is (N/K)
Frame synchronization billatra consisting of bits are inserted in a distributed manner, and in synchronization detection, detection of the L frame pattern, that is, synchronization detection, can be performed by extracting the inserted frame bits. The operating speed required for the detection circuit has been reduced, making the circuit smaller and simpler, and making it possible to configure a synchronization detection circuit suitable for high-speed, large-capacity transmission systems. By increasing the number of subframes and the number of bits constituting a subframe, it is expected to realize a transmission system that reduces the overhead of the signal amount of the frame pattern for the transmission data. In addition, in synchronization detection, the remainder of the code polynomial and generator polynomial whose coefficients are l word (N/K) bits extracted from one sequence of separated signals is calculated using the properties of cyclic codes. In other words, by detecting the cyclic code pattern inserted in the frame and then searching for the frame pattern, frame synchronization can be quickly and easily ensured. Further, transmission path monitoring information or the like is used as the input pit string for generating the cyclic code, and information such as the transmission path monitoring information is also used to calculate the quotient with the generator polynomial on the receiving side. Transmission using c
[Embodiment] Before describing embodiments of the present invention, a cyclic code will be briefly explained here. Generally code word k (AO
AIA2 ・”An-t), A.

'1n-1st order, A 1 f n -2nd order, ..., An
Corresponding to -lf
+AIX"-2+AOX=1"""'...(ll) Here, the code length is n, and in terms of time, the higher-order term Ao appears first, and the higher-order term Ao appears sequentially to the lower order. Assume that 8n-1 appears at the end.

Here, the code length is 7, and the code word is (c, c2c3...
C7), the code polynomial F(3) can be expressed as a 6th order polynomial, F(Xl=C7+c6X+C5X2-)-C4X3+C
3X4-)-C2X5+ClX6 ・・・・・・・・・
(2) For example, if a third-order polynomial is selected as the generator polynomial G and G = l + X + X (3), then k゛ = Q = Q)・・・・・・・・・(If there is a polynomial Q(XJ that satisfies 41), the polynomial in equation (2) can be determined from the generator polynomial in equation (3).Here, As polynomial Q(X), input bit string 1 = (
If we choose the polynomial 9%(5) whose coefficients are 1110) and assume a field modulo 2, we get k゛(3)=Q
Prisoner G = (X+X2+X3)・(1+X+X3)=X+X 5
+X 5 ・・・・・・・・・(6), code word Wo=(1100010) ・−・・・・・・・−・+7
1 is generated from the input bit string I=(1110). In this case, the input pit string is (000
2-1=15 bit strings excluding the bit string of 0) are merged, and a code word corresponding to each input pit string is generated.

Furthermore, as shown in Publication 1 "Code Logic" (Hiroshi Miyayo, Yoshihiro Iwadare, Hidemachi Imai, Shokodo, p. 194-197), in the field of 2ft method - generally When the total code length is n, when the generator polynomial G divides X n +1, G
The code word generated from (3) forms a cyclic code. Therefore, the generating polynomial of equation (3) is (X+1)/G(i)=(
X+z)/(X+X+1)=X'+X2+X+
1・・・・・・・・・(8), X7+l becomes X'+X2
Since it is divisible by +X+1, the code word of code length 7 generated from the generator polynomial in equation (3) becomes a cyclic code. That is, the formula (
In the code word of 7), each new component of the matrix W water-frozen by equation (9) becomes a cyclic code with a code length of 7, Wl = (1100010) ...
(10-1)W2=(1000101)...
・・・・・・(10-2)W3=(0001011)
・・・・・・・・・(10-3)W4=(001
0110) ・・・・・・・・・(10-4)W
5= (0101100)...River...(1
0-5) W6=(1011000) ・・・River・
・・(10-6)W7=(0110001)・
・・・・・・・・・When (10-7), Wl, W2
．． ..., the code polynomial having W7 as a coefficient is divisible by the generator polynomial of equation (3).

The first invention will be explained with reference to the drawings. FIG. 1 shows a frame structure in an embodiment of the first invention. In the figure, 17 frames are divided into 14 subframes, each subframe is composed of M bits, and l frame is (
The frame pattern is 14
Bits are distributed and inserted, and the cyclic code is distributed bit by bit and inserted into the first bit of each even-numbered subframe. In the figure, Fi (j=1.2°...
, 7) is the frame bit e ”1 (J ~1 +
2 +..., 7) is a cyclic code with code length 7, #1 to #1
4 indicates a subframe number in M bit units. As mentioned above, EI3117) Generator polynomial〇(x)=l+x+
Using xft, a cyclic code with a code length of 7 is generated from VC.

It is possible that U 1 (1” l * 2 m・
..., 7), a cyclic code with a code length of 7 generated from the generator polynomial of equation (31) is sequentially distributed and inserted bit by bit. Also, as a frame synchronization pattern, (
F'1F2F3F4F5F6F"7) = (l11100
0)・・・・・・・・・q■ is inserted.

In this case, as the input bit string to generate the cyclic code, excluding the bit string of (oooo), the following 2'-1=1
It is FfJ' capability to use the five types of bit strings as transmission information as well.

The second invention will be explained with reference to the drawings. FIG. 1 shows a frame configuration for implementing the second invention. In the figure, 1
There are 14 subframes in 7 frames, each subframe is composed of M bits, one frame (14XM) bits, and a cyclic code is placed in the first pit of each odd-numbered subframe. The frame pattern forming the cyclic code is distributed and inserted one bit at a time, and the cyclic code, which exists exclusively from the frame pattern forming the cyclic code, is dispersed and inserted one bit at a time in the first bit of each even-numbered subframe. It has been done. In the figure, s Fi (i=1,
2. ..., 7) is a cyclic code with a code length of 7, gold frame bits + Cj (1 to 1 + 2, ..., 7) is a cyclic code with a code length of 7, and #1-414 is a cyclic code in M bit units. Subframe number t Indication T.Ft ('=1 + 2 +
..., 7) and CH (i=x, 2...., 7)
The generator polynomial that generates the cyclic code inserted into
) shown by G (xl=l+x+x3), the frame synchronization pattern is (PIF2F3F4F5F6F7)=(011101
0)...... Use aυ. Expressing the equation υ as a sign polynomial)'(xj=
x+x3+x'+x5--"・Next to Q3'(x)/(j(xl=(x5+x4+x3+x)/
(x”+x+1)=X2+X...Group...Since it is divisible by al' (x) is the formula (3)
The cyclic code generated from the generator polynomial G4x)=1+x+x3.

~V'1=(0111010) -old-1-(1
4-1) ~ 2 = (1110100) −・・−
River - (14-2) W3 = (1101001)
・・・・・・・・・(14-3)w/4= (1010
011) ・・・・・・・・・(14-4)W'
s= (0100111) ・・・・・・・・・
(14-5)W'6=(1001110)...
-----・-(14-6)W'7=(0011101)
・・・・・・・・・(14-7) W 1 m
The code polynomial whose coefficients are W2 m...+W7 is expressed by the formula (
3) is divisible by the generating polynomial. On the other hand, the formula (7
The code word WO=(1100010) shown in
The code polynomial shown in 7) and having a nine-cycle (b) code as a coefficient is expressed by the following equations (14-1), (14-2n, ..., (14
-7) Exists exclusively with the code polynomial whose coefficients are cyclic codes, so Ci (1==l e 2
The cyclic code inserted into #..., 7) is expressed by the formula (1
0-1).

(10-2), . . . , (10-7), the nine-cycle code can be inserted. At this time, equation (10-1).

The input bit string for generating the cyclic code of (10-2), ..., (10-7) is 11=(1110)...
(15-1)I2=(1011)...
...(15-2)I3=(0001)
・・・・・・・・・(15-3)I4=(0010)
・・・・・・・・・(15-4)I5=(
0100) ・・・・・・・・・(15-6
) I, = (1000) ・・・・・・・・・
・(15-6)I7=(0111) ・・
(15-7), it is possible to use this input bit string as transmission information.

Next, in Fig. 2, 1. An embodiment of the frame synchronization method according to the second invention will be shown. In the same figure, 2014 is a human control signal line, and 2021 is a flame turn generator (FPG).
, 202.2 is a cyclic code generator (CFG).

203 is a parallel-serial converter (MLIX), 204 is a parallel-to-series converter head (P-'3), 205 is a serial-parallel converter (9-P), 206 is a clock control circuit (CeL),
207 is a serial/parallel converter (1) M [JX].

208 is a divider (IJIV), 2091 to 209M are M pieces of input information i11%, 2101 to 210M are M pieces of output information, and 211 is an output limit signal name.

In the figure, a frame pattern generator 202 generates the frame synchronization pattern described above. Therefore, (1111000) of 200 or (0111010) of equation (11) is generated as a frame pattern for each frame. The cyclic code generator 2022 generates a cyclic code with a code length of 7 for every l frame using the generating polynomial ()lx)=1+x+x3 in equation (3). As a signal,
In the embodiment of the first invention, 2'-1=15 input bits of input bit length 4, excluding the bit string (oooo), are possible; in the embodiment of the second invention, the formula (
15-1), seven types of input bits shown in equation (15-7) are possible. It is possible to allocate transmission path monitoring information, etc. to these input bits. The parallel 11-plane column converter 203 time-division multiplexes two series signals of a frame synchronization pattern and a cyclic code, which are generated in synchronization from the frame pattern generator 2021 and the cyclic code generator 2022, and converts them into a serial signal. It is something. This output is input information line 209
1 is used as an input signal to the parallel-to-serial converter f204, and the input information is converted into the frame shown in FIG. For this output signal,
The input signal becomes the serial/parallel converter 2050, and this received signal is extracted every M bits and parallel converted, resulting in N1 pieces of output information &! It is output from 2101 to 210M. Output information gBxo which is a series of information lines subjected to parallel conversion
The information from 1 becomes an input signal to the serial/parallel converter 2070, and is further parallel-converted into two series of signals.

One of the output signals converted into two series becomes the input signal of the clock control circuit 206, and the other becomes the input signal of the divider 208.
becomes the input signal. This divider IjL unit 208 is a divider that divides the code polynomial whose code word is the 7 bits transmitted from the serial/parallel converter 207 every frame period by the quick polynomial of equation (3). The remainder is clock f
The quotient is sent to the f1lJ control circuit 206 and the quotient is output i! It is expressed in the IJ signal gland 211. This process extracts 1 bit from each of the 14 subframes, either even or odd, and generates a code polynomial and equation (3) to make a total code word of 7 bits. This corresponds to performing all divisions of the polynomial, and if the remainder is zero, the signal sent from the output information line 2101 to the divider is 4! r? If the remainder is non-zero, the signal sent from the output information line 2101 is assigned to a bit other than the first bit of each subframe. It means that information is available. In this way, it can be easily detected whether the information sent from the output information edge 2101 is a code forming a cyclic code inserted into the first bit of each subframe.

First, the case where there are 7 frames transmitted to the serial/parallel converter 205 in the embodiment of the ml invention will be described. If the remainder of the divider 208 is zero, this means that the bit string sent to the divider 208 is inserted into the first bit of an even-numbered subframe and consists of a code word forming a 9-cycle code. . At this time, the position of the leading bit of each subframe can be detected, and subframe synchronization is ensured. Here, even if the information sent from the output information 12101 is information inserted into the first bit of each subframe, the remainder of the divider 208 does not necessarily become zero.
At worst, the time required to secure subframe synchronization after falling into an out-of-sync state is only limited to hunting when the subframe length is M (2M-1). After subframe synchronization is secured in this way, the bit string sent from the single-column/parallel converter 207 will be the frame synchronization pattern assigned to the first bit of the odd-numbered subframe. Search T
lc EX, it is possible to quickly recover synchronization, and the worst case recovery time is (2M-1) x 1 frame (8EC
). Furthermore, the quotient of the divider 208 is the output control signal line 2.
It is output from 11. As this quotient, a bit string of 158N can be considered, and the reception of the control information transmitted using the second frame in the embodiment of the first invention becomes 51 times.

Next, a case will be described in which the frame transmitted to the serial/parallel converter (a) 205 is a frame according to the second embodiment of the invention. As with the previous friend, when the remainder of the divider 208 is zero, the bit string sent to the divider 208 is a cyclic code inserted into the even numbered or odd numbered first bit of the subframe. At this time, it becomes possible to detect the position of the first bit of each subframe, and subframe synchronization is ensured. In this case, since the frame synchronization pattern is also a cyclic code, the time required to secure subframe synchronization after falling into a -degree out-of-sync state is, at worst, when the subframe length is M (M-1 )
All you have to do is just do it.

After securing this subframe synchronization, the clock control circuit 206 determines whether the bit string being transmitted to the divider 208Il'c is a frame synchronization pattern forming a cyclic code or whether it exists exclusively with the frame synchronization pattern. F-synchronization recovery becomes possible by detecting errors using the cyclic code and promptly searching for a frame synchronization pattern. In addition, the synchronization O1 return time in the most arbitrary case is (M−
1) Becomes an XI frame (SEC). Furthermore, the divider 208
The song is from the output side Igo + j special 211 to Deba fL,
During this period, formula (15-1), ...... (15
A bit string of 7 bits shown in -7) is considered, and it becomes possible to receive the 1ItlJ information transmitted using the frame of the second invention.

Figure 3 shows the 1. 3A and 3B partially illustrate other embodiments of the second invention. To explain the difference in operation from the example in FIG. 2, the information lines expanded into F2 series in the 100 series O parallel converter 207 are input to two dividers 2081 and 2082, respectively. Therefore, it is possible to simultaneously divide the code polynomial whose code word is a 7-bit string extracted from even-numbered and odd-numbered subframes by 1byy) and the generator polynomial of equation (3). As a result, although the circuit scale increases somewhat, the time required to secure subframe synchronization after the frame in the embodiment of the first invention once falls into an out-of-synchronization state is, at worst, as long as the subframe length is N1. In the case of (M-1), the timing is good, and the synchronization recovery time in the worst case is (M-1).
This becomes a Xi frame (SEC).

Figures 4 and 5 are the circuit symbols g explained in Figures 2 and 3.
In the example of a combination of the generator 2022 and the divider 2υ8, 22
3□~2233, 233□~2333, 1t frame length delay element, 2241~22421234, ~2
342 is an adder of MOD2, and 235 is a control gate.

l subframe length delay elements 2231-223B.

The contents of 2331 to 2333 are cleared every l frames, and multiplication and division by the generator polynomial of equation (3) are performed every l frames. As a result, the V that generated the code length 70 cyclic code between 17 frames, and the transmitted 7 pins 9
This means that division with a code polynomial whose coefficients are t sequences can be performed. The remainder becomes the output of control gate 235.

Above, the number of subframes in l frame is 14. An example will be explained in which the generating polynomial is l+x+x3.The present invention is not limited to these combinations, and various combinations can be considered.

〔Effect of the invention〕

As described above, when using the synchronization detection method according to the present invention, the overhead of the signal amount of the 7-frame pattern relative to the amount of transmitted data, the ease of synchronization detection, and the average asynchronous duration time are reduced compared to the synchronization detection method using the conventional configuration. It can be seen that this has been significantly improved.

This invention is a synchronization detection method suitable for such high-speed, large-capacity transmission systems, and is expected to be applied to transmission systems that will become faster and larger in capacity in the future.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a frame in an embodiment of the present invention, the second factor is a block diagram of the embodiment of the present invention, FIG. 4 is a block diagram showing a cyclic code generator in FIG. 2, FIG. 5 is a block diagram showing the divider in FIG. 2, and FIGS. 6 and 7 are frame configuration diagrams in the conventional example. 201...Input 11J elevation signal, 202.・・・
... Frame pattern generator, 2022 ... Mark/cyclic code generator, 203 ... Parallel/serial converter,
2o4...Narayu1" 0rin row converter, 205...
...Serial/parallel converter, 2o6...Clock control circuit, 2o7...Series/parallel converter, 2
08...Divider, 209, ~209M...
...M input information lines, 2101 to 210M...
・M output information lines, 211...Output control signal lines, 223□~2233.2331~2333...
・Delay element of 1 subframe length, 2241 to 2242
, 2341-2342 River... MUD2 adder, 2
35... Control gate. Agent: Susumu Uchihara, Patent Attorney, 1st session: $1,000 7 times

Claims (4)

[Claims] (1) Select 1 bit from each subframe of a frame that is divided into N subframes, each subframe consisting of M bits, and divide the selected N bits into K sequences (K is a factor of N). The frame synchronization pattern consisting of N/K bits is sequentially inserted into one series, and the remaining K-1
1. A frame synchronization method characterized in that a cyclic code of K-1 sequences each consisting of one word and N/K bits generated from a generator polynomial is sequentially inserted into one of the sequences. (2) Select 1 bit from each subframe of a frame that is divided into N subframes, each subframe consisting of M bits, and divide the selected N bits into K sequences (K is a factor of N). A frame synchronization pattern forming a cyclic code consisting of 1 word N/K bits generated from the generator polynomial is sequentially inserted into one series, and the remaining K-1 series are 1 word generated N
/K cyclic codes, N/K types of code polynomials whose coefficients are bit strings obtained by cycling N/K bits, which are the frame synchronization patterns, and exclusive K cyclic codes are sequentially inserted. A frame synchronization method characterized by: (3) A first parallel-serial converter that converts M parallel transmission information into serial information, and a second parallel-serial converter that converts K parallel transmission information (K is a factor of N) into serial information. , a frame pattern generator that generates a frame synchronization pattern, and one word N generated from a predetermined generator polynomial.
comprising a cyclic code generator for generating a cyclic code of bits;
The outputs of the frame pattern generator and the cyclic code generator are respectively connected to the second parallel to serial converter, and further, the output of the second parallel to serial converter is connected to the M of the first parallel to serial converter. A frame synchronization device characterized in that it is connected to any of the input terminals of a book. (4) Connected to a first serial-to-parallel converter that extracts the received signal every M bits and at least one series of the outputs of the first serial-to-parallel converter, and expands this one series into K series. a second serial-to-parallel converter; and N/K bits (
means for calculating a remainder between a code polynomial whose coefficient is (N is a multiple of K) and a predetermined generator polynomial; A frame synchronization device comprising means for detecting synchronization using N/K bit strings of K extracted sequences.