JPS6355780B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
MOSLSI (Metal Oxide Semiconductor Large)
This paper relates to improvements in isolation technology between elements of Scale Integrated Circuits.

Conventionally, a so-called selective oxidation method has been generally used as an element isolation method for MOSLSI, but as the degree of integration increases, various drawbacks have arisen.

This drawback will be explained below with reference to FIG. In the figure, an oxide film 2 is grown on a silicon substrate (for example, P type, crystal orientation: (100)) 1, a nitride film 3 is deposited, and an impurity is added to the field portion by patterning to form an inversion prevention region 4. This shows the state immediately after field oxidation is performed to form a field oxide film 5.

The disadvantages of the selective oxidation method in terms of high integration are:
First of all, there is a so-called bird's beak effect in which the field oxide film 5 digs into and grows under the nitride film 3 during field oxidation. That is, as shown in Figure 1, if the length of the bird's beak is B (for example, 1 μm), even if the minimum spacing of the nitride film 3 (determined by the technical limit of photolithography) is A (for example, 1 μm), the field is The minimum width C is C=2A+B (for example, 3μ
m), and it is impossible to make the field width smaller than this. Recently, attempts have been made to suppress bird's beak by thickening the nitride film and thinning the oxide film 2 under the nitride film, or by thinning the field oxide film 5. However, the former has the problem of increasing stress at the edge of the field, making it more likely to cause defects, and the latter has problems such as a drop in field inversion voltage, making it increasingly difficult to integrate devices using selective oxidation. It's summery. The second problem is that the boron ion-implanted for the channel stopper diffuses laterally during field oxidation, and the element formation region (portion D in Figure 1) becomes a P ⁺ region, which causes the effective The element area may become narrower. As a result,
Narrow channel effects such as a decrease in transistor current and an increase in threshold voltage occur. These problems are gradually becoming a problem with the miniaturization of elements. Furthermore, as the P ⁺ region expands in the lateral direction, the stray capacitance between the n ⁺ layer in the element region and the substrate can no longer be ignored as the element becomes smaller.

In order to eliminate such conventional drawbacks, the applicant of the present invention proposed on the same date a method of manufacturing a semiconductor device using a novel field region forming means as shown in FIGS. 2a to 2f. This method will be explained below.

(i) First, silicon substrate (P type, crystal orientation:
(100)) Masking material film 12 such as oxide film on top
(as shown in Figure 2a).

(ii) Next, the masking material film 12 is patterned by photolithography or the like to form a masking material 12' (as shown in FIG. 2b).

(iii) Next, the substrate 11 is etched using, for example, KOH using the mask material 12' to form a groove 13 having side surfaces having an inclined angle θ. The width of the opening of this groove is a (for example, 1 μm) (second
Figure c).

(iv) Next, using the mask material 12', boron, which is an impurity of the same conductivity type as the substrate 11, is ion-implanted under conditions such as an acceleration voltage of 50 KeV and a dose of 5×10 ¹² /cm ² , and then heat treatment is performed. P ⁺ area 1 is applied as a channel stopper area at the bottom of the groove 13.
4 (as shown in Figure 2d).

(v) Next, after removing the mask material 12', the SiO ₂ film 15 is deposited by CVD (Chemical Vapor Deposition).
When the width of the opening of the groove portion 13 is a, the thickness is deposited by the method to a thickness of (a cot (θ/2))/2 or more. (Illustrated in Figure 2e). At this time, CVD−SiO ₂
The film 15 is gradually deposited on the substrate 11 and the inner wall surface of the trench 13, and is sufficiently filled up to the opening of the trench 13. Note that during this deposition, re-diffusion of the P ⁺ region 14 hardly occurs because the high-temperature, long-time thermal oxidation treatment such as in the selective oxidation method is eliminated.

(vi) Next, the entire surface of the CVD-SiO ₂ film 15 is etched with ammonium fluoride until the portion of the silicon substrate 11 other than the groove portion 13 is exposed. At this time, substrate 1
The thickness of the CVD-SiO ₂ film 15 on top of the groove 13 is removed, and the CVD-SiO ₂ remains only in the groove 13.
As a result, a field region 16 buried within the substrate 11 is formed (as shown in FIG. 2f).

(vii) After that, the field area 1 is
A gate electrode 18 made of polycrystalline silicon is formed in the island-shaped element formation region separated by 6, with a gate oxide film 17 interposed therebetween, and arsenic is diffused to form source and drain n ⁺ regions 19. An insulating film 20 is deposited, and a contact hole 2 is formed.
The main steps of the LSI are completed by opening 1 and providing Al wiring 22 (as shown in Fig. 2g).

By performing the steps described above, the drawbacks of the selective oxidation method can be eliminated.

(1) The minimum width S of the field is the minimum width a of the groove 13
Since the so-called bird's beak unlike in the selective oxidation method does not occur, as long as the width of the groove 13 can be made small, any number of integrations are possible.

(2) When the field width is shortened, in the conventional selective oxidation method, the channel length of the parasitic MOS transistor is shortened, and the short channel effect tends to lower the inversion voltage of the field, making it easier for leakage current to flow between the fields. However,
If this method is used, the channel length of the parasitic MOS transistor becomes longer because the component in the depth direction of the trench 13 greatly contributes, and the short channel effect of the field can be easily prevented.

(3) To prevent field inversion, the p ⁺ region 14 is located below the trench 13, and since there is no thermal process for field oxidation, it is difficult to diffuse into the device formation region, which may cause deterioration of device characteristics due to the aforementioned narrow channel effect, etc. n ⁺ by joining the ⁺ layer and the p ⁺ region
There is no increase in stray capacitance between the layer and the substrate.

(4) Since there is no field oxidation as in the selective oxidation method, there are no defects in the silicon substrate 11 caused by stress caused when the field oxide film digs under the nitride film.

(5) In the selective oxidation method, a step is created between the field region and the element region, but with this method, it is possible to make the field region completely flat, resulting in a structure that is extremely suitable for microlithography.

As mentioned above, this method has many advantages.
However, all in narrow field areas.
This is good when forming an LSI, but there are some difficulties when forming a wide field region. That is, the width S of the field region is determined by the width S of the groove 13, and in order to leave the insulating film in the groove 13, the thickness of the insulating film is T>a cot(θ/2)/2.
When the width of the field region is wide, an insulating film must also be deposited. For example, in order to form a field with a width of 20 μm, the thickness of the insulating film must be approximately 10 μm or more, and there are many difficult problems such as deposition time, film thickness accuracy, and crack-free conditions. Furthermore, it is very difficult to form a field with a width of 200 μm (for example, the bottom of an Al bonding pad) using this method. Therefore, if a wide field is required, as shown in FIG. 3, first bury a narrow field region 16 according to the method described above, and then deposit an insulating film 23 of SiO ₂ , for example. , this insulating film 23 is left partially by photolithography,
A method was used to form a wide field region 24.

Although this method allows the formation of a wide field oxide film and overcomes most of the deficiencies of the selective oxidation method, one major drawback may occur in some cases. That is, a step is generated at the end of the wide field region 24 shown in FIG. 3, and flatness is lost. In the case of the selective oxidation method, half of the field film is buried in the silicon substrate, but in this method, the field film thickness becomes a step as it is, so a step difference occurs that is larger than that in the case of the selective oxidation method. For this reason,
This has been a major obstacle when microlithography is required near wide field membranes.

This invention was made in view of the above circumstances.
The purpose is to provide a method for manufacturing a semiconductor device that solves the problems of conventional element isolation techniques and enables higher integration and higher performance of LSIs.

An embodiment of the present invention will be described below with reference to the drawings.
A case where the present invention is applied to the manufacturing process of channel MOSLSI will be explained.

(i) First, silicon substrate (P type, crystal orientation:
(100)) A masking material film such as a SiO ₂ film is deposited on 31 and patterned using photolithography or the like to form a masking material 32 (as shown in FIG. 4a).

(ii) Next, using the mask material 32 as a mask, etching is performed to form a width with side surfaces having an inclination angle θ.
The narrow first groove portion 33 shown in (a) is formed. This etching method may be KOH etching or reactive ion etching (as shown in FIG. 4b).

(iii) Next, using the mask material 32 as a mask, for example, boron is accelerated at a voltage of 50 KeV and at a dose of 5×10 ¹² /cm ²
Ions are implanted under the following conditions to form a p ⁺ region (channel stopper region 34) at the bottom of the first trench 33 (as shown in FIG. 4c).

(iv) Next, after removing the mask material 32, if the width of the first groove 33 is a (a cot(θ/
2))/Insulating film with a thickness of 2 or more (e.g.
A CVDSIO ₂ film or a Si ₃ N ₄ film 35 is deposited to fill the first trench 33 (as shown in FIG. 4d).

(v) Next, the insulating film 35 is etched until the silicon substrate 31 is exposed. As a result, the buried field insulating film 36 ₁ ,
36 ₂ and 36 ₃ remain (as shown in Figure 4e).

(vi) Next, a thin insulating film (for example, a 500 Å thermal oxide film) 37 is formed on the silicon substrate 31, and an oxidation-resistant film (for example, a 3000 Å thick thermal oxide film) 37 is formed on this insulating film 37.
A Si ₃ N ₄ film 38 is deposited (as shown in FIG. 4 f).

(vii) Next, the resist film 39 is patterned using photolithography so that all or part of the boundaries are on the buried field insulating films 36 ₁ , 36 ₂ , 36 ₃ . Then, using this resist film 39 as a mask, the oxidation-resistant film 38 is etched, the thin insulating film 37 is etched, and the silicon substrate 31 is further etched to form a second trench 40. When etching this silicon substrate 31, buried field insulating films 36 ₁ , 36
₂ , 36 ₃ is not etched at all or hardly etched (Fig. 4g)
(Illustrated). Note that before etching the thin insulating film 37 or the silicon substrate 31, the resist film 39 is peeled off and the subsequent etching is performed using the oxidation-resistant film 38.
You may wear a mask. Further, although the etching depth of the silicon substrate 31 varies depending on the subsequent oxidation conditions, it is set to, for example, 5000 Å here.

(vii) Next, the resist film 39 [in (vii), the resist film 39
If the oxidation-resistant film 38 is peeled off, ions of boron, for example, are implanted at an acceleration voltage of 50 KeV and a dose of 1×10 ¹³ /cm ² using the oxidation-resistant film 38 as a mask to form the second groove portion 40.
A p ⁺ region 41 is formed at the bottom of the substrate (as shown in FIG. 4h).

(ix) Next, after peeling off the resist film 39, field oxidation is performed using the oxidation-resistant film 38 as a mask to form a field oxide film 42 with a film thickness of, for example, 1 μm between the buried field insulating films 36 ₁ and 36 ₃ . Then, a wide field insulating film is formed. If the field oxide film 42 is formed to have a depth twice the etching depth of the silicon substrate 31, a wide field insulating film that is flat and flat with the element formation region can be formed (as shown in FIG. 4i). At this time, the buried field insulating film 36
If a Si ₃ N ₄ film or the like is used as the buried field insulating films 36 ₂ , 36 ₃ , horizontal encroachment (bird's beak) of the field oxide film 42 during field oxidation will not occur at all in principle, and the buried field insulating films 36 ₂ , 36 ₃ Even when a SiO ₂ film is used, hard beaks are hardly a problem.

(x) Next, the oxidation-resistant film 38 and the thin insulating film 37 thereunder are removed by etching (as shown in FIG. 4J).

() Finally, a gate oxide film 43 and a gate electrode (for example, polycrystalline silicon) 44 are provided, for example, arsenic is diffused to form n ⁺ regions 45 that will become sources and drains, and an interlayer insulating film (for example, CVD
Deposit SiO ₂ film) 46 and fill contact hole 4.
7 is opened and a wiring 48 made of, for example, Al is applied to complete the main process of the LSI (as shown in FIG. 4k).

By using the above steps, it is possible to overcome the various drawbacks when using the selective oxidation method described above, and it is also possible to form a field insulation region of any axis without steps. . Therefore, it can greatly contribute to higher integration and higher performance of LSI.

Next, other embodiments of the invention will be described.

(1) When forming the p ⁺ region 34 on the silicon substrate 31, SiO ₂ is used in the embodiment shown in FIGS.
The resist film 49 used for patterning the masking material film may be left as shown in FIG. 5, and the ion implantation may be performed using this as a mask. . In addition, as shown in FIG.
1 to form the first groove 33, a resist film 49 is placed directly on the substrate without using the mask material 32, and this is used as a mask for etching to form the groove, and then this resist is used as a mask to form the groove. Ion implantation may also be used.

(2) In the embodiment shown in FIGS. 4a to 4k, ions are implanted into the p ⁺ region (channel stopper region) 34,
41, but the silicon substrate 3
Depending on conditions such as the concentration of 1, this p ⁺ region 34,
41 is not necessarily necessary and ion implantation may not be performed. Further, only one of the p ⁺ regions 34 and 41 may be provided. The mask for ion implantation is not limited to the resist film 32, but may be an insulating film or the like. Furthermore, the p ⁺ region may be provided not only by ion implantation but also by a diffusion method.

(3) Before burying the insulating film 35 in the first trench 33, the insulating film 50 may be grown inside the trench 33 in advance (as shown in FIG. 7). This insulating film 50
may be formed by, for example, oxidizing the silicon substrate 31, or may be formed by depositing a CVD film or the like. Note that at this time, the width of the opening of the first groove 33 is somewhat narrower.

(4) Etching the insulating film 35 to form the first groove 33
Embedded field insulating film 36 ₁ , 36 only in
₂ , 36 ₃ , this field insulating film 3
6 ₁ , 36 ₂ , 36 ₃ may be structured such that they fall from the surface of the silicon substrate 31 (eighth
(Illustrated)

(5) Embedded field insulating film 36 ₁ , 36 ₂ , 36
₃ may have different depths.

(6) Deposit the insulating film 35 in the first trench 33, and
After completely filling the groove 33, a low-temperature melting insulating film (for example, boron silicide glass (BSG), phosphorus silicide glass (PSG), arsenic silicide glass (AsSG), etc.) is deposited on top of the groove 33, and this is melted. After that, the insulating film 35 may be etched to fill the first trench 33 with the insulating film.

(7) Instead of the insulating film 35, the above-mentioned low-temperature melting insulating film may be used. Alternatively, a two-layer structure including a meltable film and a non-meltable film may be used.

(8) In the embodiment shown in FIGS. 4a to 4k, a Si ₃ N ₄ film was used as the oxidation-resistant film 38, but any film that can suppress oxidation of the silicon substrate 31 may be used, for example, Al ₂ An O ₃ film or a thick SiO ₂ film may be used.

(9) In the embodiment shown in FIGS. 4a to 4k, the oxidation-resistant film 38 was deposited and then the oxidation-resistant film 38 and the silicon substrate 31 were etched using photolithography. A second trench 40 is provided by etching the oxidation-resistant film 38.
is deposited and the second groove portion 40 is formed using a photolithography method.
Field oxidation may be performed after etching the oxidation-resistant film 38.

(10) In the embodiment shown in FIGS. 4a to 4k, after the oxidation-resistant film 38 was etched, the silicon substrate 31 was etched to form the second groove 40, and then field oxidation was performed. As shown in FIGS. 9a and 9b, field oxidation may be performed without etching the silicon substrate 31 after etching the oxidation-resistant film 38. In this case, although the flatness of the field region and the element region is somewhat sacrificed, the effect of suppressing the diffusion of the channel stopper p ⁺ region 34 into the element region is large. At this time, the insulating film 37 does not necessarily have to be deposited. In addition, even if the insulating film 37 is left on the substrate like a SiO ₂ film, it can be removed from the underlying substrate (for example, a silicon substrate 3).
If 1) is oxidized during field oxidation, the method shown in FIG. 7a may be omitted and field oxidation may be performed without etching the thin insulating film 37.

(11) In the embodiment (10) above, the field oxide film 42 may be etched using the oxidation-resistant film 38 as a mask to form a flat structure (as shown in FIG. 10).

(12) The embodiment (11) above is not only one in which field oxidation is performed without etching the silicon substrate 31 as in the embodiment (10) above, but also one in which the silicon substrate 31 is etched and field oxidation is performed. It also applies to those who have done so. This is because the field oxide film 42 becomes thick even though the silicon substrate 31 is etched.
This is effective when the flatness is impaired by protruding above one surface.

(13) In the above embodiment, a V-shaped groove is used, but the present invention is not limited to this, and a first groove 33' having a flat bottom may be formed in the substrate 31 as shown in FIG. At this time, the thickness of the insulating film to be deposited is the same as described above (a cot・(θ/
2))/2 or more.

(14) Regarding the shape of the groove, the side surfaces do not necessarily have to be flat, and a first groove 33'' having side surfaces made of inclined curved surfaces as shown in FIG. 12 may be formed in the substrate 31. The thickness of the insulating film to be obtained is determined by (a cot(θ/
2) Set it to 2 or more.

(15) As shown in FIG. 13a, a film 15 with a high etching rate such as a phosphorous-doped glass film (PSG film) is deposited on the substrate 31, a mask material such as a resist pattern 52 is formed, and then this is masked. Alternatively, the coating 51 and the substrate 31 may be etched using, for example, a hydrofluoric acid-based etching solution, a plasma etching solution, or the like to form a first groove portion 33' having an inclined side surface (as shown in FIG. 13B).

(16) As shown in FIG. 14a, after depositing an insulating film 35 such as an oxide film on a substrate 31 and exposing it to a plasma atmosphere, a mask material such as a resist pattern 52 is formed, and this is used as a mask. The first groove portion 33' may be formed by etching the insulating film 35 and the substrate 31 (as shown in FIG. 14B).

(17) As shown in FIG. 15a, when forming a first groove 33 having an inclined side surface in a substrate 31 and then depositing an insulating film 35 and etching this, it is not necessary to etch until the substrate 31 is exposed. There is no need to do this, and as shown in FIG.
The remaining insulating film 35' may be etched so as to remain, and the remaining insulating film 35' may be used as a gate insulating film, an interlayer insulating film, etc., or as a part thereof.

(18) As shown in FIG. 16a, a first groove portion 33 having an inclined side surface is provided using a mask material 32 made of SiO ₂ or the like on a substrate 31, and this mask material 3
The field region 36 may be formed by depositing the insulating film 35 with the mask material 2 remaining and then etching the insulating film 35 so that the mask material 32 remains (as shown in FIG. 10B).

(19) As shown in FIG. 17, the field region 36 may be formed by leaving the insulating film 35'' in the first groove 33 having the inclined side surface of the substrate 31 so as to protrude in an arc shape from the surface of the substrate. good.

(20) The above embodiments explained the manufacturing process of n-channel MOSLSI, but
Of course, it can also be applied to the manufacturing process of MOSLSI.

As explained above, according to the present invention, it is possible to overcome various drawbacks when using the conventional selective oxidation method, and also to form a field insulating region having an arbitrary width without a step, Thus, it is possible to provide a method for manufacturing a semiconductor device that can achieve higher integration and higher performance of LSI.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view for explaining the problems with the conventional selective oxidation method, and Figures 2 a to g are n-channels according to the method submitted by the applicant on the same date.
3 is a cross-sectional view showing a state in which a field region is formed by the deformation means shown in FIGS. 2 a to f, and FIGS. Cross-sectional views showing the manufacturing process of channel MOSLSI, Fig. 5, Fig. 6, Fig. 7,
Fig. 8, Fig. 9 a, b, Fig. 10, Fig. 11, Fig. 12, Fig. 13 a, b, Fig. 14 a, b, Fig. 1
5a and 5b, 16a and 16b, and 17 are sectional views showing other embodiments of the present invention. 31...Silicon substrate, 32...Mask material, 3
3, 33', 33''...first groove, 34...p ⁺
Region (channel stopper region), 35... Insulating film, 36, 36 ₁ , 36 ₂ , 36 ₃ ... Buried field insulating film, 37... Thin insulating film, 38... Oxidation resistant film, 39... Resist Film, 40... Second trench, 41... P ⁺ region, 42... Field oxide film, 43... Gate oxide film, 44... Gate electrode, 45... N ⁺ region (source, drain), 46
...Interlayer insulating film, 47...Contact hole, 4
8...Al wiring.

Claims (1)

[Scope of Claims] 1. A step of providing a first groove portion having an inclined side surface in a desired portion of a semiconductor substrate and having an inclination angle θ in a range of 0<θ<90°; When the minimum width of the opening of the first groove is a (a cot(θ/
2) a step of depositing the insulating film to a thickness of 2 or more; a step of etching this insulating film to leave the insulating film in the first trench; and etching the remaining insulating film on the main surface of the semiconductor substrate. After depositing an oxidation-resistant film and selectively etching the oxidation-resistant film between the first trenches to form a second trench, field oxidation is performed using the oxidation-resistant film as a mask to form the first trench. 1. A method of manufacturing a semiconductor device, comprising the step of filling a gap between trenches with an oxide film and integrating it with an insulating film left in the first trench to form a wide field region. 2. After depositing an oxidation-resistant film on the main surface of the semiconductor substrate where the insulating film remains, etching is selectively performed between the oxidation-resistant film and the first groove of the semiconductor substrate, thereby forming the first groove. A semiconductor device according to claim 1, characterized in that a second groove portion having the remaining insulating film on at least a part of the side surface is provided, and then field oxidation is performed using the oxidation-resistant film as a mask. Production method. 3. After providing the first groove in the semiconductor substrate, oxidizing or nitriding the entire surface of the semiconductor substrate or at least a part of the groove to grow an oxide film or a nitride film to an extent that the first groove is not blocked. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that: 4. After providing the first groove in the semiconductor substrate or after providing the second groove in the same substrate, impurities having the same conductivity type as the semiconductor substrate are added to a portion of the semiconductor substrate below or on the side of each groove. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that selective doping is performed. 5 After depositing an insulating film on the semiconductor substrate provided with the first groove portion, depositing a low-temperature melting insulating film on the whole or part of this insulating film, melting this low-temperature melting insulating film, and then forming an insulating film. A method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that the method comprises etching. 6. After selectively etching the space between the first trenches of the semiconductor substrate where the insulating film remains, a second trench is provided having the insulating film left in the first trench on at least a part of the side surface; Claim 1, characterized in that an oxidation-resistant film is deposited on the entire surface of the semiconductor substrate, the oxidation-resistant film in the second trench is etched, and then field oxidation is performed using this oxidation-resistant film as a mask. A method of manufacturing the semiconductor device described above. 7. The semiconductor according to claim 1, 2, or 6, wherein after the field oxidation, a part of the field oxide film is etched using an oxidation-resistant film as a mask to obtain a flat structure. Method of manufacturing the device.