JPS6349929B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to variable delay equalizers;
More specifically, it relates to variable delay equalizers using transversal filter theory.

FIG. 1 is a conceptual diagram showing an example of TDMA communication which is the background of this invention. TDMA communication is used, for example, in satellite communication, and such a satellite communication system includes a plurality of earth stations ES, ES′, . . . and a common communication satellite CS. The earth station ES has a transmitter
Includes TRA and receiver REA. The signal modulated by the modulator MOD included in the transmitter TRA is sent to the antenna via the equalizer EQL and the transmitter TR.
It is sent from the AE to the communication satellite CS's antenna AS. The signal is frequency converted within the satellite and sent to another earth station ES'. Similarly, other earth stations
The signal from ES′ is sent to the earth station via the communication satellite CS.
The signal is received by the antenna AE of the ES, and the received signal is given to the receiving device REA. Receiving device REA is a receiver
It passes through RE and equalizer EQL and is demodulated by demodulator DEM. It is known that the transmitter TR and receiver RE of the earth station ES and the receiving system and transmitting system of the communication satellite each produce amplitude distortion and/or group delay distortion. In particular, the high-power amplifier (not shown) included in the communication satellite CS is used in a highly saturated state due to size, cost, stability, and other reasons. Therefore, AM-PM conversion occurs in this high-power amplifier, resulting in a phase change as shown by line A in FIG. In addition, the second
In the figure, line B indicates the output level. The above-mentioned phase change results in group delay distortion.

These amplitude distortions and group delay distortions are divided into the transmitting system and the receiving system, and the equalizer EQL included in the transmitting device TRA and the equalizer included in the receiving device REA are used.
EQL performs amplitude equalization or delay amount equalization. Conventionally, such an equalizer EQL is
Generally, a fixed amplitude equalizer, as shown in FIG.
FAE, fixed delay equalizer FDE and variable equalizer
It consists of ME. Depending on the amount of actual amplitude distortion or group delay distortion, the fixed amplitude equalizer FAE
Alternatively, one or both of the fixed delay equalizers FDE may be omitted.

In the TDMA communication system that forms the background of this invention, once operation begins, test signals are transmitted and received to measure the above-mentioned amplitude characteristics and group delay characteristics, thereby measuring the optimal equalization amount. is impossible. This is because such a communication system is carried out on a time-division basis, so the time that one earth station occupies the line is extremely short. Therefore, when a new earth station joins such a communications satellite system, it is necessary to select a new earth station that has the minimum amplitude distortion, group delay distortion, and therefore the minimum bit error rate (BER).
We need to find the optimal point. For this purpose, a variable equalizer ME as shown in FIG. 3 is used.

FIG. 4 is a circuit diagram showing an example of a conventional variable equalizer which is the background of the present invention. The input signal input to the input terminal 1 is branched by a branch circuit 2, and a part is given to a coefficient loading circuit 4 having a coefficient -a _o .
The remaining signals are input to the next branch circuit 2 through a delay line 3 having a delay amount T. Thereafter, in a similar operation, each signal is input to a coefficient loading circuit having a respective coefficient. Coefficient loading circuit 4,
The signals that have passed through 4, . Note that the coefficient loading circuits 4, 4, . . . include polarity reversal. In this way, the coefficients of the coefficient loading circuits 4 _{, 4 ,} . +a ₂ and -a ₂ , ......, +a _o and -a _o
Set it like this. In this way, by arbitrarily setting the respective coefficients of each coefficient loading circuit 4, 4, . . . , the amplitude characteristics and group delay characteristics are set according to the well-known transversal filter theory. That is, by the variable equalizer ME,
While measuring BER, change the amplitude characteristics and group delay characteristics to find the optimal point.

However, in TDMA communication systems, BER is more affected by group delay distortion than amplitude distortion, and therefore, if the optimal equalization amount for group delay distortion can be set, it is necessary to perform operations to search for such an optimal point. can be done easily. However, in the conventional variable equalizer, the coefficient loading circuit 4,
Since the coefficients 4, . . . are set arbitrarily, it is not possible to change only the amplitude or the group delay, for example. This means that in a TDMA communication system where the influence of group delay is greater than the amplitude, it is difficult to find the optimal point using a conventional variable equalizer. Furthermore, the coefficients of a conventional variable equalizer each determine the amplitude characteristics and group delay characteristics, but how such characteristics change when one coefficient is changed is
Since it also differs depending on other coefficients, it was impossible to know without a huge amount of simulation data. Therefore, it is not easy to confirm in what state the amplitude and group delay are each equalized.

As a variable equalizer ME, the one shown in FIG. 5 has already been proposed, for example, by the applicant of the present invention. In this FIG. 5, the input signal given from the input terminal 1 is passed through the distributor 7 to
distributed. The signal divider 7 divides each signal into three signals of the same level using, for example, a known hybrid circuit. A delay line 3 having a delay amount T is provided on the signal path of one of the three signals.
is inserted, a delay line 31 having a delay line 2T is inserted in another path, and a polarity inverter 8 is inserted in the remaining one path. The polarity inverter 8 is
It consists of a known transformer or transistor, and shifts the phase of the applied signal by 180 degrees. delay line 3
The signal from 1 and the signal from polarity inverter 8 are combined by adder 9, and then sent to variable coefficient loading circuit 1.
given to 0. The variable coefficient loading circuit 10 includes a polarity inverter, and the output signal therefrom is combined with the output signal from the delay line 3 in an adder 11.

Here, it is assumed that there is no signal attenuation except for the variable coefficient loading circuit 10, and that there is no time delay except for the delay lines 3 and 31, and the delay of the main signal is taken as the reference (0).
Then, the output signal B(ω) obtained at the output terminal 6 is
is expressed by the following equation (1).

B(ω)=cosωt−lcosω(t+T) +lcosω(t−T) =√(1+2 ² )−2 ² 2 ×cos{ωt−π/2 +tan ⁻¹ (1/2lsinωT)} ……(1) This The characteristic G _B (ω) of the amplitude of the output signal B (ω) with respect to the frequency and the characteristic τ _B (ω) of the amount of delay with respect to the frequency are given by the following equations (2) and (3), respectively.

G _B (ω) = 20log{√(1+2 ² )−2 ² 2} ……(2) τ _B (ω)=−2lT ×cosωt／(1+2l ² )−2l ² cos2ωt ……(3) However, ω is the angular frequency and ω=2πf (f is the frequency). This amplitude characteristic G _B (ω) is the delay characteristic τ _B
(ω), when the coefficient l>0, the change characteristic is the sixth
As shown in the figure. Figure 6A shows the amplitude characteristics;
Figure B shows the delay characteristics, which change in the direction of the arrow when the coefficient l is increased. That is,
As can be seen from FIG. 6, in the example of FIG. 5, if the coefficient l is changed in the coefficient loading circuit 10, the amount of delay also changes. However, even in the example shown in FIG. 5, not only the delay amount but also the amplitude changes as the coefficient l changes, making it extremely difficult to use it as a variable equalizer in a TDMA communication system. .

Therefore, the main object of the present invention is to provide a variable delay equalizer that can be effectively used in, for example, a TDMA communication system, in which the change in amplitude is very small even when the amount of delay is changed. It is.

To summarize, the present invention includes a delay section that combines a signal that is advanced by a certain amount of time and a signal that is delayed by a certain amount of time with different polarities when the absolute delay amount of the main signal circuit is used as a reference; an amplitude correction section that generates an amplitude correction signal by synthesizing a second predetermined time advanced signal and a delayed signal, and synthesizes the main signal, the output signal from the delay section, and the output signal from the amplitude correction section. A variable delay equalizer that controls the amplitude of the output signal from the amplitude correction section and the output signal from the delay section so that they always have a constant ratio, and eliminates the amplitude distortion generated in the delay section. This is a variable delay equalizer that corrects the signal from the correction section.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

Figure 7 shows TDMA as an embodiment of this invention.
1 is a block diagram showing an equalizer used in a communication system. FIG. In FIG. 7, a signal from an input terminal 101 is applied to an output terminal 102 through a variable amplitude equalizer VAE and a variable delay equalizer VDE included in an equalizer EQL. For example, if this equalizer EQL is used in a TDMA communication system as shown in FIG. , the input terminal 101 would be connected to the receiver and the output terminal 102 would be connected to the demodulator. variable amplitude equalizer
VAE can change only the amplitude characteristic without changing the amount of delay, and variable delay equalizer VDE can change only the group delay characteristic without changing the amplitude. Thus two equalizers VAE and
The cascade of VDEs allows optimal equalization of amplitude and group delay, each independently. By using such an equalizer EQL, it is possible to equalize the amplitude distortion and group delay distortion of the system independently, and it is easy to understand in what state each is being equalized. .

In the embodiment shown in FIG. 7, it is of course possible to use a fixed equalizer if necessary.

FIG. 8 is a circuit diagram showing an example of a variable amplitude equalizer. The embodiment of FIG. 8 is substantially the same as the variable equalizer shown in FIG. 5, except that the polarity inverter is omitted. That is, the input signal from the input terminal 101 is distributed by the distributor 7. The signal passing through the delay line 31 is combined with the signal not passing through the delay line by an adder 8, and is applied to an adder 11 through a variable coefficient loading circuit 10 having a coefficient k. In this manner, the main signal passing through the delay line 3 and the sub-signal passing through the variable coefficient loading circuit 10 are combined in the adder 11 and output to the output terminal 101'. There is no signal attenuation except for the coefficient loading circuit 10, and the delay line 3
Assuming that there is no time delay other than 31 and 31, and assuming that the delay of the main signal is 0,
The output signal A(ω) derived from 1' is given by the following equation (4).

A(ω)=cosωt+kcosω(t+T) +kcosω(t-T) =(1+2kcosωT)cosωt...(4) Frequency characteristic of the amplitude of this output signal A(ω) G _A
(ω) is therefore given by the following equation (5).

G _A (ω)=20log(1+2kcosωt) (5) However, the delay characteristic τ _A (ω) is flat.
The variation characteristic of this amplitude characteristic G _A (ω) with respect to the coefficient k is shown in FIG. If the coefficient k is increased, the amplitude changes in the direction of the arrow. That is, in the embodiment of FIG. 8, by changing the coefficient k of the variable coefficient loading circuit 10, a variable amplitude equalizer VAE in which only the amplitude changes without changing the amount of delay can be obtained.

FIG. 10 is a circuit diagram showing an example of a variable coefficient loading circuit. The variable coefficient loading circuit 10 includes a double balanced mixer DBM and a voltage generator VG for providing a control voltage thereto. The double balanced mixer DBM includes an input terminal LO, an output terminal RF, and a control terminal IF. The double balanced mixer DBM has a transformer connected to the input terminal LO and a transformer connected to the output terminal RF, and four diodes D1 to D4 are connected in a bridge configuration between the two transformers. Control voltage generator VG includes a variable resistor VR and a transistor Q1 that receives a voltage from variable resistor VR at its base. One end of the transistor Q1 and the variable resistor VR is connected to the power supply +V,
The emitter of transistor Q1 and the other end of variable resistor VR are connected to power supply -V. By changing the resistance value of the variable resistor VR, a control current Ic flows from the emitter of the transistor Q1 toward the control terminal IF. Double balanced mixer DBM
For example, the output signal from the adder 8 is applied to the input terminal LO of the adder 11, and the output terminal RF is connected to the input of the adder 11.

Next, with reference to FIG. 11, the operation of the variable coefficient loading circuit shown in FIG. 10 will be explained. By adjusting the variable resistor VR, the emitter voltage Ve of the transistor Q1 can be set from +Ve to -Ve. This voltage Ve causes a control current Ic to flow in the double balanced mixer DBM through the terminal IF, and the direction of this current Ic depends on the polarity of the voltage Ve. and,
When the voltage Ve is +, the diodes D1 and D3
conducts and diodes D2 and D4 are cut off. Conversely, when voltage Ve is negative, diodes D2 and D4 are conductive and diodes D1 and D3 are cut off. When the voltage Ve is 0V, all diodes D1 to D4 are cut off. Therefore, the polarity of the signal is inverted between the + range and the - range of the voltage Ve, and is output from the output terminal RF. Also, the diode D1
Since the resistance values of D4 to D4 change depending on the current Ic, the amplitude of the output voltage changes in accordance with the change in the voltage Ve, as shown in FIG. It will be appreciated that in this manner, the variable coefficient loading circuit shown in FIG. 10 changes the amplitude and reverses the polarity of the signal passing therethrough.

FIG. 12 is a circuit diagram showing an example of a variable delay equalizer as an embodiment of the present invention. This variable delay equalizer VDE has an input terminal 102' and an output terminal 1
02, and the input terminal 102' is connected to the output terminal 101' of FIG. 8, for example. The output terminal 102 is, for example, a transmitter TR or a demodulator.
Connected to DEM (Figure 1). Input terminal 102'
is connected to a distributor 7, and the input signal is therefore divided by this distributor 7 into the required number of signals (here 5
signal). Two of these five signals are given to the delay circuit 12 and the other two correction circuits 13. One of the remaining is the amount of delay
It is applied to the adder 21 through a delay line 301 having 2T. The two signals given to the delay circuit 12 are transmitted by delay lines 302 and 303 having delay amounts of 3T and T, respectively, so that the absolute delay amount of the main signal circuit, that is, the delay line 301 (here, 2T)
The signal is delayed so that the signal is advanced by T and the signal is delayed by T with respect to . delay line 302
The output signal from the delay line 303 is a signal delayed by a time T with respect to the main signal, and the output signal from the delay line 303 is a signal delayed by a time T. The output signal from the delay line 303 passes through a known polarity inverter 14 and is applied to the adder 15 together with the output signal from the delay line 302. Therefore, in the delay circuit 12,
A signal advanced by a predetermined time T and a delayed signal based on the absolute delay amount of the main signal are combined with the same level and different polarities, and the output signal is sent to an adder 19
given to. On the other hand, the correction circuit 1 from the distributor 7
One of the two signals to 3 remains unchanged and the other is provided to adder 16 via delay line 304 having a delay amount of 4T. Therefore, this correction circuit 13 uses the absolute delay amount of the main signal as a reference to calculate the second
The adder 16 combines the lead signal and the delay signal by a predetermined time period of 2T at the same level. The output signal of the adder 16 is applied to a variable coefficient loading circuit 18 through a known fixed attenuator 17. Variable coefficient loading circuit 18 has a coefficient l, and the output signal from this circuit 18 is provided to adder 19. Therefore, this adder 19 combines the output signal from the delay circuit 12 and the output signal from the correction circuit 13, and sends the combined output to the final stage adder 21 through the variable coefficient loading circuit 20. give. The variable coefficient loading circuit 20 is interlocked with the variable coefficient loading circuit 18 described above. Specifically, these variable coefficient loading circuits 18 and 20 use a double balanced mixer as shown in FIG.
(FIG. 10) by the same voltage Ve. Therefore, in this embodiment, the variable resistor
Just by changing the resistance value of VR (Figure 10),
The coefficient l of the two coefficient loading circuits 18 and 20 can be changed in conjunction.

Here, the main signal circuit and the amplitude correction circuit 13 are similar to the variable amplitude equalizer VAE shown in FIG. By doing so, only the amplitude changes without changing the amount of delay. The repetition period of the amplitude change by this correction circuit 13 is 1/2T. On the other hand, the main signal circuit and delay circuit 12
Assuming that there is no correction circuit 13, the repetition period of amplitude change is 1/2T. In the embodiment shown in FIG. 12, the repetition period of the amplitude characteristic of the correction circuit 13 is made the same as that of the delay circuit 12,
As a result, the amplitude change in the delay circuit 12 is canceled out by the output signal from the correction circuit 13, thereby making the amplitude change extremely small.

It is assumed that there is no signal attenuation except for the variable coefficient loading circuits 18 and 20 and the fixed attenuator 17, and that there is no time delay except for each delay line, the coefficient of the variable coefficient loading circuit 20 is l, and the fixed attenuator 17 and the variable coefficient loading When the coefficient including the circuits 18 and 20 is k, the signal C(ω) obtained at the output terminal 102 is given by the following equation (6).

C(ω)=cosωt−lcosω(t+T)+lcosω(t−T
) +kcosω(t-2T)+kcosω(t+T) +kcosω(t-2T)+kcosω(t+T) =√(1+2 ² )+2(- ² )2+4 ^2
2 × sin {ωt + tan ^-1・(1+2kcosωt)/2lsinωT} ...(6) Therefore, the amplitude characteristic of this output signal C(ω)
G _C (ω) is given by the following equation (7).

G _C (ω)=20log{√(1+2 ² )+2(2− ² )
2+4 ^{2 2} }...(7) The variable coefficient loading circuits 18 and 20 are interlocked and have the same coefficient l. Assuming that the fixed attenuator 17 has an attenuation of 6 dB, that is, a coefficient of 0.5,
The overall coefficient k is given by the following equation (8).

k=0.5×l×l=l ² /2 ...(8) When the above equation (8) is substituted into (7), the second term in the root symbol becomes 0, so the above equation (7) becomes It is given by the following equation (9).

G _C (ω) = 20log {√(1+2 ² ) + ^{4 2} } ...(9) Comparing the above equation (9) and the previous equation (2), the term that changes with the amplitude frequency is In equation (2), it is 2l ² cos2ωT, while in equation (9), it is l ⁴ cos ² ωT, and it can be seen that the coefficient becomes extremely small in the range of l<1. On the other hand, the delay characteristic τ _C (ω) at this time is given by the following equation (10).

τ _C (ω) = −2Tl×{l ² sin2ωT・sinωT + (l ² +1) cosωT/(1+2l ² ) +l ⁴ cos ² 2ωT)} ...(10) This amplitude characteristic G _C (ω) and delay characteristic FIG. 13 shows the change characteristics of τ _C (ω) with respect to the coefficient l. FIG. 13A shows the amplitude characteristics, and FIG. 13B shows the delay characteristics. As you can see from this Figure 13, the first
If the coefficient l of the two variable coefficient loading circuits 18 and 20 shown in FIG. 2 is increased, the amplitude and the amount of delay change in the directions of the arrows. And this 13th
From the figure, the amount of delay can be changed by changing the coefficient l, but on the other hand, the amplitude change can be changed by changing the coefficient l.
It turns out that there are almost no such cases.

Note that although it is assumed that there is no signal attenuation except for the variable coefficient loading circuit and the fixed attenuator, the above equation (12) holds regardless of the absolute amount of attenuation.
The same applies to time delays.

The graph in FIG. 13 shows amplitude changes and delay amount changes when coefficient l>0. In the range of coefficient l<0, the sign of the above equation (10) is reversed, and the lead and lag of the delay amount are opposite to the reference. However, even if the coefficient l<0, the above formula (10) will have the same value and will not be inverted if the absolute values of the coefficients l are equal. That is, when the coefficient l changes from + to -, the delay amount changes in an inverse manner as shown in FIG. 14, but the amplitude simply repeats the change shown in FIG. 13A. In this way, it will be understood that the embodiment of FIG. 12 can change only the amount of delay without changing the amplitude. Therefore, if such a variable delay equalizer VDE is used as a variable equalizer in a TDMA communication system, it will be possible to independently equalize only the degradation in BER due to group delay distortion, which will be Compared to the case where the amplitude and the delay amount change together as in the case of the conventional method, the operation to find the optimal point can be performed extremely easily.
Furthermore, by using such a variable delay equalizer and variable amplitude equalizer, the amount of equalization for each of amplitude distortion and delay distortion can be reliably grasped, and therefore, it is possible to accurately grasp the equalization amount for each of amplitude distortion and delay distortion. , reproducible data are obtained.

FIG. 15 is a circuit diagram showing another embodiment of the invention. In FIG. 15, the position where the variable coefficient loading circuit 20 is inserted has been changed compared to the embodiment in FIG. 12, and the variable coefficient loading circuit 1
The coefficient of 8' has been changed. That is, the 12th
In the illustrated embodiment, the variable coefficient loading circuit 20 is connected to the adder 19.
One of the variable coefficient loading circuits 1 is connected to the latter stage.
If the coefficient of 8' is multiplied by the square to obtain l ² , the variable coefficient loading circuit 20 can be placed between the adders 15 and 19 as shown in FIG. In principle, the two variable coefficient loading circuits are linked together so that the amplitude of the output signal from the correction circuit 13 is attenuated by a factor of two, that is, twice the amplitude of the output signal from the delay circuit 12, in decibel terms. That's all there is to it.

FIG. 16 is a circuit diagram showing another embodiment of the invention. The embodiment of FIG. 15 is similar to the embodiment of FIG. 12 except that the combination of the conventional branch circuit and delay line shown in FIG. 4 is used as the signal deriving means.

FIG. 17 is a circuit diagram showing another embodiment of the invention. In the embodiment shown in FIG. 17, the delay circuit and the correction circuit each have a plurality of sets of signal paths. That is, delay circuit 1
Adders 15 and 15' of 2' are combined to correspond to adders 16 and 16' of correction circuit 13', respectively. The output signal of adder 15' is attenuated by fixed attenuator 22, and the output signal of adder 16' is attenuated by fixed attenuator 22.
The output signal from is attenuated by a fixed attenuator 22'.
Fixed attenuators 22 and 22' each have a coefficient m
and has m ² . When a delay amount different from the variable delay amount caused by the combination of adders 15 and 16 is required, by setting the coefficients m and ^m2 in this way, the amplitude change of the signal passing through the adder 15' is controlled by the adder. 16', and the resulting signal obtained at the output terminal 102 changes only the amount of delay by changing the coefficient l of the variable coefficient loading circuits 18 and 20 in conjunction. can be done.

Note that in the above embodiment, a double balanced mixer was used as an example of the variable coefficient loading circuit. However, those skilled in the art will readily understand that such a variable coefficient loading circuit may be achieved with other circuit configurations.

Furthermore, in the embodiments of FIGS. 12, 15, 16, and 17, the polarity inverters 14, 1
4', a 180° phase shifter was used. however,
As such a polarity inverter, a 180° combiner, a 90° divider, or a combiner can also be used. For example, in the embodiment shown in FIG. 12, the same result can be obtained even if a 180° combiner is placed in the adder 15, or a 90° divider and combiner is placed in the part that sends the signal to the delay circuit between the adder 15 and the divider 7. is obtained. The point is that, for example, in the embodiment of FIG. 12, the two signals applied to the adder 15 do not end up having different polarities.

Similarly, variable coefficient loading circuit 18 (or 18')
and 20 also do not include polarity reversal, and another polarity inverter may be used. Further, these circuits 18, 18', and 20 may be interlocked so that the amplitudes of the output signal from the delay circuit 12 and the output signal from the correction circuit 13 become a constant ratio, and their insertion positions and coefficients may be arbitrarily selected as long as they satisfy such requirements. For example, in the embodiment of FIG. 12, variable coefficient loading circuits having predetermined coefficients may be arranged in the respective signal paths supplied to the delay circuit 12 and the correction circuit 13 so as to be able to interlock with each other.

In addition, we have described a TDMA communication system as an example in which a variable delay equalizer is used.
Needless to say, it can also be used for FDM communication systems, etc., if necessary.

As described above, according to the present invention, it is possible to obtain a variable delay equalizer that can vary only the frequency characteristics of the delay amount without changing the frequency characteristics of the amplitude. Also, if multiple variable coefficient loading circuits are linked together,
Adjustment of such a delay amount is easy. Furthermore, if the same variable coefficient loading circuits are linked together as in the embodiment, a highly accurate variable delay equalizer with a very simple circuit configuration can be obtained at a lower cost.

[Brief explanation of the drawing]

FIG. 1 shows the concept of a TDMA communication system which is the background of this invention. FIG. 2 is a graph showing the characteristics of a high-power amplifier included in a communication satellite. Third
The figure is a block diagram showing an example of an equalizer used in a TDMA communication system. FIG. 4 is a circuit diagram showing an example of a conventional variable equalizer. FIG. 5 is a circuit diagram showing another example of the variable equalizer. FIG. 6 is a graph showing the frequency characteristics of the amplitude and delay amount in the example of FIG. FIG. 7 is a block diagram showing an example of an equalizer used in a TDMA communication system as an embodiment of the present invention. 8th
The figure is a circuit diagram showing an example of a variable amplitude equalizer.
FIG. 9 is a graph showing the amplitude frequency characteristics of the embodiment shown in FIG. FIG. 10 is a circuit diagram showing an example of a variable coefficient loading circuit. FIG. 11 is a graph explaining the operation of the embodiment shown in FIG. FIG. 12 is a circuit diagram showing an example of a variable delay equalizer. 13th
This figure is a graph showing the frequency characteristics of the amplitude and the amount of delay in the embodiment of FIG. 12. FIG. 14 is another graph showing the frequency characteristics of the amount of delay. FIG. 15 is a circuit diagram showing another example of a variable delay equalizer. FIG. 16 is a circuit diagram showing still another example of a variable delay equalizer. FIG. 17 is a circuit diagram showing another example of the variable delay equalizer. In the figure, EQL is an equalizer, VAE is a variable amplitude equalizer, VDE is a variable delay equalizer, 101 is an input terminal, 102 is an output terminal, 3, 31, 301 to 304 and 311 to 318 are delay lines, 1
4, 14' are polarity inverters, 15, 15', 16, 1
6', 19, 21, 24, 25 are adders, 18,
18' and 20 indicate variable coefficient loading circuits.

Claims (1)

[Scope of Claims] 1. A signal input section, and distributes and delays input signals from the signal input section to at least output the main signal and the first, second, and third signals.
and signal deriving means for deriving a fourth signal, wherein the first and second signals are a first predetermined time lead signal and a first delay signal, respectively, based on the absolute delay amount of the main signal. The third and fourth signals are a second predetermined time lead signal and a second delay signal, respectively, with respect to the absolute delay amount of the main signal, and the first and second signals are mutually polarized. a first polarity reversing means for synthesizing the first and second signals having different polarities and the same level; and a first combining means for synthesizing the first and second signals having different polarities and the same level; a correction signal generation means for synthesizing and outputting an amplitude correction signal; amplitude changing means; second polarity inverting means for inverting the polarity of the output signal from the first combining means compared to the original output signal; and the first combining means having a different polarity and a predetermined amplitude ratio. A variable delay equalizer comprising second combining means for combining the output signal from the combining means and the output signal from the correction signal generating means together with the main signal. 2. The correction signal generating means includes: adder means for combining the third and fourth signals of the same level; and fixed attenuator means for attenuating the output signal from the adder means by a fixed amount. A variable delay equalizer according to claim 1. 3. The variable delay equalizer according to claim 1 or 2, wherein the second predetermined time is selected to be twice the first predetermined time. 4. The amplitude changing means changes the amplitude of the output signal from the correction signal generating means to the square of the amplitude of the output signal from the first combining means (twice in decibels).
4. A variable delay equalizer as claimed in claim 3, including amplitude adjustment means for attenuation. 5. The amplitude adjustment means is inserted into a signal path that affects the amplitude of the output signal from the first synthesis means and a signal path that affects the amplitude of the output signal from the correction signal creation means, and 5. A variable delay equalizer as claimed in claim 4, comprising at least two interlocking variable coefficient weighting circuits. 6. The second combining means includes: a first adder for combining the output signal from the first combining means and the output signal from the correction signal generating means; and the main signal and the first adder. 6. The variable delay equalizer of claim 5, further comprising a second adder for combining the output signals from the variable delay equalizer. 7. The amplitude adjusting means includes: a first variable coefficient loading circuit interposed between the correction signal generating means and the first adder; and a first variable coefficient loading circuit interposed between the first adder and the second adder. 7. The variable delay equalizer according to claim 6, further comprising a second variable coefficient loading circuit interposed in said first variable coefficient loading circuit and interlocking with said first variable coefficient loading circuit. 8. The variable delay equalizer according to claim 7, wherein the second polarity inversion means is included in the second variable coefficient loading circuit. 9. The amplitude adjustment means includes: a first variable coefficient loading circuit interposed between the first synthesis means and the first adder; and a first variable coefficient loading circuit interposed between the correction signal generation means and the first adder. a second variable coefficient loading circuit interposed in the circuit, interlocking with the first variable coefficient loading circuit, and having a coefficient that is twice the coefficient of the first variable coefficient loading circuit (twice in decibel conversion); 7. A variable delay equalizer as claimed in claim 6. 10. The variable delay equalizer according to claim 9, wherein the second polarity inversion means is included in the first and second variable coefficient loading circuits. 11. The variable delay equalizer according to claim 6, wherein the amplitude adjusting means includes a plurality of mutually interlocking variable coefficient loading circuits interposed in paths of each of the first to fourth signals. 12 The signal deriving means includes: a distribution circuit for distributing the input signal from the signal input section into at least the five signals; and a necessary delay circuit inserted in each signal path from the distribution circuit. The variable delay equalizer according to item 1. 13. The first polarity inverting means is inserted between the necessary delay circuit and the first combining means in either the first signal path or the second signal path. Claim 1
Variable delay equalizer according to item 2. 14. The first polarity inverting means is interposed between the necessary delay circuit and the distribution circuit in either one of the first signal path and the second signal path. The variable delay equalizer according to range 12. 15. Claim 1, wherein the signal deriving means includes: a plurality of branch circuits that receive input signals from the signal input section and are connected in cascade; and a delay circuit inserted between each of the branch circuits. Variable delay equalizer as described. 16 The first polarity inverting means connects one of the branch circuit for taking out the first signal and the branch circuit for taking out the second signal and the first polarity inverting means.
16. The variable delay equalizer according to claim 15, which is inserted between the variable delay equalizer and the combining means. 17. The variable delay equalizer according to claim 1, wherein a plurality of sets of the first synthesizing means and the correction signal generating means are each provided.