JPS6348189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor integrated circuit including a power transistor.

Transistors in semiconductor integrated circuits are called PN
A structure in which the emitter, base, and collector electrodes are formed in island-like regions separated by bonding and taken out from the surface of the semiconductor substrate is well known. When a transistor with this structure is used for power purposes and can draw a large output current, a low-resistance collector region is buried at the bottom of the island-like region, and highly concentrated impurities are diffused from the surface of the semiconductor substrate to form the buried collector region. A commonly used method is to form a collector draw-out area that reaches . However, as long as the collector electrode is formed on the surface of the semiconductor substrate, the current path for the collector current becomes quite long, and there is a limit to reducing the resistance value of this path. Therefore, the collector saturation voltage V _CE (sat) of the transistor becomes large, resulting in a drawback that power loss within the semiconductor substrate is large. Furthermore, since a considerable area is required for the collector electrode, there is also the disadvantage that the area of the semiconductor substrate (chip size) becomes large.

As a structure that can overcome these drawbacks, a structure is known in which a collector electrode is taken out from the back surface of a semiconductor substrate, similar to a discrete power transistor. An integrated circuit with this structure is shown in Figs.
It is formed as shown in FIG.

That is, first, as shown in FIG. 1, an N type semiconductor region 2 having high resistivity (specific resistance) is formed on an N ⁺ type semiconductor substrate 1 by epitaxial growth. next,
A P-type semiconductor region 3 is formed by diffusion in a region 2 where a plurality of circuit elements (here, small signal transistors and resistors) are to be formed. Furthermore, there is an N ⁺ type region 4 which becomes the buried collector region of the small signal transistor.
and an N ⁺ type region 5, which serves as a region for preventing parasitic leakage current of the resistor, are formed in region 3 by diffusion.

Next, as shown in FIG.
4 and 5), a high resistivity N-type semiconductor region 6 is formed by epitaxial growth.

Next, as shown in FIG. 3, a P-type region 7, which will become the base region of the power transistor, is formed in the region 6 where the power transistor is to be formed (the tip of the region 7 reaches the region 2). ). Further, a P-type region 8 is formed in the region 6 by diffusion so as to separate the portions of the region 6 where a plurality of circuit elements are to be formed. In addition, in the area 6 where a plurality of circuit elements are to be formed, an N-type area 6a where a small signal transistor is to be formed and an N-type area 6b where a resistor is to be formed.
A P-type region 9 is formed by diffusion to separate the two.

Next, as shown in FIG. 4, an N ⁺ type region 10 which will become the emitter region of the power transistor and an N ⁺ type region 11 which will serve as the collector extraction region of the small signal transistor are formed by diffusion in the regions 7 and 6a, respectively. . Next, a P-type region 12 that will become a base region of a small signal transistor and a P-type region 13 that will become a resistance region are formed by diffusion in regions 6a and 6b, respectively. Furthermore, an N ⁺ type region 14 which acts as an emitter series resistance of a power transistor and an N ⁺ type region 15 which serves as an emitter region of a small signal transistor are formed by diffusion. Finally, the emitter, base, and collector electrodes 16, 17, and 18 of the power transistor, and the emitter, base, and collector electrodes 19, 20, and
21 and resistor electrodes 22 and 23 are formed. The surface of the semiconductor substrate is covered and protected with a SiO ₂ film 24.

Note that in FIGS. 1 to 3, the SiO ₂ film formed for use as a selective diffusion mask is omitted. Further, in FIG. 4, wiring electrodes connecting each element inside the semiconductor integrated circuit are omitted. Further, although it is common to form a plurality of regions 10 and 14, which are emitter regions of a power transistor, to form a multi-emitter structure, they are shown here as a single-emitter structure.

In such a semiconductor integrated circuit, regions 1 and 2
This serves as a substrate on which a plurality of circuit elements are constructed, and also serves as a collector region of a power transistor. Therefore, the collector saturation voltage V _CE (sat) of the power transistor can be made as small as that of an individual element, and the chip size does not increase due to the area required for the collector electrode of the power transistor.

However, there are still problems to be solved.
That is, regions 2 and 6 are usually formed as a so-called double epitaxial region, in which two regions grown by epitaxial growth are stacked one on top of the other. In this case, region 6, which is the epitaxial region of the second layer, inevitably has more crystal defects (dislocations, stacking faults, etc.) than region 2 of the first layer, and this region 6 with poor crystallinity is used as a power transistor. This will form active regions for a plurality of circuit elements. This poor crystallinity has little effect on a plurality of circuit elements that do not require a very high breakdown voltage, but it does have a considerable effect on power transistors that have a relatively high breakdown voltage and a large area. Power transistors generally have high breakdown voltage characteristics (collector-base voltage V _CBO ,
The collector-emitter voltage ( _VCEO ) deteriorates. There are also negative effects such as a decrease in manufacturing yield. Note that there is also a method of forming region 1 by performing high concentration diffusion for a long time in a high resistivity N type substrate, and forming the remaining region 2. According to this method, it is not necessary to perform double epitaxial growth. However, even in this case, crystal defects (dislocations, stacking faults, scratches, etc.) occur quite often. The poor crystallinity near the surface of the region 6 causes deterioration of the breakdown voltage characteristics of the power transistor and a decrease in manufacturing yield, as described above.

Furthermore, in power transistors, an emitter series resistor is often provided as a stabilizing balance resistor to prevent secondary damage due to current concentration.
In the conventional structure shown in FIG. 4, the lateral resistance of region 14 is utilized to provide emitter series resistance. Therefore, region 14 requires a certain amount of area, which has the drawback of increasing the chip size accordingly. Another disadvantage is that when a large current is passed, the current density in the region 14 becomes extremely large, and the emitter series resistor is likely to be destroyed by burning.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit including a power transistor that can solve the above-mentioned drawbacks.

To achieve the above object, the present invention will be explained with reference to the reference numerals in FIGS. 5 to 11 of the embodiment drawings for ease of understanding. a semiconductor region 31 and a second semiconductor region of a first conductivity type and high resistivity adjacent to the first semiconductor region 31;
a third semiconductor region 33 of a second conductivity type opposite to the first conductivity type formed so as to be partially surrounded by the second semiconductor region 32;
, a portion thereof is surrounded by the second semiconductor region 32 and the third semiconductor region 3
3, a fourth semiconductor region 34 of the second conductivity type separated from the third semiconductor region 3; a fifth semiconductor region 35 of the first conductivity type formed so as to be partially surrounded by the third semiconductor region 33; at least the second semiconductor region 3
2, an epitaxial growth layer 38 of a first conductivity type and high resistivity formed to cover the third semiconductor region 33, the fourth semiconductor region 34, and the fifth semiconductor region 35; The third semiconductor region 33 extends through the epitaxial growth layer 38.
a second conductivity type sixth semiconductor region 39 formed to reach the epitaxial growth layer 38;
a seventh semiconductor region 38a of the first conductivity type provided on at least the fifth semiconductor region 35 based on a portion of the epitaxial growth layer 38;
an eighth semiconductor region 40 of a second conductivity type formed to extend through the fourth semiconductor region 34 and annularly surround a part of the epitaxial growth layer 38; a ninth semiconductor region 38b, 38c consisting of a part of the epitaxial growth layer 38 surrounded by the region 40; a small signal transistor, for example, formed in the ninth semiconductor region 38b, 38c; A circuit element such as a resistor, a collector electrode 50 of a power transistor provided in the first semiconductor region 31, a base electrode 49 of a power transistor provided in the sixth semiconductor region 39, and the seventh an emitter electrode 48 of the power transistor provided to be connected to the semiconductor region 38a of the power transistor, and the first and second semiconductor regions 31 and 32 are connected to the collector region of the power transistor and the emitter electrode 48 of the power transistor The third semiconductor region 33 is a base region of the power transistor, the fifth semiconductor region 35 is an emitter region of the power transistor, the sixth semiconductor region 39 is a base lead-out region of the power transistor, and the fifth semiconductor region 35 is an emitter region of the power transistor. This example relates to a semiconductor integrated circuit in which the semiconductor region 38a of No. 7 functions as an emitter series resistance region.

According to the present invention, since the active region of the power transistor is formed away from the surface of the semiconductor substrate, the adverse effects of crystal defects that are likely to occur near the surface of the semiconductor substrate are reduced, and the breakdown voltage of the power transistor is reduced. Disadvantages such as deterioration of characteristics and reduction in manufacturing yield are reduced. Additionally, no extra area is required to form the emitter series resistor of the power transistor, resulting in chip size savings. Furthermore, this emitter series resistor has a large current capacity, so that burnout and destruction of the emitter series resistor is unlikely to occur.

Hereinafter, a method and structure for manufacturing an integrated circuit according to an embodiment of the present invention will be described with reference to FIGS. 5 to 11.

FIGS. 5 to 11 show cross sections at various steps in forming an integrated circuit including power transistors using a semiconductor silicon substrate. First, as shown in FIG. 5, a second N ^- type semiconductor region 31 lightly doped with phosphorus is grown by epitaxial growth on a first semiconductor region 31 made of an N + type (first conductivity type) substrate with a thickness of approximately 250 μm. A semiconductor region 32 is formed. The first and second semiconductor regions 31 and 32 not only function as a substrate for an integrated circuit, but also function as a collector region of a power transistor.
Note that the resistivity of the region 32 is as high as 10 to 15 Ω·cm, and the thickness is about 40 μm. Next, area 32
A P-type (second conductivity type) third semiconductor region 33, which will become a base region of the power transistor, is formed in the portion where the power transistor is to be formed. In addition, a plurality of circuit elements in the region 32 (usually a large number of circuit elements such as transistors, diodes, and resistors are formed, but to simplify the explanation, we will use a simple example of one small signal transistor and one resistor). ) is to be formed, a P-type fourth semiconductor region 34 is formed. Regions 33 and 34 are formed simultaneously by diffusing boron, which is a P-type impurity, from the surface of region 32, and the surface impurity concentration is approximately 1×.
10 ¹⁶ atoms/cm ³ , and the depth is approximately 10 μm. In addition,
Regions 31 and 32 directly below region 33 and their surrounding regions become collector regions of the power transistor.

Next, as shown in FIG. 6, a fifth N ⁺ type semiconductor region 35 is formed in the region 33 to serve as the emitter region of the power transistor. Also, the N ⁺ type semiconductor region 36 becomes the buried collector region of the small signal transistor and the region to prevent parasitic leakage current of the resistor.
An N ⁺ type semiconductor region 37 is formed within region 34.
Regions 35, 36, and 37 are simultaneously formed by diffusing antimony or arsenic, which is an N-type impurity, from the surface of region 33 or 34, and the surface impurity concentration is approximately 8+10 ¹⁹ atoms/cm ³ and the depth is approximately 5 μm. .

Next, as shown in FIG. 7, a region 38 consisting of an N-type epitaxial growth layer lightly doped with phosphorous is formed on the regions 32 to 37 by an epitaxial growth method. The region 38 made of this epitaxially grown layer has a high resistivity of about 10 to 15 Ω·cm, and has a thickness of about 12 μm.

Next, as shown in FIG. 8, a P-type sixth semiconductor region 39 is formed to be connected to the third semiconductor region 33 to be a base region of the power transistor and to be a base lead-out region. The region 39 annularly surrounds the N-type seventh semiconductor region 38a, which serves as the emitter series resistance region of the power transistor, and isolates the region 38a from the collector region of the power transistor. Further, the fourth semiconductor region 34
Eighth P-type semiconductor regions 40 and 41 are formed in the region 38 to be connected to and serve as isolation regions. area 40
In this embodiment, a portion of the region 38 where a plurality of circuit elements are to be formed is surrounded in an annular shape, and this portion is insulated and isolated from the collector region of the power transistor. The region 41 insulates and isolates the N-type ninth semiconductor region 38b in which a small signal transistor is to be formed and the region 38c in which a resistor is to be formed. Area 39, 40,
41 is simultaneously formed by diffusing boron, which is a P-type impurity, from the surface of region 38, and the surface impurity concentration is approximately 1×10 ¹⁹ atoms/cm ³ and the depth is approximately 10 μm (regions 33 and 34 are located above). (It may be slightly shallower than the thickness of the region 38 in order to expand the thickness of the region 38.)

Next, as shown in FIG. 9, there is formed a tenth N ⁺ type semiconductor region 42 which serves as an emitter electrode connection region, and an N ⁺ type which acts to reduce the hole current injected from the region 39 to the region 38a. An eleventh semiconductor region 43 is formed in the region 38a. Also, area 38
An N ⁺ type semiconductor region 44 is formed at b to serve as a collector lead-out region of a small signal transistor. Note that the regions 42 are formed in a dispersed manner in the form of islands. Region 43 is adjacent to the surface side portion of region 39 . area 42,
43 and 44 are simultaneously formed by diffusing phosphorus, which is an N-type impurity, from the surface of the region 38, and the surface impurity concentration is about 1×10 ²⁰ atoms/cm ³ and the depth is about 5 μm.

Next, as shown in FIG. 10, a P-type semiconductor region 45, which will become the base region of the small signal transistor, is formed in the region 38b. Further, a P-type region 46 which becomes a resistance region is formed in the region 38c. Regions 45 and 46 are simultaneously formed by diffusing boron, which is a P-type impurity, from the surface of region 38, and the surface impurity concentration is approximately 5.
×10 ¹⁸ atoms/cm ³ , and the depth is approximately 3 μm.

Next, as shown in FIG. 11, phosphorus, which is an N type impurity, is diffused from the surface of the region 45 to form an N ⁺ type region 47 in the region 45, which will become the emitter region of the small signal transistor. The surface impurity concentration of the region 47 is about 1×10 ²⁰ atoms/cm ³ and the depth is about 1.5 μm.
Next, the collector electrode 50 of the power transistor is placed on the first semiconductor region 31, the base electrode 49 of the power transistor is placed on the sixth semiconductor region 39, and the electrode is placed on the seventh semiconductor region 38a and the tenth semiconductor region 42. The emitter electrode 48 of the power transistor, the emitter, base, and collector electrodes 51, 52, 53 of the small signal transistor, and the resistor electrodes 54, 5
5 are formed by vapor deposition of aluminum. The surface of the semiconductor substrate is covered and protected with a SiO ₂ film 56. Note that in FIGS. 5 to 11, the SiO ₂ film formed for use as a selective diffusion mask or the like is omitted. Also the 11th
In the figure, wiring electrodes connecting each element inside the semiconductor integrated circuit are omitted.

By configuring the semiconductor integrated circuit as described above, the following advantages can be obtained.

(a) The main part of the active region of the power transistor is formed in the second semiconductor region 32, which is the first layer of the double epitaxial region, and is formed in the second layer of the double epitaxial region, which will eventually become the surface region. Region 3 consisting of a certain epitaxially grown layer
The region 38 made of this epitaxially grown layer, which is not formed in the epitaxial layer 8, is mainly used as a seventh semiconductor region 38a for obtaining an emitter series resistance with respect to the power transistor. Therefore, the probability that crystal defects, which occur in large numbers in the region 38 made of the epitaxially grown layer, will lead to disadvantages such as deterioration of the breakdown voltage of the power transistor and reduction in manufacturing yield is greatly reduced. As a result, it has become possible to manufacture semiconductor integrated circuits including high-voltage transistors for power use with a high manufacturing yield.

(b) Region 38a, which is the emitter series resistance region of the power transistor, is region 3, which is the emitter region.
5 and the emitter series resistance is in area 38
The vertical bulk resistance of a is used. Therefore, adding an emitter series resistor to the power transistor does not increase the chip size, and there are no problems such as increased costs or decreased manufacturing yield due to increased chip size.

(c) The path of the current flowing through the emitter series resistor of the power transistor extends over substantially the entire area (entire cross section) of the region 38a. Therefore, the current capacity of the emitter series resistor is large, and a burnout accident of the emitter series resistor is unlikely to occur. Note that in order to connect the emitter electrode 48 to the high resistivity region 38a with low resistance, it is a common practice to form a low resistivity region as an electrode connection region. In the above embodiment, an N ⁺ type (first conductivity type) is provided on the surface side of the seventh semiconductor region 38a as the emitter electrode connection region.
A plurality of tenth semiconductor regions 42 having low resistivity are arranged in a dispersed manner in the form of islands. In this case, the emitter series resistance uses the bulk resistance of the region 38a between the tip of the region 42 and the region 35, and since the region 42 is distributed in the region 38a, the emitter series resistance Area 38a
It will be distributed and arranged. Therefore, the current flows in a distributed manner in the region 38a, which is the emitter series resistance region, and the emitter series resistance becomes more difficult to burn out. Moreover, the effect of this current dispersion is
Since it acts in a direction that prevents the current flowing from the base region to the region 33, which is the base region, to concentrate, there is also an advantage that the secondary breakdown resistance of the power transistor is improved.

(d) Formed at the boundary between the region 39 that is the base extraction region of the power transistor and the region 38a that is the emitter series resistance region, that is, on the surface side of the seventh semiconductor region 38a and adjacent to the sixth semiconductor region 39. The eleventh semiconductor region 43 reduced in current due to holes (majority carriers in the region 39) injected from the region 39 to the region 38a,
It plays a role in improving the linearity of the current amplification factor h _FE of the power transistor. area 43
If there is no impurity concentration, the region 39 with a low impurity concentration will be moved from near the surface of the region 39 with a high impurity concentration due to diffusion.
The hole current injected into 8a becomes large and the proportion of this hole current in the base current is large in the low current region, so h _FE in the low current region decreases and the linearity of h _FE deteriorates. Since the impurity concentration due to diffusion is considerably lower in the lower part of the region 39, the hole current injected from there into the region 38a is small. Therefore, area 39
There is no practical problem even if the region 43 does not extend to the bottom of the screen.

(e) In the manufacturing method explained in FIGS. 5 to 11,
Since regions 33 and 34, regions 35, 36 and 37, and regions 39, 40 and 41 are formed at the same time, it becomes possible to rationally manufacture a semiconductor integrated circuit.

Although the embodiments have been described above, the present invention is not limited to these embodiments, and various changes can be made without departing from the spirit of the invention. For example, the power transistor may have a multi-emitter structure, or may have two transistors connected in a Darlington connection. Alternatively, the region formed by diffusing impurities may be formed by implanting impurity ions using an ion implantation method. Further, the resistivity, impurity concentration, dimensions, etc. of each region may be variously changed depending on desired characteristics. Further, the second semiconductor region 32, which serves as the collector high resistance region of the power transistor, is usually formed by epitaxial growth, and the effects of the present invention are significant in this case.
However, even if the first semiconductor region 31, which serves as the collector low resistance region of the power transistor, is formed on a high resistivity semiconductor substrate by diffusion, and the remaining region is used as the second semiconductor region 32, the effects of the present invention will not be sufficiently exhibited. Ru.

[Brief explanation of the drawing]

1, 2, 3, and 4 are cross-sectional views showing the state of each manufacturing process of conventional integrated circuits, and FIG. 5, FIG. 6, FIG. 7, FIG. 8, and FIG. Figures 9 and 10
11 and 11 are cross-sectional views showing states of each manufacturing process of an integrated circuit according to an embodiment of the present invention. In the reference symbols used in the drawings, 31 is the first semiconductor region, 32 is the second semiconductor region, and 3 is the first semiconductor region.
3 is a second semiconductor region, 34 is a fourth semiconductor region, 35 is a fifth semiconductor region, 38 is an epitaxial growth layer, 38a is a seventh semiconductor region, 40 is an eighth semiconductor region, 38b, 38c is the ninth semiconductor region.

Claims (1)

[Claims] 1. First semiconductor region 3 of first conductivity type and low resistivity.
1, a second semiconductor region 32 of a first conductivity type and high resistivity adjacent to the first semiconductor region 31, and a second semiconductor region 32 formed so as to be partially surrounded by the second semiconductor region 32. a third semiconductor region 33 of a second conductivity type opposite to the first conductivity type; a third semiconductor region 33 formed so as to be partially surrounded by the second semiconductor region 32;
a fourth semiconductor region 3 of the second conductivity type separated from the
4, and a fifth semiconductor region 3 of the first conductivity type formed so as to be partially surrounded by the third semiconductor region 33.
5, and at least the second semiconductor region 32, the third semiconductor region 33, and the fourth semiconductor region 34.
The third semiconductor region 3 is formed by penetrating the first conductivity type and high resistivity epitaxial growth layer 38 formed to cover the third semiconductor region 35 and the fifth semiconductor region 35 .
a sixth semiconductor region 39 of the second conductivity type formed so as to reach 3; and a first conductivity type provided on at least the fifth semiconductor region 35 based on a part of the epitaxial growth layer 38; seventh semiconductor region 38a of the mold
and an eighth semiconductor region of a second conductivity type formed to penetrate through the epitaxial growth layer 38 to reach the fourth semiconductor region 34 and to annularly surround a part of the epitaxial growth layer 38. 40, and a ninth region comprising a portion of the epitaxial growth layer 38 surrounded by the eighth semiconductor region 40.
a semiconductor region formed in the ninth semiconductor region, a collector electrode 50 of a power transistor provided in the first semiconductor region 31, and a semiconductor circuit element formed in the ninth semiconductor region 39; a base electrode 49 of a power transistor provided; and an emitter electrode 48 of the power transistor provided so as to be connected to the seventh semiconductor region 38a; Area 31,
32 is a collector region of the power transistor;
The third semiconductor region 33 is a base region of the power transistor, the fifth semiconductor region 35 is an emitter region of the power transistor, the sixth semiconductor region 39 is a base extraction region of the power transistor, and Said seventh semiconductor region 3
A semiconductor integrated circuit configured such that 8a acts as an emitter series resistance region. 2. The semiconductor integrated circuit according to claim 1, wherein the second semiconductor region 32 is a region formed by an epitaxial growth method. 3. The seventh semiconductor region 38a has, on its surface side, a plurality of regions 42 of the first conductivity type and low resistivity connected to the emitter electrode 48 and distributed in an island shape. The semiconductor integrated circuit according to the range 1 or 2. 4. The seventh semiconductor region 38a has a region 43 of the first conductivity type and low resistivity in a portion adjacent to the sixth semiconductor region 39 on its surface side. Or the semiconductor integrated circuit according to item 2 or 3.