JPS6348838A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6348838A JPS6348838A JP19203086A JP19203086A JPS6348838A JP S6348838 A JPS6348838 A JP S6348838A JP 19203086 A JP19203086 A JP 19203086A JP 19203086 A JP19203086 A JP 19203086A JP S6348838 A JPS6348838 A JP S6348838A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- type
- alloy
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910000676 Si alloy Inorganic materials 0.000 claims abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 abstract description 10
- 239000000956 alloy Substances 0.000 abstract description 10
- 238000005275 alloying Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229910000952 Be alloy Inorganic materials 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置のためのヒユーズ素子を形成するためにp型
シリコン基板の表面の絶縁層にコンタクトホールを形成
し、このコンタクトホールをアルミニウム(i)で埋め
込み、A6/Si接合部を作るにおいて、A/ /Si
(n” 1m)接合部を合金化してp型層を形成し、
p−nジャンクションにして絶縁(非導通)状態を作る
。Detailed Description of the Invention [Summary] In order to form a fuse element for a semiconductor device, a contact hole is formed in an insulating layer on the surface of a p-type silicon substrate, and this contact hole is filled with aluminum (i). /Si In making the joint, A/ /Si
(n” 1m) alloy the junction to form a p-type layer,
Create an insulated (non-conducting) state by creating a p-n junction.
C産業上の利用分野〕
本発明は半導体装置の製造方法に関し、さらに詳しく言
えば、アルミニウム(A7りと半導体基板(シリコン基
板)の接合部を合金化することによりヒユーズ素子を形
成する方法に関するものである。C. Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for forming a fuse element by alloying the joint between aluminum (A7) and a semiconductor substrate (silicon substrate). It is.
D −RAMなどのしSIにおいては冗長回路内で切断
を行うために多結晶シリコン(ポリシリコン)ヒユーズ
が設置されている。第2図を参照すると、21は選択用
(スイッチング)トランジスタ、22はヒユーズ、23
は冗長回路である。LSIの製作においてテストを行い
、不良部分のあることが判明すればそれを冗長回路につ
なぎ代え、またテストの拮果が完全であれば冗長回路を
切断する。それにはトランジスタをスイッチングさせ、
大電流を流して冗長回路へのヒユーズを切断する。In an SI such as a D-RAM, a polycrystalline silicon (polysilicon) fuse is installed to perform disconnection within a redundant circuit. Referring to FIG. 2, 21 is a selection (switching) transistor, 22 is a fuse, and 23 is a selection (switching) transistor.
is a redundant circuit. Tests are performed during LSI manufacturing, and if a defective part is found, it is connected to a redundant circuit, and if the test results are perfect, the redundant circuit is disconnected. To do this, switch transistors,
Cut the fuse to the redundant circuit by applying a large current.
従来例のヒユーズは第3図の平面図に示され、図におい
て、24はポリシリコンヒユーズ、25はそれぞれトラ
ンジスタと冗長回路とをつなぐアルミニウム(八2)配
線層である。図示のヒユーズを切断するには、Aβ配線
Ji25に大電流を流し、ポリシリコンヒユーズ24の
幅の狭くなった部分24aを溶融し、焼き切ってAe配
線層25の間の接続を切断する(絶縁する)。A conventional fuse is shown in the plan view of FIG. 3, where 24 is a polysilicon fuse and 25 is an aluminum (82) wiring layer that connects the transistor and the redundant circuit. To cut the fuse shown in the figure, a large current is applied to the Aβ wiring Ji 25 to melt the narrowed portion 24a of the polysilicon fuse 24 and burn it out, cutting the connection between the Ae wiring layers 25 (insulating do).
従来のポリシリコンヒユーズは第3図に示す如(平面状
に延在する構成のものであるので、LSIの集積化を阻
害し、またヒユーズをLSI内に形成するためのプロセ
スが複雑化する問題がある。As shown in Figure 3, conventional polysilicon fuses have a planar configuration, which hinders the integration of LSIs and complicates the process for forming fuses in LSIs. There is.
本発明はこのような点に鑑みて創作されたもので、LS
Iの冗長回路の切断などに用いるヒユーズ素子を、従来
例の如く面積をとることなく LSI回路が形成された
半導体基板内に製作する方法を提供することを目的とす
る。The present invention was created in view of these points, and the LS
It is an object of the present invention to provide a method for manufacturing a fuse element used for cutting a redundant circuit of an I in a semiconductor substrate on which an LSI circuit is formed, without taking up a large area as in the conventional example.
第1図fa)と[blは本発明実施例の断面図で、図中
、11はp型シリコン(Si)基板、12はシリコン基
板11内に形成されたn+型層、13は絶縁膜(SiO
2膜)、14はA7!配線である。1 fa) and [bl are cross-sectional views of the embodiment of the present invention, in which 11 is a p-type silicon (Si) substrate, 12 is an n+-type layer formed in the silicon substrate 11, and 13 is an insulating film ( SiO
2 membranes), 14 is A7! It's the wiring.
本発明においては、SiO2膜13全13されたコンタ
クトホール16を1配線14で埋め込み、コンタクトホ
ール内で基板とA7!配線の接合部分すなわち八jf/
5t(n+型層)の接合部を第1図(blに示す如(合
金化してA7!・Siのp型層15を形成し、p−nジ
ャンクション(接合)を作ってAl配線14を絶縁(非
導通)状態にする。In the present invention, the contact hole 16 in which the entire SiO2 film 13 is formed is filled with one wiring 14, and the substrate and A7! The joint part of the wiring, i.e. 8jf/
5t (n+ type layer) is alloyed as shown in Figure 1 (bl) to form a p-type layer 15 of A7!Si, create a p-n junction (junction), and insulate the Al wiring 14. (non-conducting) state.
第1図(a)に示す状態では電流は矢印■の方向にもそ
の反対方向にも流れることができて導通状態にあるが、
AJ/Siの接合部にp型のAl −Si合金層15を
作ると、第1図fb)に矢印■で示す電流はn−p接合
部に障壁ができて合金層15で流れなくなって非導通状
態になり、また前記と反対方向の電流の流れの場合も反
対側のコンタクトホールにおいて同様の現象が発生する
。In the state shown in Figure 1(a), current can flow in the direction of the arrow ■ and in the opposite direction, and is in a conductive state.
When a p-type Al-Si alloy layer 15 is formed at the AJ/Si junction, the current indicated by the arrow ■ in Fig. 1fb) is blocked by the alloy layer 15 due to a barrier formed at the n-p junction, and becomes non-current. A similar phenomenon occurs in the contact hole on the opposite side when the contact hole becomes conductive and current flows in the opposite direction to that described above.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
先ず第1図(alを参照すると、p型シリコン基板11
に公知の技術でn+型層12を作り、シリコン基板11
上に例えば1μmの厚さのSiO2膜13全13、次い
でSiO2膜13全13タクトホール16を窓開けし、
引続き厚さが例えば1μmのA1配線14をn+型層1
2を経て導通するようパターニングする。First, referring to FIG. 1 (al), a p-type silicon substrate 11
The n+ type layer 12 is formed using a technique known in the art, and the silicon substrate 11 is
For example, a 1 μm thick SiO2 film 13 is opened on top of the SiO2 film 13, and then a tact hole 16 is opened in the SiO2 film 13, and
Subsequently, the A1 wiring 14 having a thickness of, for example, 1 μm is formed into the n+ type layer 1.
Patterning is performed so that conduction occurs through step 2.
この状態で電流は矢印1方向またはその反対方向に流れ
ることができる。In this state, current can flow in the direction of arrow 1 or in the opposite direction.
次に、第1図(blに示される如く、コンタクトホール
領域にレーザパルス17を照射する。連続波(CW)レ
ーザビームはそれを照射するとへβ配線14が剥がれる
ことがあるので用いない。このレーザパルスの加熱によ
ってコンタクトホール領域のAAが溶融し、Al/Si
の接合部が合金化されて^1si合金層15が形成され
る。この合金化にはAlが高い吸収係数をもった光を発
振するレーザが必要であり、また合金層15が深くなり
すぎてn+層12を突き抜けることのないように、例え
ばパワーが約5J/c、n’のArFエキシマレーザの
パルスを照射する。Aj’は元素周期表で3価の元素で
あるのでAjl!Si合金層15はp型Si層となる。Next, as shown in FIG. 1 (bl), the contact hole area is irradiated with a laser pulse 17.Continuous wave (CW) laser beam is not used because the β wiring 14 may be peeled off when irradiated with it. AA in the contact hole area is melted by the heating of the laser pulse, and the Al/Si
The joint portion is alloyed to form the ^1si alloy layer 15. This alloying requires a laser that emits light with a high Al absorption coefficient, and in order to prevent the alloy layer 15 from becoming too deep and penetrating the n+ layer 12, the power must be set to about 5 J/c, for example. , n' are irradiated with ArF excimer laser pulses. Aj' is a trivalent element in the periodic table of elements, so Ajl! The Si alloy layer 15 becomes a p-type Si layer.
この合金層15は基板11内だけでなく接合部のAl中
にも拡がる。This alloy layer 15 spreads not only within the substrate 11 but also into the Al of the joint.
A//5i(n+型層)接合部にp型の合金層が作られ
る結果、矢印■の方向に流れる電流は第1図(blの右
の八!・Si合金層15で止められ、反対方向の電流は
同図の左の合金層15で止められるので、A/配線14
は非導通の絶縁状態になり、図示のデバイスはヒユーズ
素子として働く。As a result of the formation of a p-type alloy layer at the A//5i (n+ type layer) junction, the current flowing in the direction of arrow Since the current in the direction is stopped by the alloy layer 15 on the left side of the figure, the A/wiring 14
is in a non-conducting, insulating state, and the illustrated device acts as a fuse element.
コンタクトホール領域のi配線を上記の如く選択的に加
熱すると、当該領域のi配線の表面が平坦化する効果も
ある。Selectively heating the i-wire in the contact hole region as described above also has the effect of flattening the surface of the i-wire in the region.
以上述べてきたように本発明によれば、従来のヒユーズ
が平面的に延在したために占有した面精(第3図に見て
ポリシリコンヒユーズ24の幅Wは20μm程度であっ
たものが、第1同価)にW′で示される5μm程度の幅
に短縮化されて、LSIの築槓化に有効であり、また本
発明のヒユーズ素子は通常の半導体プロセスで形成され
うる利点がある。As described above, according to the present invention, the surface area occupied by the conventional fuse (the width W of the polysilicon fuse 24 was about 20 μm as seen in FIG. 3) due to its planar extension is reduced. The fuse element of the present invention has the advantage that it can be shortened to a width of about 5 μm, indicated by W' (first equivalent), and is effective for building up LSIs, and that the fuse element of the present invention can be formed by a normal semiconductor process.
第1図ta+と山)は本発明実施例断面図、第2図は冗
長回路の構成用、
第3図は従来例平面図である。
第1図において、
11はシリコン基板、
I2はn+型層、
13は 5i02膜、
14はA!!配線、
15はAN −5i合金層、
16はコンタクトホール、
17はレーザパルスである。
代理人 弁理士 久木元 彰
IM代理人 弁理士 大 菅 義 之木餐8月実に馴
ケ使1吏7iaコ
第1図
冗長回路の才1べ閃
第2図
従来例平面図
第3図FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a redundant circuit configuration, and FIG. 3 is a plan view of a conventional example. In FIG. 1, 11 is a silicon substrate, I2 is an n+ type layer, 13 is a 5i02 film, and 14 is A! ! 15 is an AN-5i alloy layer, 16 is a contact hole, and 17 is a laser pulse. Agent Patent Attorney Akira Kuki IM Agent Patent Attorney Yoshinoki Osuga
Claims (1)
を経由して導通をとるアルミニウム配線(14)を形成
してなるヒューズを絶縁状態にするにおいて、アルミニ
ウム配線(14)とn^+型層(12)との接合部のア
ルミニウムを溶融し、当該接合部にp型のアルミニウム
・シリコン合金層(15)を形成してアルミニウム配線
(14)を絶縁状態にすることを特徴とする半導体装置
の製造方法。n^+ type layer (12) formed on p-type semiconductor substrate (11)
In order to insulate a fuse formed by forming an aluminum wiring (14) that conducts electrically via the A method of manufacturing a semiconductor device, characterized in that a p-type aluminum-silicon alloy layer (15) is formed at a junction part to bring an aluminum wiring (14) into an insulating state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19203086A JPH0770599B2 (en) | 1986-08-19 | 1986-08-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19203086A JPH0770599B2 (en) | 1986-08-19 | 1986-08-19 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6348838A true JPS6348838A (en) | 1988-03-01 |
JPH0770599B2 JPH0770599B2 (en) | 1995-07-31 |
Family
ID=16284428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19203086A Expired - Lifetime JPH0770599B2 (en) | 1986-08-19 | 1986-08-19 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0770599B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0655783A1 (en) * | 1993-11-30 | 1995-05-31 | STMicroelectronics S.A. | Fuse for integrated circuit |
JP2015079804A (en) * | 2013-10-15 | 2015-04-23 | 富士電機株式会社 | Semiconductor device |
-
1986
- 1986-08-19 JP JP19203086A patent/JPH0770599B2/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0655783A1 (en) * | 1993-11-30 | 1995-05-31 | STMicroelectronics S.A. | Fuse for integrated circuit |
FR2713398A1 (en) * | 1993-11-30 | 1995-06-09 | Sgs Thomson Microelectronics | Fuse for integrated circuit. |
US5665627A (en) * | 1993-11-30 | 1997-09-09 | Sgs Thomson Microelectronics S.A. | Method of irreversibly locking a portion of a semiconductor device |
US5969403A (en) * | 1993-11-30 | 1999-10-19 | Sgs-Thomson Microelectronics S.A. | Physical fuse for semiconductor integrated circuit |
JP2015079804A (en) * | 2013-10-15 | 2015-04-23 | 富士電機株式会社 | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPH0770599B2 (en) | 1995-07-31 |
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