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JPS6344733A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6344733A
JPS6344733A JP61189097A JP18909786A JPS6344733A JP S6344733 A JPS6344733 A JP S6344733A JP 61189097 A JP61189097 A JP 61189097A JP 18909786 A JP18909786 A JP 18909786A JP S6344733 A JPS6344733 A JP S6344733A
Authority
JP
Japan
Prior art keywords
electrode
wire
package
semiconductor device
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61189097A
Other languages
Japanese (ja)
Inventor
Masataka Mizukoshi
正孝 水越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61189097A priority Critical patent/JPS6344733A/en
Publication of JPS6344733A publication Critical patent/JPS6344733A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/05554—Shape in top view being square
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To raise the packaging density by a method wherein a vertical electrode installed at a package is connected with an electrode installed at a semiconductor chip so that the plane size of a semiconductor device can be reduced. CONSTITUTION:A semiconductor chip 2 is fixed at a concave part 12 of a ceramic package 11. A vertical electrode 13 is formed on a vertical surrounding wall 14 at the concave part 12. In addition, a wire 17 is wired between a part where an electrode 9 on the chip 2 is bonded and another part where the electrode 13 is bonded. Because, according to a semiconductor device 10, the electrode 13 is formed vertically on the surrounding wall 14 at the concave part 12, the plane size of the package 11 can be reduced. Therefore, it is possible to raise the packaging density as compared with the constitution which has been adopted so far.

Description

【発明の詳細な説明】 〔概要） 本発明は半導体装置において、電極をパッケージのうち
半導体チップが収容固着される四部の周壁面に垂直に設
け、電極を配するための平面的なスペースを実質上零と
して小型（ヒを図っＩζちのである。[Detailed Description of the Invention] [Summary] The present invention provides a semiconductor device in which electrodes are provided perpendicularly to the peripheral wall surfaces of the four parts of the package where the semiconductor chip is housed and fixed, and the planar space for arranging the electrodes is substantially reduced. It is small as a top zero (Iζchino).

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置に関する。 The present invention relates to a semiconductor device.

〔従来の技術〕[Conventional technology]

第５図（Ａ）、（Ｂ）は従来の半導体装置の構造を示す
。図中、１はセラミックパッケージ、２は半導体チップ
、３はワイヤ、４は蓋、５はリードである。チップ２は
パッケージ１の凹部６に固定しである。FIGS. 5A and 5B show the structure of a conventional semiconductor device. In the figure, 1 is a ceramic package, 2 is a semiconductor chip, 3 is a wire, 4 is a lid, and 5 is a lead. The chip 2 is fixed in the recess 6 of the package 1.

パッケージ１には、四部６を囲むように段部７が形成し
てあり、この段部７の水平面に電極８が形成しである。A stepped portion 7 is formed in the package 1 so as to surround the four parts 6, and an electrode 8 is formed on the horizontal surface of the stepped portion 7.

ワイヤ３はチップ２上の電極９とパッケージ１上の電極
８との間に接続しである。The wire 3 is connected between the electrode 9 on the chip 2 and the electrode 8 on the package 1.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

パッケージ１には、電極８を配するための平面的な領域
（第５図（Ｂ）中クロスハンチングで示す）が必要とな
り、パッケージ１自体の平面的な寸法Ｌ＋ＸＷ＋はある
程度大きくならざるをえなかった。このため、半導体装
置の平面的なサイズを小形化することが困難であり、半
導体装置の実装密度の向上を図る上で問題があった。The package 1 requires a planar area (indicated by cross-hunting in FIG. 5(B)) for arranging the electrode 8, and the planar dimension L+XW+ of the package 1 itself must be large to some extent. Ta. Therefore, it is difficult to reduce the planar size of the semiconductor device, which poses a problem in improving the packaging density of the semiconductor device.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、凹部内に半導体チップが固定さ
れたパッケージと、 上記凹部の周壁面上に垂直に設けた垂直電極と、上記半
導体チップ上の電極と上記のＩ直ＴＡ極との間を接続す
るワイヤとからなる。The semiconductor device of the present invention includes a package in which a semiconductor chip is fixed in a recess, a vertical electrode provided perpendicularly on a peripheral wall surface of the recess, and a gap between the electrode on the semiconductor chip and the I-direct TA pole. Consists of wires to connect.

〔作用〕[Effect]

垂直電極はこれを配するための平面的なスペースを不要
として、パッケージの平面的なサイズを小型とする。The vertical electrode eliminates the need for a planar space for arranging it, thereby reducing the planar size of the package.

〔実施例〕〔Example〕

第１図（Ａ＞、（Ｂ）は、本発明の一実施例になる半導
体装置１０を示す。図中、第５図（Ａ）。1 (A>, (B)) show a semiconductor device 10 according to an embodiment of the present invention. In the figures, FIG. 5 (A).

（Ｂ）に示す構成部分と同一部分には同一符号を付す。Components that are the same as those shown in (B) are given the same reference numerals.

１１はセラミックパッケージであり、凹部１２が形成し
てあり、ここに半導体チップ２が固定しである。11 is a ceramic package in which a recess 12 is formed, in which the semiconductor chip 2 is fixed.

１３は垂直電極であり、凹部１２の垂直な周壁面１４上
に形成しである。各電極１３は、パッケージ１１内部の
配線１５を介してリード１６と電気的に接続しである。A vertical electrode 13 is formed on the vertical peripheral wall surface 14 of the recess 12. Each electrode 13 is electrically connected to a lead 16 via a wiring 15 inside the package 11 .

なお、ワイヤボンディングを考慮して、電極１３は、周
壁面１４のうち凹部１２の開口に臨む個所に配しである
。Note that, in consideration of wire bonding, the electrode 13 is arranged at a portion of the peripheral wall surface 14 facing the opening of the recess 12.

１７はワイヤであり、デツプ２上の電極９と上記の電極
１３とにボンディングされて両者間に配線しである。A wire 17 is bonded to the electrode 9 on the depth 2 and the electrode 13, and is wired between the two.

１８は、蓋であり、四部１２を被うようにパッケージ１
１に固着してあり、チップ２を気密封止している。18 is a lid, which covers the four parts 12 of the package 1;
1 and hermetically seals the chip 2.

上記構成の半導体装置１０によれば、パッケージ１１の
電極１３は凹部１２の周壁面１４上に垂直に形成しであ
るため、パッケージ１１には、従来、ｆｆｆｌｉを設け
るために形成されていた段部７（第５図（Ａ＞、（Ｂ）
参照）が不要となり、パッケージ１１の平面的な寸法が
小となる。これにより、半導体装置１ｏの長さＬ２．幅
Ｗ２は夫々従来の半導体装置の対応する寸法Ｌ＋、Ｗ＋
に比して小となり、半導体装置１０は平面的なサイズが
従来のものに比べて小となる。従って、この半導体装置
１０によれば、従来のものに比べて実装密度の向上を図
ることが出来る。According to the semiconductor device 10 having the above configuration, the electrode 13 of the package 11 is formed perpendicularly on the peripheral wall surface 14 of the recess 12. 7 (Figure 5 (A>, (B)
) is no longer necessary, and the planar dimensions of the package 11 are reduced. As a result, the length L2 of the semiconductor device 1o. The width W2 is the corresponding dimension L+ and W+ of the conventional semiconductor device, respectively.
Therefore, the planar size of the semiconductor device 10 is smaller than that of the conventional device. Therefore, according to this semiconductor device 10, it is possible to improve the packaging density compared to the conventional device.

次に、上記のチップ２上の水平な電極９及びパッケージ
１１上の垂直電極１３へのワイヤボンディングについて
、第２図（Ａ＞乃至（Ｇ）及び第３図を参照して説明す
る。Next, wire bonding to the horizontal electrode 9 on the chip 2 and the vertical electrode 13 on the package 11 will be described with reference to FIGS. 2A to 3G.

第２図（Ａ）中、２０はウェッジツール、２１は振動子
２２はワイヤクランパである。ウェッジツール２０の先
端には、水平抑圧面２３と、垂直抑圧面２４とが形成し
である。Δｕ、Ａ２等のワイヤ１７は、ツール２０内の
孔２５を通ってツール２０の先端より一部突出している
。In FIG. 2(A), 20 is a wedge tool, and 21 is a vibrator 22, which is a wire clamper. A horizontal suppression surface 23 and a vertical suppression surface 24 are formed at the tip of the wedge tool 20. The wires 17, such as Δu and A2, pass through holes 25 in the tool 20 and partially protrude from the tip of the tool 20.

チップ２が固定されたパッケージ１１は、第２図（Ｄ）
に示すように振動子２６上のワークホルダ２７に固定し
である。The package 11 to which the chip 2 is fixed is shown in FIG. 2(D).
As shown in the figure, it is fixed to a work holder 27 on a vibrator 26.

ワイヤボンディングは、最初に電汚９、次いで垂直電極
１３の順で行なわれる。Wire bonding is performed first on the electrode 9 and then on the vertical electrode 13 in that order.

まず、ツール２０が第２図−（Ａ＞に示す状態で第３図
中■で示すように下降する。これにより、第２図（８）
に示すように、ツール２０がその水平押圧面２３と電極
９との間にワイヤ１７を挾み、振動子２１が駆動して、
ツール２０が矢印Ｉ」で示すように水平方向に例えば周
波数６０ｋＨｚ　、振幅１０μ程度で振動し、ワイヤ１
７の先端が１１極９に超音波ボンディングされる。First, the tool 20 is lowered in the state shown in FIG. 2-(A>) as shown by ■ in FIG.
As shown in FIG. 2, the tool 20 sandwiches the wire 17 between its horizontal pressing surface 23 and the electrode 9, and the vibrator 21 is driven.
The tool 20 vibrates horizontally at a frequency of, for example, 60 kHz and an amplitude of about 10 μ as shown by arrow I, and the wire 1
The tip of 7 is ultrasonically bonded to 11 poles 9.

次いで、ツール２０は、第２図（Ｃ）で示すように、ワ
イヤ１７をツール２０より相対的に繰り出しつつ上昇す
る（第３図中■）。Next, as shown in FIG. 2(C), the tool 20 ascends while letting out the wire 17 relatively from the tool 20 (■ in FIG. 3).

次いで、ツール２０は第３図中■で示すように移動し、
第２図＜Ｄ＞に示すように、垂直押圧面２４と電極１３
との間にワイヤ１７を挾む。振動子２６が駆動して、パ
ッケージ１１がワークホルダ２７と共に矢印Ｖで示すよ
うに垂直方向に上記と同様に例えば周波数６０ｋＨｚで
振動し、ワイヤ１７が垂直の電極１３に超音波ボンディ
ングされる。Next, the tool 20 moves as shown by ■ in FIG.
As shown in FIG. 2 <D>, the vertical pressing surface 24 and the electrode 13
A wire 17 is sandwiched between the two. The vibrator 26 is driven to vibrate the package 11 together with the work holder 27 in the vertical direction as shown by the arrow V at a frequency of 60 kHz, for example, as described above, and the wire 17 is ultrasonically bonded to the vertical electrode 13.

この後、ツール２０は、第３図中■、■で示すように、
電極１３よりワイヤ径程度離れて上昇し、第２図（Ｅ）
に示す状態となる。第３図中■は、ツール２０の上動時
にワイヤボンディングした部分を傷句けないようにする
ためである。この時点でクランパ２２が動作して、ワイ
ヤ１７をクランプする（第２図（Ｆ）参照）。After this, the tool 20, as shown by ■ and ■ in FIG.
It rises from the electrode 13 at a distance of approximately the diameter of the wire, as shown in Fig. 2 (E).
The state shown in is reached. The symbol (■) in FIG. 3 is to prevent the wire bonded portion from being damaged when the tool 20 is moved upward. At this point, the clamper 22 operates to clamp the wire 17 (see FIG. 2(F)).

次いで、ツール２０が第３図中■で示すように右方向に
、即ちパッケージ１１の外方向に移動する。この移動に
より、ツール２０の先端より引き出されている部分のワ
イヤ１７が第２図（Ｆ）に示すように屈曲し、引っ張ら
れて遂には第２図（Ｇ）に示すように、電極１３との接
続部分で切Ｉ！１ｌｉ（所謂ブルカット）されるっ上記
の屈曲は、チップ２上の次の電極９へのボンディングを
し易くするためである。Next, the tool 20 is moved to the right, that is, to the outside of the package 11, as shown by the symbol ■ in FIG. As a result of this movement, the portion of the wire 17 pulled out from the tip of the tool 20 is bent as shown in FIG. 2(F) and pulled, and finally the wire 17 is connected to the electrode 13 as shown in FIG. 2(G). Turn off at the connection part! 1li (so-called bull cut) is made to facilitate bonding to the next electrode 9 on the chip 2.

次いで、ツール２０は第３図中■で示すように、移動し
て、第２図（Ａ）に示す状態となる。Next, the tool 20 moves as shown by ■ in FIG. 3 and enters the state shown in FIG. 2(A).

上記の動作を繰り返すことにより、水平な電極つと垂直
な電極１３とにワイヤボンディングが作業能率良く行な
われる。By repeating the above operations, wire bonding between the horizontal electrode 13 and the vertical electrode 13 can be performed with good work efficiency.

第４図は本発明の半導体装置の別の実施例を示す。これ
は電極数が多い場合の実施例である。FIG. 4 shows another embodiment of the semiconductor device of the present invention. This is an example in which the number of electrodes is large.

半導体装置３０のパッケージ３１には、半導体チップ３
２を囲んで二重に電極３３．３４が設けである。このう
ち、内側の電極３３は、パッケージ３１の凹部３５の周
壁面３６に垂直に形成しである。このように、内側の電
極３３を垂直電極としたことにより、内側の電極及び外
側の電極を共に水平に配した従来の構成に比べて、パッ
ケージ３１（半導体装置３０）の平面的なサイズの小型
化が図られており、実装密度の向上を図り得る。A package 31 of a semiconductor device 30 includes a semiconductor chip 3.
Two electrodes 33 and 34 are provided surrounding the two electrodes. Among these, the inner electrode 33 is formed perpendicularly to the peripheral wall surface 36 of the recess 35 of the package 31. In this way, by making the inner electrode 33 a vertical electrode, the planar size of the package 31 (semiconductor device 30) can be reduced compared to the conventional structure in which both the inner electrode and the outer electrode are arranged horizontally. This makes it possible to improve the packaging density.

３７はワイヤ、３８は蓋である。37 is a wire, and 38 is a lid.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、パッケージ上の電極を配するための平
面的なスペースを実質上零とし１ワ、これによりパッケ
ージの平面的なサイズを小として半導体装置の平面的な
サイズの小型化を図ることが出来、この半導体装置を使
用することにより実装密度の向上を図ることが出来る。According to the present invention, the planar space for arranging electrodes on the package is substantially zero, thereby reducing the planar size of the package and reducing the planar size of the semiconductor device. By using this semiconductor device, it is possible to improve the packaging density.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（Ａ＞、（Ｂ）は夫々本発明になる半導体装置の
一実施例の平面図及び断面図、第２図（△）乃至（Ｇ）
は夫々第１図（Ａ）。 （Ｂ）中のワイヤのボンディングを説明する図、第３図
はワイヤボイングのときのウェッジツールの動きを説明
する図、 第４図は本発明の半導体装置の別の実施例の断面図、 第５図（Ａ）、（Ｂ）は夫々従来の半導体装置の平面図
、断面図である。 図中、 ２．３２は半導体チップ、 ８は電極、 １０．３０は半導体装置、 １１．３１はセラミックパッケージ、 １２．３５は凹部、 １３．３３は垂直電極、 １４．３６は周壁面、 １７．３７はワイヤ、 ２０はウェッジツール、 ２１．２６は撮動子、 ２２はワイヤクランパ、 ２３は水平押圧面、 ２４は垂直抑圧面、 ２５は孔、 ２７はワークホルダである。 ■（導俸昧１ ＣＢ） 木受７３１１乃牛博功囁Ｈ！【示Ｔ図 第１図 ７Ｘヤポレテ〉グーときり−７−１しｔ”＠　９　初耳
１う刃第３図 本年５レーＰＩＦ−、Ｍ澄の別ρ爽υｌ＆ホ↑図第４図 （Ｂ）FIG. 1 (A>, (B) is a plan view and a cross-sectional view, respectively, of an embodiment of a semiconductor device according to the present invention, and FIG. 2 (△) to (G)
are respectively shown in Figure 1 (A). 3 is a diagram illustrating the movement of the wedge tool during wire bowing; FIG. 4 is a sectional view of another embodiment of the semiconductor device of the present invention; 5A and 5B are a plan view and a cross-sectional view, respectively, of a conventional semiconductor device. In the figure, 2.32 is a semiconductor chip, 8 is an electrode, 10.30 is a semiconductor device, 11.31 is a ceramic package, 12.35 is a recess, 13.33 is a vertical electrode, 14.36 is a peripheral wall surface, 17. 37 is a wire, 20 is a wedge tool, 21, 26 is a camera, 22 is a wire clamper, 23 is a horizontal pressing surface, 24 is a vertical suppressing surface, 25 is a hole, and 27 is a work holder. ■(Douhanmai 1 CB) Kiuke 7311 Nogyu Hiroko whisper H! [T figure 1 figure 7 B)

Claims (1)

【特許請求の範囲】 〔１〕凹部（１２、３５）内に半導体チップ（２、３２
）が固定されたパッケージ（１１、３１）と、上記凹部
（１２、３５）の周壁面（１４、３６）上に垂直に設け
た垂直電極（１３、３３）と、上記半導体チップ（２、
３２）上の電極（８）と上記の垂直電極（１３、３３）
との間を接続するワイヤ（１７、３７）とよりなる構成
を特徴とする半導体装置。 〔２〕上記ワイヤ（１７）は、 ウェッジツール（２０）がこれと上記半導体チップ（１
２）上の電極（８）との間に上記ワイヤ（１７）を挟持
し、該ウェッジツール（２０）が水平方向に振動して該
ワイヤ（１７）を上記電極（８）に超音波ボンディング
する工程と、 この後、上記ウェッジツール（２０）がこれと上記垂直
電極（１３）との間に上記ワイヤ（１７）を挾持し、上
記パッケージ（１１）が垂直方向に振動して該ワイヤ（
１７）を上記垂直電極（１３）に超音波ボンディングす
る工程と、 この後上記ワイヤ（１７）をクランプし、上記ウェッジ
ツール（２０）を上記パッケージ（１１）の外方向に移
動させて上記ワイヤ（１７）をブルカットする工程とに
より、 上記半導体チップ（２）上の電極（８）と上記垂直電極
（１３）との間に接続されてなることを特徴とする特許
請求の範囲第１項記載の半導体装置。[Claims] [1] Semiconductor chip (2, 32) in recess (12, 35)
) to which the package (11, 31) is fixed, the vertical electrode (13, 33) provided perpendicularly on the peripheral wall surface (14, 36) of the recess (12, 35), and the semiconductor chip (2,
32) Above electrode (8) and above vertical electrode (13, 33)
A semiconductor device characterized by a configuration consisting of wires (17, 37) connecting between the two. [2] The wire (17) is connected to the semiconductor chip (1) by a wedge tool (20).
2) The wire (17) is held between the upper electrode (8) and the wedge tool (20) vibrates in the horizontal direction to ultrasonically bond the wire (17) to the electrode (8). After this, the wedge tool (20) clamps the wire (17) between it and the vertical electrode (13), and the package (11) vibrates vertically to release the wire (
17) to the vertical electrode (13), after which the wire (17) is clamped and the wedge tool (20) is moved outward of the package (11) to bond the wire (17) to the vertical electrode (13); 17) is connected between the electrode (8) on the semiconductor chip (2) and the vertical electrode (13) by bull-cutting the semiconductor chip (17). Semiconductor equipment.
JP61189097A 1986-08-12 1986-08-12 Semiconductor device Pending JPS6344733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61189097A JPS6344733A (en) 1986-08-12 1986-08-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61189097A JPS6344733A (en) 1986-08-12 1986-08-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6344733A true JPS6344733A (en) 1988-02-25

Family

ID=16235295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61189097A Pending JPS6344733A (en) 1986-08-12 1986-08-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6344733A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793104A (en) * 1996-02-29 1998-08-11 Lsi Logic Corporation Apparatus for forming electrical connections between a semiconductor die and a semiconductor package
WO2016070211A1 (en) * 2014-11-05 2016-05-12 Zizala Lichtsysteme Gmbh Method and device for connecting a wire
US10290603B2 (en) 2016-11-10 2019-05-14 Mitsubishi Electric Corporation High-frequency circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793104A (en) * 1996-02-29 1998-08-11 Lsi Logic Corporation Apparatus for forming electrical connections between a semiconductor die and a semiconductor package
WO2016070211A1 (en) * 2014-11-05 2016-05-12 Zizala Lichtsysteme Gmbh Method and device for connecting a wire
US10290603B2 (en) 2016-11-10 2019-05-14 Mitsubishi Electric Corporation High-frequency circuit

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