JPS6338260A - High breakdown strength semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Use Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Schematic diagram of the embodiments (Fig. 1) Carrier Concentration profile diagram (Fig. 2) Process cross-sectional view of the embodiment (Fig. 3) Effects of the invention [Summary] A gate is formed using a narrow enhancement region formed using a DSA (diffusion self-alignment) method and a depletion region. This is an offset-type high voltage element that reduces on-resistance and increases the amplification factor by configuring the device. By doing so, it is possible to form the source region, the enrichment channel region, the depletion region, the offset region, and the drain all by self-line, and also to interpose the above-mentioned isolation insulating film between the offset region and the gate electrode. This aims to improve the drain-gate breakdown voltage.

[Industrial application field]

The present invention relates to an MIS type high breakdown voltage semiconductor device and an improvement in its manufacturing method, and more particularly to an 11LS type high breakdown voltage semiconductor device and a manufacturing method thereof, which are aimed at improving the degree of integration and drain-to-gate breakdown voltage.

Recently, the demand for semiconductor ICs equipped with control circuits for high-voltage drive devices such as display devices such as electroluminescence and plasma displays has increased, and the scale of the high-voltage drive devices has increased. With the increasing functionality and speed, there is a demand for semiconductor devices constituting control circuits to have higher voltage resistance, higher power, higher speed, and an increased amplification factor.

[Conventional technology]

FIG. 4 is a schematic side sectional view showing an example of a typical structure of a conventional MIS type high breakdown voltage semiconductor device, ie, a high breakdown voltage MIS l-run transistor.

In the figure, 51 is an n-type well, 52 is a field oxide film, 53 is an n-'' liner stopper, 54 is a gate oxide film, 55 is a gate electrode, 56 is a p-type offset region, and 57 is a p' source. 58 is a P drain region, 59 is an oxide film for impurity blocking, 60 is an interlayer insulating film, 61 is a source wiring, 62 is a gate wiring, and 63 is a drain wiring.

As shown in the figure, in the conventional structure, the channel forming portion ch
An offset region 56 having a low impurity concentration and high resistance is disposed between the drain region 58 and the drain region 58, and the drain breakdown voltage is improved by increasing the spread of the depletion layer near the drain.

However, this structure included the following problems.

In other words, 1) In order to achieve even higher voltage resistance, off-separation]・
Length of area 56. Since it is necessary to lengthen F, the element area increases.

2) By increasing the length of 10F, its resistance value increases, so the amplification factor (β) decreases and the operating speed decreases.

3) Since the conductance decreases by lengthening the I-OF, the width of the offset region must be increased in order to drive large power, which further increases the device area.

4) Since the channel region is formed to match the width of the gate electrode defined by the limits of lithography technology, it is difficult to make a short channel, and it is difficult to achieve high speed and high β.

5) Since it is an enhancement type, the on-resistance is high, making it possible to achieve high power and high β.

etc.

Therefore, as a structure to solve the above problem, the inventor previously proposed in Japanese Patent Application No. 61-118506 an offset type structure having a diffusion self 7 line (DS8) enhancement gate and a depletion gate as shown in FIG. We proposed a high-voltage semiconductor device.

In the figure, reference numeral 64 denotes a p''-type depletion region, and reference numeral 65 denotes a p''-type depletion region. Before forming the source region 57, impurities are introduced into the source formation region side in alignment with the D1-electrode, and the depletion region 64 is formed with a predetermined width W (channel length Lch). Carrier concentration 10 formed by performing drive-in processing so as to invert by
The n-type region 66 of about "~10I9cA-" is an inversion region having a width W (LCh) of about 0.2 to 0.5 μm and is an enhancement type channel region, and the other regions have the same symbols as in FIG. is shown.

In this structure, the offset portion between the drain region 58 and the channel region 66 is
an offset region 56 having a low concentration provided between the gate and the gate;
and a depletion region 64 of lower concentration provided below the gate, and this depletion region 64 has a very high resistance when no gate voltage is applied, so that the depletion region 64 and the enhancement type channel region 66 have a high resistance. The potential of the contact portion is significantly lowered, and a drain breakdown voltage higher than that of the conventional structure shown in FIG. 4 is obtained.

In addition, during operation, that is, when gate voltage is applied, the width W of the enhancement region corresponding to the channel length LCh is formed to be extremely narrow due to lateral diffusion of impurities, and the depletion region becomes a low resistance region. The on-resistance is significantly reduced and the drive current is increased, producing the effect that I and β are also different from each other.

[Problem that the invention seeks to solve]

However, a problem with this structure is that while the source region, enhancement region, depletion region, and offset region can all be formed with self-aligned lines, only the drain region cannot be formed with self-aligned lines. Secondly, the element area could not be reduced sufficiently, and the insulation between the offset region near the 1-rain region and the gate electrode was made only by a thin gate insulating film and an impurity blocking insulating film. A high density electric field concentration occurred between the gate electrode and the offset region, and the dielectric strength between the drain and the gate could not be sufficiently adjusted.

[Means for solving problems]

The above problem is caused by a semiconductor substrate (2) of one conductivity type and an insulating film for element isolation (!J) formed on the surface of the semiconductor substrate (2).
a) (9b) and the element isolation insulating film (9a) (9
The element isolation insulating film (9a
) (9b) and a pair of active region isolation insulating films (10a) (10b) formed apart from each other.
, an opposite conductivity type source region (15) formed on the substrate surface defined by the active region isolation insulating film (10a) and the element isolation insulating film (9a) on one side, and the active region on the other side. Isolation insulating film (10b) and element isolation insulating film (9
The insulating film (1G) is formed under the active region isolation insulating film (10a) on the opposite conductivity type drain region (1G) formed on the substrate surface defined by b) and the source region (15).
0a) and is formed along and in contact with the bottom surface of the source region (
15) and the active region (11), a high concentration region (7) of an opposite conductivity type having a carrier concentration equal to or higher than that of the source region (15), and the high concentration region (7) of the opposite conductivity type. an impurity-introduced region (5) of one conductivity type with higher carrier concentration than the base (2) formed along and in contact with the bottom surface of the high concentration region (7) of the opposite conductivity type, and the drain region (16). (10b) of the side active region isolation insulating film
At the bottom, a first opposite conductivity type low concentration region (8) is formed along and in contact with the bottom surface of the insulating film (10h) and has a lower gear concentration than the drain region (16) which communicates between the drain region and the active region. ) and the first opposite conductivity type low concentration region (
8) and a second opposite conductivity region having a lower carrier concentration than the first opposite conductivity type low concentration region (8) formed on the surface of the active region (11) between the one conductivity type impurity introduction region (5) and the first opposite conductivity type low concentration region (8). a type low concentration region (12), a gate insulating film (13) formed on the active region (11), and the active region isolation insulating film (10a) (10b) on the gate insulating film (13). A high voltage semiconductor device according to the present invention has a gate electrode (14) extending upwardly, and a semiconductor substrate of one conductivity type, on a source formation region, on a drain formation region, and on a source formation region. first, second, and third oxidation-resistant film patterns each individually covering the active region formation region provided between the drain region and the active region formed in a spaced manner;
a step of simultaneously forming the first mask in alignment with the same mask;
Impurities are selectively introduced in alignment with the gap between the oxidation-resistant film pattern and the third oxidation-resistant film pattern, so that the substrate surface in the gap has a higher impurity concentration than the substrate and the source/drain regions. A step of forming an impurity-introduced region of one conductivity type having a lower impurity concentration, and a step of forming a surface portion of the high concentration region of one conductivity type in alignment with the gap between the first oxidation resistant film pattern and the third oxidation resistant film pattern. selectively introducing impurities of the opposite conductivity type to a concentration equal to or higher than that of the source/drain regions, and aligning the impurities with the gap between the third oxidation resistant film pattern and the second oxidation resistant film pattern. selectively on the base surface in the gap,
a step of introducing an opposite conductivity type impurity at a higher concentration than the substrate and at a lower concentration than the source/drain region;
By selective oxidation using the third oxidation resistant film pattern as a mask, an oxide film for element isolation is formed on the outside of the first and second oxidation resistant film patterns, and also on the first, second, and third oxidation resistant film patterns. An active region isolation oxide film is formed in the gap, and the introduced impurity is activated to form an opposite conductivity type oxide film along and in contact with the bottom surface of the isolation oxide film under the active region isolation oxide film on the source region side. An impurity-introduced region of one conductivity type along and in contact with the bottom surface of the high concentration region and the high concentration region of the opposite conductivity type, and a doped region along the bottom surface of the isolation oxide film under the active region isolation oxide film on the drain region side. forming contacting first low concentration opposite conductivity type regions, and forming first low concentration regions on the active region forming surface.
forming a gate insulating film on the active region; -11 to the active region isolation oxide film 1D, and the process of introducing impurities in alignment with the gap between the element isolation oxide film and the active region isolation oxide film 1D to form a gate electrode of the opposite conductivity type. One L forming the source region and train region
The problem is solved by a method of manufacturing a high voltage semiconductor device according to the present invention, which includes steps and three.

[For production]

That is, in the MTS type high breakdown voltage semiconductor device with an offset structure in which I) SA enhancement gate and debris: 'y', IJn y-1, according to the present invention, By creating a structure in which the drain region is separated and defined by a thick insulating film that is formed at the same time as the element isolation insulating film, the source region, The enhancement channel region, the depletion region, the offset region 1-region, and the drain wiring can all be formed using self-aligned lines, thereby achieving high integration of the device. In addition, the offset region is arranged under the active region isolation insulating film. between the offset region and the gate electrode.
By interposing a thick insulating film for separating the active region, electric field concentration can be alleviated and the withstand voltage between the drain and the gate 1 can be improved.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view showing an embodiment of the structure of a high voltage semiconductor device according to the present invention, FIG. 2 is an impurity concentration profile diagram between the source and drain in the same embodiment, and FIG. hl is a process sectional view showing an example of the manufacturing method.

Objects that are the same throughout the drawings are indicated by the same reference numerals.

In FIG. 1 showing an embodiment of the structure according to the present invention, 1
is a p-type silicon substrate (ρ-3uh), 2 is an n-type well with a carrier concentration of about IQ I S cm -3, which is a conductivity type substrate, and 5 is a carrier concentration of about 101Ilc13, which forms an enhancement channel, and the depth 0.5~
The n-type region 6 of about I μm is an n-type channel stopper,
7 is a p" type source extension region with a carrier concentration of 1020 cffl-3 or more and a depth of about 0.3 to 0.5 μm; 8 is a p" type source extension region with a carrier concentration of about 1017 cm-3 and a depth of 0.3 to 0.5 μm.
p-type offset 1-region of about 1 to 0.3 μm; 9a and 9b are element isolation oxide films of about 0.5 to 0.6 μm; 10a and 10b are about 0.5 to 0.6 μm thick. 11 is an active region, 12 is a carrier concentration I Q '' cm −3, depth 0.1 to 0.2
A p-type depletion region of about μm, I3 a gate oxide film, 14 a gate electrode made of polycrystalline Si, etc., 15 a carrier concentration of 1 Q 20 cm-3, and a depth of 0.3 to 0.
．． p source region of about 5 μm, 16 is a p source region with a carrier concentration of 1020 µm,
The 'type drain region 17 is an oxide film for impurity blocking with a thickness of about 0.1 μm, 18 is a phosphosilicate glass (PSG) interlayer insulating film, 19 is a gate wiring made of aluminum or the like, 2
0 is the same source wiring, 21 is the same drain wiring, 2
2 indicates an enhancement channel region.

As shown in this embodiment, in the p-channel type high breakdown voltage semiconductor device according to the present invention, the active region 11 under the gate
A thick active region isolation oxide film (insulating film) 1 is formed simultaneously with the element isolation oxide films (insulating films) 9a and 9b between the p° type source region 15 and the p° type drain region 16.
0a and 10b are provided, and in order to conduct the source region 15 and the active region 11, a p source extension region 7 with a high carrier concentration and low series resistance is provided under the active region isolation oxide film 10a on the source side. , are disposed in contact with the bottom surface of the oxide film 10a. In the lower part thereof, along and in contact with the source extension region 7, a channel length L (h
An enhancement type n-type region 5 whose width is defined is provided.

In addition, oxide film 10b for active region isolation in 16 drain regions
A p-type offset region 8 is provided below the drain region 16 and the active region 1, and serves as a conduction region between the drain region 16 and the active region 1, and the edge of the offset HJ region 8 in the active region 1 and the n-type region between the end of the p-
It has a structure that is communicated by a mold depletion region 12.

For reference, FIG. 2 is an impurity concentration profile diagram between the source and drain schematically showing the carrier concentration in each region in the above example. In the figure, Nc is the carrier concentration, l
-5o indicates the distance from the source region to the drain region.

The high voltage semiconductor device according to the present invention is formed, for example, by the manufacturing method described below with reference to FIGS. 3 fat to fhl and FIG. 1.

Refer to Fig. 3 fa+, that is, first, p
A thin thermal oxide film for buffering, that is, a base oxide film 3, is formed on one surface of a type silicon substrate (P-5UB) by a normal method, and then an oxidation-resistant film is formed on the base oxide film 3 by a chemical vapor deposition (CVll) method. A first 5iJ4 film pattern 4a is formed by forming a silicon nitride (Si:IN) film, which is a film, and patterning it by ordinary lithography using one mask to cover the region where the source region is to be formed. and a second 5iJa film pattern 4b covering the region where the source region and the drain region are formed, and a third Si3N4 film covering the region where the active region is formed, which is provided between the source region and the drain region and spaced therefrom. Form Bakun 4c.

Next, n-type impurities are added to the Si:IN, films 4a, 4b, 4.
The n-type well 2 having a carrier concentration of about 10''c+n-3 is formed by selectively introducing energy through injection into the base oxide film 3 and performing a heat treatment.

FIG. 3 (See BL) Next, a first resist mask RM having an opening on the substrate that selectively exposes the gap between the first Si3N4 film pattern 4a and the third Si3N4 film pattern 4c.

, forming an opening in the resist mask RM and
For example, phosphorus (P') is ion-implanted into one surface of the substrate through the gap between the i+Na film patterns 4a and 40, and after removing the resist mask RM, a driving process is performed at, for example, 1000° C. for about 60 minutes. Carrier concentration IQ11Ic
An n-type region 5 with a depth of about 0.5 to 1 μm is formed. An enhancement channel is formed on the surface of the substrate after this n-type region 5.

Note that the depth of the n-type region is controlled so that the difference from the depth of the source extension region formed in a later step becomes the required channel length.

Referring to FIG. 3(C), a P+ implantation region 106 for an n-type channel stopper is selectively placed on one surface of the well using a resist mask (not shown).
After forming, a second resist mask RM having openings similar to those of the first resist mask RM+ is formed on the substrate, and the openings of the second resist mask RM and the Si3N4 film pattern are Through the gap between 4a and 4c, boron (B) ions are implanted to a high concentration on the 5th surface of the n-type region (1074; t: n'' high-concentration implantation region). The carrier concentration after distribution is adjusted to a value equal to or higher than that of the source region.

Note that either the channel stopper P1 implantation or the B' high concentration implantation may be performed first.

FIG. 3 (d+) After removing the reference resist mask RMz, a third resist mask RM3 having an opening that selectively exposes the gap between the 5iJ4 film pattern 4c and the Si3N4 film pattern 4b is formed on the substrate. 10'6 at the time of activation and redistribution of B' onto the surface of the substrate through the opening of the resist mask RM and the gap between the 5isN4 film patterns 4c and 4b.
Ions are implanted at a dosage such that a carrier concentration of about 10'7 -3 is obtained. Note that 108 is a large B-note region which becomes an offset region after activation redistribution.

The offset B injection region 108 may be formed at the same time as the channel stopper B injection region on the substrate side (not shown).

Refer to FIG. 3. Then, by using the Si:+Nn film patterns 4a, 4b, and 4C as masks, a normal selective oxidation process is performed at about 900°C.
Element isolation oxide films 9a and 9b and active region isolation oxide films 10a and 10b are formed on one surface of the substrate. At the same time, the n high concentration implantation region IQT under the active region isolation oxide film 10a is activated and redistributed to increase the carrier concentration IQ.
2' cm −', depth of about 0.3 to 0.5 μm
A +-type source extension region 7 and an n-type region 5 with a width of about 0.5 to 111 m surrounding the P-type source extension region 7 are formed, and an oxide film 101 for active region isolation and an oxide film 101 for element isolation are formed. Activate and redistribute the n-input region 108 under the oxide film 9h, carrier concentration 101b to 10I7cn+-',
A p-type offset region 8 having a depth of about 0.1 to 083 μm is formed. At this time, an n-type channel strike collar (i) is also formed at the same time.

Here, the p-type offset DJ region 8 under the element isolation oxide film 9b must be formed apart from the n-type channel stopper 6 in order to ensure breakdown voltage.

Refer to FIG. 3() Next, after removing the 5iJn film patterns 4a, 4b, 4c and the base oxide film 3, a gate oxide film 13 is formed.
A fourth resist mask RM4 having an opening exposing the gap between the active region isolation oxide films 10a and 10b, that is, the active region 11, is formed on the substrate, and the resist mask R)
14 holes, R゛ was selectively implanted at a low concentration,
The resist mask RM4 is removed and a necessary activation heat treatment is performed to form a carrier concentration of 1016 cm-3 on the active region surface between the n-type region and the p-type offset lfJ region 8.
A p-type depletion region 12 having a depth of about 0.1 to 0.2 pm is formed.

Referring to FIG. 3, the active region 11 having the gate oxide film 13 is then oxidized for isolation by a conventional method.
For example, a polycrystalline Si gate electrode 14 is formed extending onto 0b.

FIG. 3 (see hl) Next, the gate electrode 14 and the active region isolation oxide film 10a.
, 10b, using the element isolation oxide films 9a and 9b as a mask, B' is ion-implanted at a high concentration, and the required activation process is performed to form a p' source region 15 and a p'' type drain region 16.
Form.

Refer to Figure 1. Next, the source and drain regions 15.
After removing the same material as the gate oxide film 13, the surface of the electrode 14 and the source,
An impurity blocking oxide film 17 is formed on the surface of the drain region 15, 16, a PSG interlayer insulating film 18 is formed on the substrate by CVO method, and a gate electrode is formed on the PSC interlayer insulating film 18 and the impurity blocking oxide film 17. 14. Form a contact window for the source region 15 and drain region 16, and form a gate wiring 19 made of aluminum or the like, a source wiring 20, a drain wiring fa 21, etc. on the PSG interlayer insulating film 18 and connected to each region in the contact window. After that, a cover insulating film (not shown) is formed, and the p-channel type high voltage semiconductor device according to the present invention is completed.

In the p-channel type high-voltage semiconductor device shown in the above embodiment, the offset portion between the drain region 16 and the enhancement channel region 22 is located between the offset region 8 disposed between the drain region 16 and the gate, and the offset portion between the drain region 16 and the enhancement channel region 22. and a depletion region 12 provided in the
Since this depletion region 12 has a very high resistance in the state where no voltage is applied, the enhancement channel region 22 of the depletion region 12
A high drain breakdown voltage can be obtained by significantly lowering the potential at the contact point with the drain.

In addition, during operation, that is, when applying a gate voltage, the n-type region 5 corresponding to the channel length I-ch in the DSA method
Since the width of the (enhancement H1 region) can be formed extremely narrow and the depletion region functions as a low resistance region, the on-resistance is significantly reduced and the operating speed and drive current are increased.

In addition to the above, source region 15 and drain region 1
6 and the active region 11 under the gate are covered with thick insulating films 9a, 9.
By separating the source region 15 and the source extension region 7 through the active region isolation oxide films 9a and 9b and their formation process, as is clear from the above description of the manufacturing method,
, the enhancement channel region 22, the depletion region 12, the offset region 8, and the drain region 16 are all formed by self-alignment, so that the drain region 1
6 and the offset region 8 are no longer required, and the degree of device integration can be improved compared to the conventional structure in which the train region could not be formed by self-line.

Further, since the offset region 8 is provided under the active region isolation oxide film 9b, a thick oxide film of about 0.5 to 0.6 μm is interposed between the offset region 8 and the gate electrode 14. The electric field density therebetween is relaxed, and the withstand voltage between the drain regions 1 and 1 is greatly reduced.

In the examples, the structure and manufacturing method of the present invention have been described with respect to a p-channel type element formed in an n-type impurity well using an n-type substrate, but the element may also be formed directly on the n-type substrate. .

Furthermore, the present invention is of course applicable to n-channel type devices and CMOS devices.

〔Effect of the invention〕

As explained above, according to the present invention, it has high speed, high current drive capability, high amplification factor, and high drain-gauge 1.
- An effect is produced in that it becomes possible to form a Mis-type high voltage semiconductor device having a high voltage breakdown voltage with a high degree of integration using an all-self line.

[Brief explanation of the drawing]

FIG. 1 is a schematic side sectional view of one embodiment of the structure of the present invention, FIG. 2 is a carrier concentration profile diagram between the source and drain in the embodiment, and FIG. 3 (al~+h+ is one of the manufacturing methods according to the present invention) 4 is a side sectional view of a conventional Mis-type high-withstanding high-voltage semiconductor device; FIG. 5 is a schematic side view of a conventional DSA enhancement gate/depletion gate-type MrS high-voltage semiconductor device. This is a cross-sectional view. In the figure, ① is a p-type silicon substrate (p-sub), 2 is an n-type well, 3 is a thermal oxide film for buffering, 4a, 4b, 4c are Si.N. film patterns, 5 7 is a p-type source extension region; 8 is a p-type offset region; 9a and 9b are oxides for element isolation; 10a and 10b are for active region isolation. 11 is an active region, 12 is a p-type depletion region, 13 is a gate oxide film, 14 is a gate electrode, 15 is a p9-type source region, 16 is a p-type drain region 22 is an enhancement channel region. Opening RG3-382GO (10) Otsu a

Claims (1)

[Claims] 1. A semiconductor substrate (2) of one conductivity type, an insulating film for element isolation (9a) (9b) formed on the surface of the semiconductor substrate (2), and an insulating film for element isolation ( A pair of active region isolation insulating films (10a) (10b) formed on the region plane defined by 9a) and (9b), spaced apart from the element isolation insulating films (9a) and (9b), and spaced apart from each other. ), an opposite conductivity type source region (15) formed on the substrate surface defined by the active region isolation insulating film (10a) and the element isolation insulating film (9a) on one side, and the active region on the other side. Insulating film for region isolation (10b) and insulating film for element isolation (9b)
An insulating film (10a) is formed under the active region isolation insulating film (10a) on the opposite conductivity type drain region (16) and the source region (15) side, which are formed on the substrate surface defined by
) is formed along and in contact with the bottom surface of the source region (15
) and the active region (11).
a high concentration region (7) of opposite conductivity type having a carrier concentration equal to or higher than 5); An impurity-introduced region (5) of one conductivity type with a higher carrier concentration than the substrate (2) formed in contact with the substrate (2), and (
10b) A first opposite conductivity type low concentration region formed in the lower part along and in contact with the bottom surface of the insulating film (10b) and having a carrier concentration lower than that of the drain region (16) communicating between the drain region and the active region. (8), and the first opposite conductivity type formed in the surface portion of the active region (11) between the first opposite conductivity type low concentration region (8) and the one conductivity type impurity introduction region (5). a second opposite conductivity type low concentration region (12) having a lower carrier concentration than the low concentration region (8); and a gate insulating film (13) formed on the active region (11).
), and the active region isolation insulating film (13) is on the gate insulating film (13).
10a) A high-voltage semiconductor device comprising: a gate electrode (14) extending upward from (10b); 2. On the semiconductor substrate of one conductivity type, a first layer that individually covers the source formation region, the drain formation region, and the active region formation region provided between the source region and the drain region apart from these regions. , a step of simultaneously forming second and third oxidation resistant film patterns in alignment with the same mask; a first step of introducing an impurity into the substrate surface of the gap to form an impurity-introduced region of one conductivity type having a higher carrier concentration than the substrate and a lower carrier concentration than the source/drain region; In alignment with the gap between the oxidation-resistant film pattern and the third oxidation-resistant film pattern, impurities of the opposite conductivity type are selectively applied to the surface of the high concentration region of one conductivity type at a concentration equal to or higher than that of the source/drain region. Aligning with the gap between the third oxidation resistant film pattern and the second oxidation resistant film pattern, selectively applying it to the substrate surface in the gap at a higher concentration than the substrate and in the source/drain region. A step of introducing impurities of opposite conductivity type at a lower concentration, and element isolation outside the first and second oxidation resistant film patterns by selective oxidation using the first, second and third oxidation resistant film patterns as masks. An oxide film for active region isolation is formed in the gap between the first, second, and third oxidation-resistant film patterns, and the introduced impurities are activated to separate the active region on the source region side. At the bottom of the oxide film, there is a high concentration region of opposite conductivity type along and in contact with the bottom surface of the isolation oxide film, and an impurity-introduced region of one conductivity type along and in contact with the bottom surface of the high concentration region of opposite conductivity type, and a region on the drain region side. forming first low concentration opposite conductivity type regions along and in contact with the bottom surface of the isolation oxide film under the active region isolation oxide film; and forming first low concentration opposite conductivity type regions on the active region forming surface. A step of introducing an impurity of an opposite conductivity type at a concentration lower than that of the active region and at a concentration that reverses the substrate surface of the region, forming a gate insulating film on the active region, and forming a gate insulating film from above the gate insulating film for isolation of the active region. A step of forming a gate electrode extending onto the oxide film, and forming a source region and a drain region of opposite conductivity type by introducing impurities in alignment with the gap between the oxide film for element isolation and the oxide film for active region isolation. A method of manufacturing a high voltage semiconductor device, comprising the steps of: